I'm not sure the assembler checks predicates. The MC tests for FMA and AVX don't seem to specifically enable FMA or AVX.<br><br><div class="gmail_quote">On Sat, Jun 23, 2012 at 2:23 PM, Bruno Cardoso Lopes <span dir="ltr"><<a href="mailto:bruno.cardoso@gmail.com" target="_blank">bruno.cardoso@gmail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Can't you write a llvm-mc (e.g. assembler) based test that checks for<br>
a specific processor feature?<br>
<div class="HOEnZb"><div class="h5"><br>
On Sat, Jun 23, 2012 at 5:52 PM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:<br>
> I can't write a test case because the instructions themselves don't have<br>
> patterns declared in them.<br>
><br>
><br>
> On Sat, Jun 23, 2012 at 1:29 PM, Bruno Cardoso Lopes<br>
> <<a href="mailto:bruno.cardoso@gmail.com">bruno.cardoso@gmail.com</a>> wrote:<br>
>><br>
>> Hi Craig,<br>
>><br>
>> Testcase?<br>
>><br>
>> On Sat, Jun 23, 2012 at 5:15 PM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>><br>
>> wrote:<br>
>> > Author: ctopper<br>
>> > Date: Sat Jun 23 15:15:42 2012<br>
>> > New Revision: 159086<br>
>> ><br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=159086&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=159086&view=rev</a><br>
>> > Log:<br>
>> > Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and<br>
>> > PD2DQ to the SSE2 section of the file.<br>
>> ><br>
>> > Modified:<br>
>> > llvm/trunk/lib/Target/X86/X86InstrFormats.td<br>
>> > llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td<br>
>> > URL:<br>
>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=159086&r1=159085&r2=159086&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=159086&r1=159085&r2=159086&view=diff</a><br>
>> ><br>
>> > ==============================================================================<br>
>> > --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)<br>
>> > +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Sat Jun 23 15:15:42<br>
>> > 2012<br>
>> > @@ -366,6 +366,7 @@<br>
>> > //<br>
>> > // SDI - SSE2 instructions with XD prefix.<br>
>> > // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.<br>
>> > +// SSDI - SSE2 instructions with XD prefix.<br>
>> > // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.<br>
>> > // PDI - SSE2 instructions with TB and OpSize prefixes.<br>
>> > // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize<br>
>> > prefixes.<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
>> > URL:<br>
>> > <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=159086&r1=159085&r2=159086&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=159086&r1=159085&r2=159086&view=diff</a><br>
>> ><br>
>> > ==============================================================================<br>
>> > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
>> > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Jun 23 15:15:42 2012<br>
>> > @@ -1855,6 +1855,36 @@<br>
>> > (memop addr:$src)))],<br>
>> > IIC_SSE_CVT_PS_RM>;<br>
>> ><br>
>> > +// Convert Packed Double FP to Packed DW Integers<br>
>> > +let Predicates = [HasAVX] in {<br>
>> > +// The assembler can recognize rr 256-bit instructions by seeing a ymm<br>
>> > +// register, but the same isn't true when using memory operands<br>
>> > instead.<br>
>> > +// Provide other assembly rr and rm forms to address this explicitly.<br>
>> > +def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > + "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +def VCVTPD2DQXrYr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR256:$src),<br>
>> > + "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>,<br>
>> > VEX;<br>
>> > +<br>
>> > +// XMM only<br>
>> > +def VCVTPD2DQXrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > + "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > f128mem:$src),<br>
>> > + "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +<br>
>> > +// YMM only<br>
>> > +def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR256:$src),<br>
>> > + "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,<br>
>> > VEX;<br>
>> > +def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > f256mem:$src),<br>
>> > + "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,<br>
>> > VEX, VEX_L;<br>
>> > +}<br>
>> > +<br>
>> > +def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > f128mem:$src),<br>
>> > + "cvtpd2dq\t{$src, $dst|$dst, $src}", [],<br>
>> > + IIC_SSE_CVT_PD_RM>;<br>
>> > +def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > + "cvtpd2dq\t{$src, $dst|$dst, $src}", [],<br>
>> > + IIC_SSE_CVT_PD_RR>;<br>
>> > +<br>
>> > // SSE2 packed instructions with XD prefix<br>
>> > def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > "vcvtpd2dq\t{$src, $dst|$dst, $src}",<br>
>> > @@ -1992,6 +2022,13 @@<br>
>> > "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],<br>
>> > IIC_SSE_CVT_PD_RM>, VEX, VEX_L;<br>
>> ><br>
>> > +let Predicates = [HasAVX] in {<br>
>> > + def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),<br>
>> > + (VCVTTPD2DQYrr VR256:$src)>;<br>
>> > + def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),<br>
>> > + (VCVTTPD2DQYrm addr:$src)>;<br>
>> > +} // Predicates = [HasAVX]<br>
>> > +<br>
>> > // Convert packed single to packed double<br>
>> > let Predicates = [HasAVX] in {<br>
>> > // SSE2 instructions without OpSize prefix<br>
>> > @@ -2038,6 +2075,52 @@<br>
>> > IIC_SSE_CVT_PD_RM>,<br>
>> > TB, Requires<[HasSSE2]>;<br>
>> ><br>
>> > +// Convert Packed DW Integers to Packed Double FP<br>
>> > +let Predicates = [HasAVX] in {<br>
>> > +def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > i64mem:$src),<br>
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins<br>
>> > i128mem:$src),<br>
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins<br>
>> > VR128:$src),<br>
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > +}<br>
>> > +<br>
>> > +def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > i64mem:$src),<br>
>> > + "cvtdq2pd\t{$src, $dst|$dst, $src}", [],<br>
>> > + IIC_SSE_CVT_PD_RR>;<br>
>> > +def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > + "cvtdq2pd\t{$src, $dst|$dst, $src}", [],<br>
>> > + IIC_SSE_CVT_PD_RM>;<br>
>> > +<br>
>> > +// 128 bit register conversion intrinsics<br>
>> > +let Predicates = [HasAVX] in<br>
>> > +def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),<br>
>> > + (VCVTDQ2PDrr VR128:$src)>;<br>
>> > +<br>
>> > +let Predicates = [HasSSE2] in<br>
>> > +def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),<br>
>> > + (CVTDQ2PDrr VR128:$src)>;<br>
>> > +<br>
>> > +// AVX 256-bit register conversion intrinsics<br>
>> > +let Predicates = [HasAVX] in {<br>
>> > + def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),<br>
>> > + (VCVTDQ2PDYrr VR128:$src)>;<br>
>> > + def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64<br>
>> > addr:$src))),<br>
>> > + (VCVTDQ2PDYrm addr:$src)>;<br>
>> > +<br>
>> > + def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),<br>
>> > + (VCVTPD2DQYrr VR256:$src)>;<br>
>> > + def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),<br>
>> > + (VCVTPD2DQYrm addr:$src)>;<br>
>> > +<br>
>> > + def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),<br>
>> > + (VCVTDQ2PDYrr VR128:$src)>;<br>
>> > + def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),<br>
>> > + (VCVTDQ2PDYrm addr:$src)>;<br>
>> > +} // Predicates = [HasAVX]<br>
>> > +<br>
>> > // Convert packed double to packed single<br>
>> > // The assembler can recognize rr 256-bit instructions by seeing a ymm<br>
>> > // register, but the same isn't true when using memory operands<br>
>> > instead.<br>
>> > @@ -4867,93 +4950,6 @@<br>
>> > "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>,<br>
>> > XS;<br>
>> ><br>
>> ><br>
>> > //===---------------------------------------------------------------------===//<br>
>> > -// SSE3 - Conversion Instructions<br>
>> ><br>
>> > -//===---------------------------------------------------------------------===//<br>
>> > -<br>
>> > -// Convert Packed Double FP to Packed DW Integers<br>
>> > -let Predicates = [HasAVX] in {<br>
>> > -// The assembler can recognize rr 256-bit instructions by seeing a ymm<br>
>> > -// register, but the same isn't true when using memory operands<br>
>> > instead.<br>
>> > -// Provide other assembly rr and rm forms to address this explicitly.<br>
>> > -def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > - "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR256:$src),<br>
>> > - "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -<br>
>> > -// XMM only<br>
>> > -def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > - "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > f128mem:$src),<br>
>> > - "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -<br>
>> > -// YMM only<br>
>> > -def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR256:$src),<br>
>> > - "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,<br>
>> > VEX;<br>
>> > -def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > f256mem:$src),<br>
>> > - "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,<br>
>> > VEX, VEX_L;<br>
>> > -}<br>
>> > -<br>
>> > -def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > f128mem:$src),<br>
>> > - "cvtpd2dq\t{$src, $dst|$dst, $src}", [],<br>
>> > - IIC_SSE_CVT_PD_RM>;<br>
>> > -def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > - "cvtpd2dq\t{$src, $dst|$dst, $src}", [],<br>
>> > - IIC_SSE_CVT_PD_RR>;<br>
>> > -<br>
>> > -let Predicates = [HasAVX] in {<br>
>> > - def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),<br>
>> > - (VCVTTPD2DQYrr VR256:$src)>;<br>
>> > - def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),<br>
>> > - (VCVTTPD2DQYrm addr:$src)>;<br>
>> > -} // Predicates = [HasAVX]<br>
>> > -<br>
>> > -// Convert Packed DW Integers to Packed Double FP<br>
>> > -let Predicates = [HasAVX] in {<br>
>> > -def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > i64mem:$src),<br>
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins<br>
>> > i128mem:$src),<br>
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins<br>
>> > VR128:$src),<br>
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;<br>
>> > -}<br>
>> > -<br>
>> > -def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> > i64mem:$src),<br>
>> > - "cvtdq2pd\t{$src, $dst|$dst, $src}", [],<br>
>> > - IIC_SSE_CVT_PD_RR>;<br>
>> > -def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> > VR128:$src),<br>
>> > - "cvtdq2pd\t{$src, $dst|$dst, $src}", [],<br>
>> > - IIC_SSE_CVT_PD_RM>;<br>
>> > -<br>
>> > -// 128 bit register conversion intrinsics<br>
>> > -let Predicates = [HasAVX] in<br>
>> > -def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),<br>
>> > - (VCVTDQ2PDrr VR128:$src)>;<br>
>> > -<br>
>> > -let Predicates = [HasSSE2] in<br>
>> > -def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),<br>
>> > - (CVTDQ2PDrr VR128:$src)>;<br>
>> > -<br>
>> > -// AVX 256-bit register conversion intrinsics<br>
>> > -let Predicates = [HasAVX] in {<br>
>> > - def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),<br>
>> > - (VCVTDQ2PDYrr VR128:$src)>;<br>
>> > - def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64<br>
>> > addr:$src))),<br>
>> > - (VCVTDQ2PDYrm addr:$src)>;<br>
>> > -<br>
>> > - def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),<br>
>> > - (VCVTPD2DQYrr VR256:$src)>;<br>
>> > - def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),<br>
>> > - (VCVTPD2DQYrm addr:$src)>;<br>
>> > -<br>
>> > - def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),<br>
>> > - (VCVTDQ2PDYrr VR128:$src)>;<br>
>> > - def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),<br>
>> > - (VCVTDQ2PDYrm addr:$src)>;<br>
>> > -} // Predicates = [HasAVX]<br>
>> > -<br>
>> ><br>
>> > -//===---------------------------------------------------------------------===//<br>
>> > // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP<br>
>> ><br>
>> > //===---------------------------------------------------------------------===//<br>
>> > multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string<br>
>> > OpcodeStr,<br>
>> ><br>
>> ><br>
>> > _______________________________________________<br>
>> > llvm-commits mailing list<br>
>> > <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
>> > <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
>><br>
>><br>
>><br>
>> --<br>
>> Bruno Cardoso Lopes<br>
>> <a href="http://www.brunocardoso.cc" target="_blank">http://www.brunocardoso.cc</a><br>
><br>
><br>
><br>
><br>
> --<br>
> ~Craig<br>
<br>
<br>
<br>
--<br>
Bruno Cardoso Lopes<br>
<a href="http://www.brunocardoso.cc" target="_blank">http://www.brunocardoso.cc</a><br>
</div></div></blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>