<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Hi Craig,<div><br></div><div>You can go ahead and write patterns that match the fma SDNode today. At the moment, this is only generated when the user explicitly wrote a call to fma(), so matching it won't break existing semantics. Lang's FP_CONTRACT proposal involves introducing @llvm.fmuladd(), which is an <i>optionally</i> fused mul-add, and will be lowered out before SelectionDAG pattern matching.</div><div><br></div><div>--Owen</div><div><br><div><div>On May 31, 2012, at 11:07 PM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Author: ctopper<br>Date: Fri Jun 1 01:07:48 2012<br>New Revision: 157804<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=157804&view=rev">http://llvm.org/viewvc/llvm-project?rev=157804&view=rev</a><br>Log:<br>Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though.<br><br>Removed:<br> llvm/trunk/test/CodeGen/X86/fma3.ll<br>Modified:<br> llvm/trunk/lib/Target/X86/X86InstrFMA.td<br><br>Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=157804&r1=157803&r2=157804&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=157804&r1=157803&r2=157804&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)<br>+++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Fri Jun 1 01:07:48 2012<br>@@ -113,162 +113,6 @@<br> memopv4f64, int_x86_fma4_vfnmsub_pd, int_x86_fma4_vfnmsub_pd_256>, VEX_W;<br> }<br><br>-let Predicates = [HasFMA3], AddedComplexity = 20 in {<br>-//------------<br>-// FP double precision ADD - 256<br>-//------------<br>-<br>-// FMA231: src1 = src2*src3 + src1<br>-def : Pat<(v4f64 (fadd (fmul VR256:$src2, (memopv4f64 addr:$src3)), VR256:$src1)),<br>- (VFMADDPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = src2*src3 + src1<br>-def : Pat<(v4f64 (fadd (fmul VR256:$src2, VR256:$src3), VR256:$src1)),<br>- (VFMADDPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-<br>-//------------<br>-// FP double precision ADD - 128<br>-//------------<br>-<br>-<br>-// FMA231: src1 = src2*src3 + src1<br>-def : Pat<(v2f64 (fadd (fmul VR128:$src2, (memopv2f64 addr:$src3)), VR128:$src1)),<br>- (VFMADDPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = src2*src3 + src1<br>-def : Pat<(v2f64 (fadd (fmul VR128:$src2, VR128:$src3), VR128:$src1)),<br>- (VFMADDPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;<br>-<br>-//------------<br>-// FP double precision SUB - 256<br>-//------------<br>-// FMA231: src1 = src2*src3 - src1<br>-def : Pat<(v4f64 (fsub (fmul VR256:$src2, (memopv4f64 addr:$src3)), VR256:$src1)),<br>- (VFMSUBPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = src2*src3 - src1<br>-def : Pat<(v4f64 (fsub (fmul VR256:$src2, VR256:$src3), VR256:$src1)),<br>- (VFMSUBPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-<br>-//------------<br>-// FP double precision SUB - 128<br>-//------------<br>-<br>-// FMA231: src1 = src2*src3 - src1<br>-def : Pat<(v2f64 (fsub (fmul VR128:$src2, (memopv2f64 addr:$src3)), VR128:$src1)),<br>- (VFMSUBPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = src2*src3 - src1<br>-def : Pat<(v2f64 (fsub (fmul VR128:$src2, VR128:$src3), VR128:$src1)),<br>- (VFMSUBPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;<br>-<br>-//------------<br>-// FP double precision FNMADD - 256<br>-//------------<br>-// FMA231: src1 = - src2*src3 + src1<br>-def : Pat<(v4f64 (fsub VR256:$src1, (fmul VR256:$src2, (memopv4f64 addr:$src3)))),<br>- (VFNMADDPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = - src2*src3 + src1<br>-def : Pat<(v4f64 (fsub VR256:$src1, (fmul VR256:$src2, VR256:$src3))),<br>- (VFNMADDPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-//------------<br>-// FP double precision FNMADD - 128<br>-//------------<br>-<br>-// FMA231: src1 = - src2*src3 + src1<br>-def : Pat<(v2f64 (fsub VR128:$src1, (fmul VR128:$src2, (memopv2f64 addr:$src3)))),<br>- (VFNMADDPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = - src2*src3 + src1<br>-def : Pat<(v2f64 (fsub VR128:$src1, (fmul VR128:$src2, VR128:$src3))),<br>- (VFNMADDPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;<br>-<br>-//------------<br>-// FP single precision ADD - 256<br>-//------------<br>-<br>-// FMA231: src1 = src2*src3 + src1<br>-def : Pat<(v8f32 (fadd (fmul VR256:$src2, VR256:$src3), VR256:$src1)),<br>- (VFMADDPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-// FMA213 : src1 = src2*src1 + src3<br>-def : Pat<(v8f32 (fadd (fmul VR256:$src1, VR256:$src2), (memopv8f32 addr:$src3))),<br>- (VFMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = src2*src3 + src1<br>-def : Pat<(v8f32 (fadd (fmul (memopv8f32 addr:$src3), VR256:$src2), VR256:$src1)),<br>- (VFMADDPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA213: src1 = src2*src1 + src3<br>-def : Pat<(v8f32 (fadd (fmul VR256:$src2, VR256:$src1), VR256:$src3)),<br>- (VFMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-//------------<br>-// FP single precision ADD - 128<br>-//------------<br>-<br>-// FMA231 : src1 = src2*src3 + src1<br>-def : Pat<(v4f32 (fadd (fmul VR128:$src2, (memopv4f32 addr:$src3)), VR128:$src1)),<br>- (VFMADDPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;<br>-<br>-// FMA231 : src1 = src2*src3 + src1<br>-def : Pat<(v4f32 (fadd (fmul VR128:$src2, VR128:$src3), VR128:$src1)),<br>- (VFMADDPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;<br>-<br>-//------------<br>-// FP single precision SUB - 256<br>-//------------<br>-// FMA231: src1 = src2*src3 - src1<br>-def : Pat<(v8f32 (fsub (fmul VR256:$src2, (memopv8f32 addr:$src3)), VR256:$src1)),<br>- (VFMSUBPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = src2*src3 - src1<br>-def : Pat<(v8f32 (fsub (fmul VR256:$src2, VR256:$src3), VR256:$src1)),<br>- (VFMSUBPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-//------------<br>-// FP single precision SUB - 128<br>-//------------<br>-// FMA231 : src1 = src2*src3 - src1<br>-def : Pat<(v4f32 (fsub (fmul VR128:$src2, (memopv4f32 addr:$src3)), VR128:$src1)),<br>- (VFMSUBPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;<br>-<br>-// FMA231 : src1 = src2*src3 - src1<br>-def : Pat<(v4f32 (fsub (fmul VR128:$src2, VR128:$src3), VR128:$src1)),<br>- (VFMSUBPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;<br>-<br>-//------------<br>-// FP single precision FNMADD - 256<br>-//------------<br>-// FMA231: src1 = - src2*src3 + src1<br>-def : Pat<(v8f32 (fsub VR256:$src1, (fmul VR256:$src2, (memopv8f32 addr:$src3)))),<br>- (VFNMADDPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;<br>-<br>-// FMA231: src1 = - src2*src3 + src1<br>-def : Pat<(v8f32 (fsub VR256:$src1, (fmul VR256:$src2, VR256:$src3))),<br>- (VFNMADDPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;<br>-<br>-//------------<br>-// FP single precision FNMADD - 128<br>-//------------<br>-<br>-// FMA231 : src1 = src2*src3 - src1<br>-def : Pat<(v4f32 (fsub VR128:$src1, (fmul VR128:$src2, (memopv4f32 addr:$src3)))),<br>- (VFNMADDPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;<br>-<br>-// FMA231 : src1 = src2*src3 - src1<br>-def : Pat<(v4f32 (fsub VR128:$src1, (fmul VR128:$src2, VR128:$src3))),<br>- (VFNMADDPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;<br>-<br>-} // HasFMA3<br>-<br>-//------------------------------<br>-// SCALAR<br>-//------------------------------<br><br> let Constraints = "$src1 = $dst" in {<br> multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,<br>@@ -328,62 +172,6 @@<br> int_x86_fma4_vfnmsub_sd>, VEX_W, VEX_LIG;<br><br><br>-let Predicates = [HasFMA3], AddedComplexity = 20 in {<br>-<br>-//------------<br>-// FP scalar ADD<br>-//------------<br>-<br>-<br>-// FMADD231 : src1 = src2*src3 + src1<br>-def : Pat<(f32 (fadd (fmul FR32:$src2, FR32:$src3), FR32:$src1)),<br>- (VFMADDSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;<br>-<br>-def : Pat<(f32 (fadd (fmul FR32:$src2, (loadf32 addr:$src3)), FR32:$src1)),<br>- (VFMADDSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;<br>-<br>-def : Pat<(f64 (fadd (fmul FR64:$src2, FR64:$src3), FR64:$src1)),<br>- (VFMADDSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;<br>-<br>-def : Pat<(f64 (fadd (fmul FR64:$src2, (loadf64 addr:$src3)), FR64:$src1)),<br>- (VFMADDSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;<br>-<br>-<br>-<br>-//------------<br>-// FP scalar SUB src2*src3 - src1<br>-//------------<br>-<br>-def : Pat<(f32 (fsub (fmul FR32:$src2, FR32:$src3), FR32:$src1)),<br>- (VFMSUBSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;<br>-<br>-def : Pat<(f32 (fsub (fmul FR32:$src2, (loadf32 addr:$src3)), FR32:$src1)),<br>- (VFMSUBSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;<br>-<br>-def : Pat<(f64 (fsub (fmul FR64:$src2, FR64:$src3), FR64:$src1)),<br>- (VFMSUBSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;<br>-<br>-def : Pat<(f64 (fsub (fmul FR64:$src2, (loadf64 addr:$src3)), FR64:$src1)),<br>- (VFMSUBSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;<br>-<br>-//------------<br>-// FP scalar NADD src1 - src2*src3<br>-//------------<br>-<br>-def : Pat<(f32 (fsub FR32:$src1, (fmul FR32:$src2, FR32:$src3))),<br>- (VFNMADDSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;<br>-<br>-def : Pat<(f32 (fsub FR32:$src1, (fmul FR32:$src2, (loadf32 addr:$src3)))),<br>- (VFNMADDSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;<br>-<br>-def : Pat<(f64 (fsub FR64:$src1, (fmul FR64:$src2, FR64:$src3))),<br>- (VFNMADDSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;<br>-<br>-def : Pat<(f64 (fsub FR64:$src1, (fmul FR64:$src2, (loadf64 addr:$src3)))),<br>- (VFNMADDSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;<br>-<br>-} // HasFMA3<br>-<br> //===----------------------------------------------------------------------===//<br> // FMA4 - AMD 4 operand Fused Multiply-Add instructions<br> //===----------------------------------------------------------------------===//<br><br>Removed: llvm/trunk/test/CodeGen/X86/fma3.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma3.ll?rev=157803&view=auto">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fma3.ll?rev=157803&view=auto</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/fma3.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/fma3.ll (removed)<br>@@ -1,66 +0,0 @@<br>-; RUN: llc < %s -mtriple=x86_64-pc-win32 -mcpu=core-avx2 -mattr=avx2,+fma3 | FileCheck %s<br>-<br>-define <4 x float> @test_x86_fmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {<br>- ; CHECK: fmadd231ps {{.*\(%r.*}}, %xmm<br>- %x = fmul <4 x float> %a0, %a1<br>- %res = fadd <4 x float> %x, %a2<br>- ret <4 x float> %res<br>-}<br>-<br>-define <4 x float> @test_x86_fmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {<br>- ; CHECK: fmsub231ps {{.*\(%r.*}}, %xmm<br>- %x = fmul <4 x float> %a0, %a1<br>- %res = fsub <4 x float> %x, %a2<br>- ret <4 x float> %res<br>-}<br>-<br>-define <4 x float> @test_x86_fnmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {<br>- ; CHECK: fnmadd231ps {{.*\(%r.*}}, %xmm<br>- %x = fmul <4 x float> %a0, %a1<br>- %res = fsub <4 x float> %a2, %x<br>- ret <4 x float> %res<br>-}<br>-<br>-define <8 x float> @test_x86_fmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {<br>- ; CHECK: vfmadd213ps<span class="Apple-tab-span" style="white-space:pre"> </span>{{.*\(%r.*}}, %ymm<br>- %x = fmul <8 x float> %a0, %a1<br>- %res = fadd <8 x float> %x, %a2<br>- ret <8 x float> %res<br>-}<br>-<br>-define <4 x double> @test_x86_fmadd_pd_y(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {<br>- ; CHECK: vfmadd231pd {{.*\(%r.*}}, %ymm<br>- %x = fmul <4 x double> %a0, %a1<br>- %res = fadd <4 x double> %x, %a2<br>- ret <4 x double> %res<br>-}<br>-<br>-<br>-define <8 x float> @test_x86_fmsub_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {<br>- ; CHECK: fmsub231ps {{.*\(%r.*}}, %ymm<br>- %x = fmul <8 x float> %a0, %a1<br>- %res = fsub <8 x float> %x, %a2<br>- ret <8 x float> %res<br>-}<br>-<br>-define <8 x float> @test_x86_fnmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {<br>- ; CHECK: fnmadd231ps {{.*\(%r.*}}, %ymm<br>- %x = fmul <8 x float> %a0, %a1<br>- %res = fsub <8 x float> %a2, %x<br>- ret <8 x float> %res<br>-}<br>-<br>-define float @test_x86_fnmadd_ss(float %a0, float %a1, float %a2) {<br>- ; CHECK: vfnmadd231ss %xmm1, %xmm0, %xmm2<br>- %x = fmul float %a0, %a1<br>- %res = fsub float %a2, %x<br>- ret float %res<br>-}<br>-<br>-define double @test_x86_fnmadd_sd(double %a0, double %a1, double %a2) {<br>- ; CHECK: vfnmadd231sd %xmm1, %xmm0, %xmm2<br>- %x = fmul double %a0, %a1<br>- %res = fsub double %a2, %x<br>- ret double %res<br>-}<br>-<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote></div><br></div></body></html>