Shouldn't the non-MC JIT emitter also be fixed?<br><br><div class="gmail_quote">On Tue, May 29, 2012 at 12:05 PM, Benjamin Kramer <span dir="ltr"><<a href="mailto:benny.kra@googlemail.com" target="_blank">benny.kra@googlemail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: d0k<br>
Date: Tue May 29 14:05:25 2012<br>
New Revision: 157634<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=157634&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=157634&view=rev</a><br>
Log:<br>
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.<br>
<br>
This required light surgery on the assembler and disassembler<br>
because the instructions use an uncommon encoding. They are<br>
the only two instructions in x86 that use register operands<br>
and two immediates.<br>
<br>
Added:<br>
llvm/trunk/test/MC/X86/x86_64-sse4a.s<br>
Modified:<br>
llvm/trunk/include/llvm/IntrinsicsX86.td<br>
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
llvm/trunk/test/CodeGen/X86/sse4a.ll<br>
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt<br>
llvm/trunk/test/MC/Disassembler/X86/x86-64.txt<br>
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IntrinsicsX86.td Tue May 29 14:05:25 2012<br>
@@ -1008,6 +1008,17 @@<br>
// SSE4A<br>
<br>
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".<br>
+ def int_x86_sse4a_extrqi : GCCBuiltin<"__builtin_ia32_extrqi">,<br>
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i8_ty, llvm_i8_ty], []>;<br>
+ def int_x86_sse4a_extrq : GCCBuiltin<"__builtin_ia32_extrq">,<br>
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v16i8_ty], []>;<br>
+<br>
+ def int_x86_sse4a_insertqi : GCCBuiltin<"__builtin_ia32_insertqi">,<br>
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,<br>
+ llvm_i8_ty, llvm_i8_ty], []>;<br>
+ def int_x86_sse4a_insertq : GCCBuiltin<"__builtin_ia32_insertq">,<br>
+ Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], []>;<br>
+<br>
def int_x86_sse4a_movnt_ss : GCCBuiltin<"__builtin_ia32_movntss">,<br>
Intrinsic<[], [llvm_ptr_ty, llvm_v4f32_ty], []>;<br>
def int_x86_sse4a_movnt_sd : GCCBuiltin<"__builtin_ia32_movntsd">,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Tue May 29 14:05:25 2012<br>
@@ -1150,8 +1150,9 @@<br>
}<br>
<br>
// If there is a remaining operand, it must be a trailing immediate. Emit it<br>
- // according to the right size for the instruction.<br>
- if (CurOp != NumOps) {<br>
+ // according to the right size for the instruction. Some instructions<br>
+ // (SSE4a extrq and insertq) have two trailing immediates.<br>
+ while (CurOp != NumOps && NumOps - CurOp <= 2) {<br>
// The last source register of a 4 operand instruction in AVX is encoded<br>
// in bits[7:4] of a immediate byte.<br>
if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue May 29 14:05:25 2012<br>
@@ -7268,6 +7268,31 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
let Predicates = [HasSSE4A] in {<br>
+<br>
+let Constraints = "$src = $dst" in {<br>
+def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),<br>
+ (ins VR128:$src, i8imm:$len, i8imm:$idx),<br>
+ "extrq\t{$idx, $len, $src|$src, $len, $idx}",<br>
+ [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,<br>
+ imm:$idx))]>, TB, OpSize;<br>
+def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),<br>
+ (ins VR128:$src, VR128:$mask),<br>
+ "extrq\t{$mask, $src|$src, $mask}",<br>
+ [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,<br>
+ VR128:$mask))]>, TB, OpSize;<br>
+<br>
+def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),<br>
+ (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),<br>
+ "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",<br>
+ [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,<br>
+ VR128:$src2, imm:$len, imm:$idx))]>, XD;<br>
+def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),<br>
+ (ins VR128:$src, VR128:$mask),<br>
+ "insertq\t{$mask, $src|$src, $mask}",<br>
+ [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,<br>
+ VR128:$mask))]>, XD;<br>
+}<br>
+<br>
def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),<br>
"movntss\t{$src, $dst|$dst, $src}",<br>
[(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse4a.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse4a.ll?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse4a.ll?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse4a.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse4a.ll Tue May 29 14:05:25 2012<br>
@@ -1,8 +1,8 @@<br>
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s<br>
<br>
define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {<br>
+; CHECK: test1:<br>
; CHECK: movntss<br>
-entry:<br>
tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind<br>
ret void<br>
}<br>
@@ -10,10 +10,47 @@<br>
declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)<br>
<br>
define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {<br>
+; CHECK: test2:<br>
; CHECK: movntsd<br>
-entry:<br>
tail call void @<a href="http://llvm.x86.sse4a.movnt.sd" target="_blank">llvm.x86.sse4a.movnt.sd</a>(i8* %p, <2 x double> %a) nounwind<br>
ret void<br>
}<br>
<br>
declare void @<a href="http://llvm.x86.sse4a.movnt.sd" target="_blank">llvm.x86.sse4a.movnt.sd</a>(i8*, <2 x double>)<br>
+<br>
+define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {<br>
+; CHECK: test3:<br>
+; CHECK: extrq<br>
+ %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)<br>
+ ret <2 x i64> %1<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind<br>
+<br>
+define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {<br>
+; CHECK: test4:<br>
+; CHECK: extrq<br>
+ %1 = bitcast <2 x i64> %y to <16 x i8><br>
+ %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind<br>
+ ret <2 x i64> %2<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind<br>
+<br>
+define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {<br>
+; CHECK: test5:<br>
+; CHECK: insertq<br>
+ %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)<br>
+ ret <2 x i64> %1<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind<br>
+<br>
+define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {<br>
+; CHECK: test6:<br>
+; CHECK: insertq<br>
+ %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind<br>
+ ret <2 x i64> %1<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64>, <2 x i64>) nounwind<br>
<br>
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)<br>
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Tue May 29 14:05:25 2012<br>
@@ -612,3 +612,21 @@<br>
<br>
# CHECK: shrxl %esi, %ebx, %edx<br>
0xc4 0xe2 0x0b 0xf7 0xd3<br>
+<br>
+# CHECK: extrq $2, $3, %xmm0<br>
+0x66 0x0f 0x78 0xc0 0x03 0x02<br>
+<br>
+# CHECK: extrq %xmm1, %xmm0<br>
+0x66 0x0f 0x79 0xc1<br>
+<br>
+# CHECK: insertq $6, $5, %xmm1, %xmm0<br>
+0xf2 0x0f 0x78 0xc1 0x05 0x06<br>
+<br>
+# CHECK: insertq %xmm1, %xmm0<br>
+0xf2 0x0f 0x79 0xc1<br>
+<br>
+# CHECK: movntsd %xmm0, (%edi)<br>
+0xf2 0x0f 0x2b 0x07<br>
+<br>
+# CHECK: movntss %xmm0, (%edi)<br>
+0xf3 0x0f 0x2b 0x07<br>
<br>
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)<br>
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Tue May 29 14:05:25 2012<br>
@@ -61,3 +61,21 @@<br>
<br>
# CHECK: cmpordsd<br>
0xf2 0x0f 0xc2 0xc7 0x07<br>
+<br>
+# CHECK: extrq $2, $3, %xmm0<br>
+0x66 0x0f 0x78 0xc0 0x03 0x02<br>
+<br>
+# CHECK: extrq %xmm1, %xmm0<br>
+0x66 0x0f 0x79 0xc1<br>
+<br>
+# CHECK: insertq $6, $5, %xmm1, %xmm0<br>
+0xf2 0x0f 0x78 0xc1 0x05 0x06<br>
+<br>
+# CHECK: insertq %xmm1, %xmm0<br>
+0xf2 0x0f 0x79 0xc1<br>
+<br>
+# CHECK: movntsd %xmm0, (%rdi)<br>
+0xf2 0x0f 0x2b 0x07<br>
+<br>
+# CHECK: movntss %xmm0, (%rdi)<br>
+0xf3 0x0f 0x2b 0x07<br>
<br>
Added: llvm/trunk/test/MC/X86/x86_64-sse4a.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-sse4a.s?rev=157634&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-sse4a.s?rev=157634&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/X86/x86_64-sse4a.s (added)<br>
+++ llvm/trunk/test/MC/X86/x86_64-sse4a.s Tue May 29 14:05:25 2012<br>
@@ -0,0 +1,25 @@<br>
+# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s<br>
+<br>
+extrq $2, $3, %xmm0<br>
+# CHECK: extrq $2, $3, %xmm0<br>
+# CHECK: encoding: [0x66,0x0f,0x78,0xc0,0x03,0x02]<br>
+<br>
+extrq %xmm1, %xmm0<br>
+# CHECK: extrq %xmm1, %xmm0<br>
+# CHECK: encoding: [0x66,0x0f,0x79,0xc1]<br>
+<br>
+insertq $6, $5, %xmm1, %xmm0<br>
+# CHECK: insertq $6, $5, %xmm1, %xmm0<br>
+# CHECK: encoding: [0xf2,0x0f,0x78,0xc1,0x05,0x06]<br>
+<br>
+insertq %xmm1, %xmm0<br>
+# CHECK: insertq %xmm1, %xmm0<br>
+# CHECK: encoding: [0xf2,0x0f,0x79,0xc1]<br>
+<br>
+movntsd %xmm0, (%rdi)<br>
+# CHECK: movntsd %xmm0, (%rdi)<br>
+# CHECK: encoding: [0xf2,0x0f,0x2b,0x07]<br>
+<br>
+movntss %xmm0, (%rdi)<br>
+# CHECK: movntss %xmm0, (%rdi)<br>
+# CHECK: encoding: [0xf3,0x0f,0x2b,0x07]<br>
<br>
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=157634&r1=157633&r2=157634&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=157634&r1=157633&r2=157634&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Tue May 29 14:05:25 2012<br>
@@ -690,12 +690,13 @@<br>
// Operand 2 is a register operand in the R/M field.<br>
// - In AVX, there is a register operand in the VEX.vvvv field here -<br>
// Operand 3 (optional) is an immediate.<br>
+ // Operand 4 (optional) is an immediate.<br>
<br>
if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)<br>
assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&<br>
"Unexpected number of operands for MRMSrcRegFrm with VEX_4V");<br>
else<br>
- assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&<br>
+ assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&<br>
"Unexpected number of operands for MRMSrcRegFrm");<br>
<br>
HANDLE_OPERAND(roRegister)<br>
@@ -716,6 +717,7 @@<br>
if (!HasMemOp4Prefix)<br>
HANDLE_OPTIONAL(immediate)<br>
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4<br>
+ HANDLE_OPTIONAL(immediate)<br>
break;<br>
case X86Local::MRMSrcMem:<br>
// Operand 1 is a register operand in the Reg/Opcode field.<br>
@@ -759,16 +761,18 @@<br>
case X86Local::MRM7r:<br>
// Operand 1 is a register operand in the R/M field.<br>
// Operand 2 (optional) is an immediate or relocation.<br>
+ // Operand 3 (optional) is an immediate.<br>
if (HasVEX_4VPrefix)<br>
assert(numPhysicalOperands <= 3 &&<br>
"Unexpected number of operands for MRMnRFrm with VEX_4V");<br>
else<br>
- assert(numPhysicalOperands <= 2 &&<br>
+ assert(numPhysicalOperands <= 3 &&<br>
"Unexpected number of operands for MRMnRFrm");<br>
if (HasVEX_4VPrefix)<br>
HANDLE_OPERAND(vvvvRegister)<br>
HANDLE_OPTIONAL(rmRegister)<br>
HANDLE_OPTIONAL(relocation)<br>
+ HANDLE_OPTIONAL(immediate)<br>
break;<br>
case X86Local::MRM0m:<br>
case X86Local::MRM1m:<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>