Args: llc -debug 
Subtarget features: SSELevel 5, 3DNowLevel 0, 64bit 1
Computing probabilities for 



=== test_nocall_hipecc
Initial selection DAG: BB#0 'test_nocall_hipecc:'
SelectionDAG has 17 nodes:
  0x2f01400: ch = EntryToken [ORD=1]

  0x2f2a620: i32 = undef [ORD=1]

    0x2f2a620: <multiple use>
    0x2f2a620: <multiple use>
  0x2f2a720: i32,i32 = merge_values 0x2f2a620, 0x2f2a620

          0x2f01400: <multiple use>
          0x2f2a020: i64 = Register %vreg0 [ORD=1]

        0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1]

      0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1]

      0x2f2a620: <multiple use>
    0x2f2a820: i32,i32 = merge_values 0x2f2a220, 0x2f2a620 [ORD=1]

        0x2f01400: <multiple use>
        0x2f2a320: i64 = Register %vreg1 [ORD=2]

      0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2]

    0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2]

  0x2f2a920: i32,i32 = merge_values 0x2f2a820, 0x2f2a520 [ORD=2]

    0x2f01400: <multiple use>
    0x2f2ab20: i32 = Register %R15

    0x2f2a920: <multiple use>
  0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a920

    0x2f2ac20: <multiple use>
    0x2f2ad20: i32 = Register %RBP

    0x2f2a920: <multiple use>
    0x2f2ac20: <multiple use>
  0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a920:1, 0x2f2ac20:1

    0x2f2ae20: <multiple use>
    0x2f2aa20: i16 = TargetConstant<0>

    0x2f2ae20: <multiple use>
  0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1


Optimized lowered selection DAG: BB#0 'test_nocall_hipecc:'
SelectionDAG has 13 nodes:
  0x2f01400: ch = EntryToken [ORD=1]

    0x2f01400: <multiple use>
    0x2f2ab20: i32 = Register %R15

        0x2f01400: <multiple use>
        0x2f2a020: i64 = Register %vreg0 [ORD=1]

      0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1]

    0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1]

  0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220

    0x2f2ac20: <multiple use>
    0x2f2ad20: i32 = Register %RBP

        0x2f01400: <multiple use>
        0x2f2a320: i64 = Register %vreg1 [ORD=2]

      0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2]

    0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2]

    0x2f2ac20: <multiple use>
  0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1

    0x2f2ae20: <multiple use>
    0x2f2aa20: i16 = TargetConstant<0>

    0x2f2ae20: <multiple use>
  0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1


Legally typed node: 0x2f2ad20: i32 = Register %RBP [ID=0]

Legally typed node: 0x2f2ab20: i32 = Register %R15 [ID=0]

Legally typed node: 0x2f2aa20: i16 = TargetConstant<0> [ID=0]

Legally typed node: 0x2f2a320: i64 = Register %vreg1 [ORD=2] [ID=0]

Legally typed node: 0x2f2a020: i64 = Register %vreg0 [ORD=1] [ID=0]

Legally typed node: 0x2f01400: ch = EntryToken [ORD=1] [ID=0]

Legally typed node: 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=0]

Legally typed node: 0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1] [ID=0]

Legally typed node: 0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=0]

Legally typed node: 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=0]

Legally typed node: 0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2] [ID=0]

Legally typed node: 0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=0]

Legally typed node: 0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1 [ID=0]

Legally typed node: 0x7fffc689a4e0: ch = handlenode 0x2f2cbe0 [ID=0]

Type-legalized selection DAG: BB#0 'test_nocall_hipecc:'
SelectionDAG has 13 nodes:
  0x2f01400: ch = EntryToken [ORD=1] [ID=-3]

    0x2f01400: <multiple use>
    0x2f2ab20: i32 = Register %R15 [ID=-3]

        0x2f01400: <multiple use>
        0x2f2a020: i64 = Register %vreg0 [ORD=1] [ID=-3]

      0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=-3]

    0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1] [ID=-3]

  0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=-3]

    0x2f2ac20: <multiple use>
    0x2f2ad20: i32 = Register %RBP [ID=-3]

        0x2f01400: <multiple use>
        0x2f2a320: i64 = Register %vreg1 [ORD=2] [ID=-3]

      0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=-3]

    0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2] [ID=-3]

    0x2f2ac20: <multiple use>
  0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=-3]

    0x2f2ae20: <multiple use>
    0x2f2aa20: i16 = TargetConstant<0> [ID=-3]

    0x2f2ae20: <multiple use>
  0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1 [ID=-3]


Legalized selection DAG: BB#0 'test_nocall_hipecc:'
SelectionDAG has 13 nodes:
  0x2f01400: ch = EntryToken [ORD=1] [ID=0]

    0x2f01400: <multiple use>
    0x2f2ab20: i32 = Register %R15 [ID=4]

        0x2f01400: <multiple use>
        0x2f2a020: i64 = Register %vreg0 [ORD=1] [ID=1]

      0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=6]

    0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1] [ID=8]

  0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=10]

    0x2f2ac20: <multiple use>
    0x2f2ad20: i32 = Register %RBP [ID=5]

        0x2f01400: <multiple use>
        0x2f2a320: i64 = Register %vreg1 [ORD=2] [ID=2]

      0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=7]

    0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2] [ID=9]

    0x2f2ac20: <multiple use>
  0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=11]

    0x2f2ae20: <multiple use>
    0x2f2aa20: i16 = TargetConstant<0> [ID=3]

    0x2f2ae20: <multiple use>
  0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1 [ID=12]


Optimized legalized selection DAG: BB#0 'test_nocall_hipecc:'
SelectionDAG has 13 nodes:
  0x2f01400: ch = EntryToken [ORD=1] [ID=0]

    0x2f01400: <multiple use>
    0x2f2ab20: i32 = Register %R15 [ID=4]

        0x2f01400: <multiple use>
        0x2f2a020: i64 = Register %vreg0 [ORD=1] [ID=1]

      0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=6]

    0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1] [ID=8]

  0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=10]

    0x2f2ac20: <multiple use>
    0x2f2ad20: i32 = Register %RBP [ID=5]

        0x2f01400: <multiple use>
        0x2f2a320: i64 = Register %vreg1 [ORD=2] [ID=2]

      0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=7]

    0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2] [ID=9]

    0x2f2ac20: <multiple use>
  0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=11]

    0x2f2ae20: <multiple use>
    0x2f2aa20: i16 = TargetConstant<0> [ID=3]

    0x2f2ae20: <multiple use>
  0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1 [ID=12]


===== Instruction selection begins: BB#0 ''
Selecting: 0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1 [ID=12]

ISEL: Starting pattern match on root node: 0x2f2cbe0: ch = X86ISD::RET_FLAG 0x2f2ae20, 0x2f2aa20, 0x2f2ae20:1 [ID=12]

  Morphed node: 0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1

ISEL: Match complete!
=> 0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1

Selecting: 0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=11]

=> 0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1

Selecting: 0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=10]

=> 0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220

Selecting: 0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2] [ID=9]

ISEL: Starting pattern match on root node: 0x2f2a520: i32 = truncate 0x2f2a420 [ORD=2] [ID=9]

  Initial Opcode index to 82374
  Match failed at index 82379
  Continuing at 82516
  Skipped scope entry (due to false predicate) at index 82521, continuing at 82585
  TypeSwitch[i32] from 82588 to 82591
  Morphed node: 0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2]

ISEL: Match complete!
=> 0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2]

Selecting: 0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1] [ID=8]

ISEL: Starting pattern match on root node: 0x2f2a220: i32 = truncate 0x2f2a120 [ORD=1] [ID=8]

  Initial Opcode index to 82374
  Match failed at index 82379
  Continuing at 82516
  Skipped scope entry (due to false predicate) at index 82521, continuing at 82585
  TypeSwitch[i32] from 82588 to 82591
  Morphed node: 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1]

ISEL: Match complete!
=> 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1]

Selecting: 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=7]

=> 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2]

Selecting: 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=6]

=> 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1]

Selecting: 0x2f2ad20: i32 = Register %RBP [ID=5]

=> 0x2f2ad20: i32 = Register %RBP

Selecting: 0x2f2ab20: i32 = Register %R15 [ID=4]

=> 0x2f2ab20: i32 = Register %R15

Selecting: 0x2f2a320: i64 = Register %vreg1 [ORD=2] [ID=2]

=> 0x2f2a320: i64 = Register %vreg1 [ORD=2]

Selecting: 0x2f2a020: i64 = Register %vreg0 [ORD=1] [ID=1]

=> 0x2f2a020: i64 = Register %vreg0 [ORD=1]

Selecting: 0x2f01400: ch = EntryToken [ORD=1] [ID=0]

=> 0x2f01400: ch = EntryToken [ORD=1]

===== Instruction selection ends:
Selected selection DAG: BB#0 'test_nocall_hipecc:'
SelectionDAG has 13 nodes:
  0x2f01400: ch = EntryToken [ORD=1]

    0x2f01400: <multiple use>
    0x2f2ab20: i32 = Register %R15

        0x2f01400: <multiple use>
        0x2f2a020: i64 = Register %vreg0 [ORD=1]

      0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1]

      0x2f2aa20: <multiple use>
    0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1]

  0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220

    0x2f2ac20: <multiple use>
    0x2f2ad20: i32 = Register %RBP

        0x2f01400: <multiple use>
        0x2f2a320: i64 = Register %vreg1 [ORD=2]

      0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2]

      0x2f2aa20: <multiple use>
    0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2]

    0x2f2ac20: <multiple use>
  0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1

  0x2f2aa20: i32 = TargetConstant<4>

    0x2f2ae20: <multiple use>
    0x2f2ae20: <multiple use>
  0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1


********** List Scheduling BB#0 '' **********
SU(0): 0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1 [ID=0]

    0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=0]

    0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=0]

  # preds left       : 2
  # succs left       : 0
  # rdefs left       : 0
  Latency            : 1
  Depth              : 0
  Height             : 0
  Predecessors:
   val SU(1): Latency=1
   val SU(3): Latency=1

SU(1): 0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2] [ID=1]

  # preds left       : 1
  # succs left       : 1
  # rdefs left       : 1
  Latency            : 1
  Depth              : 0
  Height             : 0
  Predecessors:
   val SU(2): Latency=1
  Successors:
   val SU(0): Latency=1

SU(2): 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=2]

  # preds left       : 0
  # succs left       : 1
  # rdefs left       : 1
  Latency            : 1
  Depth              : 0
  Height             : 0
  Successors:
   val SU(1): Latency=1

SU(3): 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1] [ID=3]

  # preds left       : 1
  # succs left       : 1
  # rdefs left       : 1
  Latency            : 1
  Depth              : 0
  Height             : 0
  Predecessors:
   val SU(4): Latency=1
  Successors:
   val SU(0): Latency=1

SU(4): 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=4]

  # preds left       : 0
  # succs left       : 1
  # rdefs left       : 1
  Latency            : 1
  Depth              : 0
  Height             : 0
  Successors:
   val SU(3): Latency=1


Examining Available:
Height 0: SU(0): 0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1 [ID=0]

    0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=0]

    0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=0]


*** Scheduling [0]: SU(0): 0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1 [ID=0]

    0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=0]

    0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=0]

GR64: 2 / 12

Examining Available:
Height 1: SU(1): 0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2] [ID=1]

Height 1: SU(3): 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1] [ID=3]


*** Scheduling [1]: SU(1): 0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2] [ID=1]

GR64: 2 / 12

Examining Available:
Height 2: SU(2): 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=2]

Height 1: SU(3): 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1] [ID=3]


*** Scheduling [2]: SU(2): 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=2]

GR64: 1 / 12

Examining Available:
Height 1: SU(3): 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1] [ID=3]


*** Scheduling [3]: SU(3): 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1] [ID=3]

GR64: 1 / 12

Examining Available:
Height 4: SU(4): 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=4]


*** Scheduling [4]: SU(4): 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=4]

*** Final schedule ***
SU(4): 0x2f2a120: i64,ch = CopyFromReg 0x2f01400, 0x2f2a020 [ORD=1] [ID=4]

SU(3): 0x2f2a220: i32 = EXTRACT_SUBREG 0x2f2a120, 0x2f2aa20 [ORD=1] [ID=3]

SU(2): 0x2f2a420: i64,ch = CopyFromReg 0x2f01400, 0x2f2a320 [ORD=2] [ID=2]

SU(1): 0x2f2a520: i32 = EXTRACT_SUBREG 0x2f2a420, 0x2f2aa20 [ORD=2] [ID=1]

SU(0): 0x2f2cbe0: ch = RET 0x2f2ae20, 0x2f2ae20:1 [ID=0]

    0x2f2ac20: ch,glue = CopyToReg 0x2f01400, 0x2f2ab20, 0x2f2a220 [ID=0]

    0x2f2ae20: ch,glue = CopyToReg 0x2f2ac20, 0x2f2ad20, 0x2f2a520, 0x2f2ac20:1 [ID=0]


Total amount of phi nodes to update: 0
******** Pre-regalloc Machine LICM: test_nocall_hipecc ********
Entering: 
Exiting: 
******** Machine Sinking ********
********** REWRITING TWO-ADDR INSTRS **********
********** Function: test_nocall_hipecc
********** PROCESS IMPLICIT DEFS **********
********** Function: test_nocall_hipecc
# Machine code for function test_nocall_hipecc: Post SSA
Function Live Ins: %R15 in %vreg0, %RBP in %vreg1
Function Live Outs: %R15 %RBP

0B	BB#0: derived from LLVM BB %0
	    Live Ins: %R15 %RBP
16B		%vreg1<def> = COPY %RBP<kill>; GR64:%vreg1
32B		%vreg0<def> = COPY %R15<kill>; GR64:%vreg0
48B		%vreg2<def> = COPY %vreg0:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg0
64B		%vreg3<def> = COPY %vreg1:sub_32bit<kill>; GR32:%vreg3 GR64:%vreg1
80B		%R15<def> = COPY %vreg2<kill>; GR32:%vreg2
96B		%RBP<def> = COPY %vreg3<kill>; GR32:%vreg3
112B		RET %R15<imp-use,kill>, %RBP<imp-use,kill>

# End machine code for function test_nocall_hipecc.

********** COMPUTING LIVE INTERVALS **********
********** Function: test_nocall_hipecc
BB#0:		# derived from 
		livein register: %R15 killed +[0B,32r:0)
		livein register: %RBP killed +[0B,16r:0)
16B	%vreg1<def> = COPY %RBP<kill>; GR64:%vreg1
		register: %vreg1 +[16r,64r:0)
32B	%vreg0<def> = COPY %R15<kill>; GR64:%vreg0
		register: %vreg0 +[32r,48r:0)
48B	%vreg2<def> = COPY %vreg0:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg0
		register: %vreg2 +[48r,80r:0)
64B	%vreg3<def> = COPY %vreg1:sub_32bit<kill>; GR32:%vreg3 GR64:%vreg1
		register: %vreg3 +[64r,96r:0)
80B	%R15<def> = COPY %vreg2<kill>; GR32:%vreg2
		register: %R15 killed +[80r,112r:1)
96B	%RBP<def> = COPY %vreg3<kill>; GR32:%vreg3
		register: %RBP killed +[96r,112r:1)
112B	RET %R15<imp-use,kill>, %RBP<imp-use,kill>
********** INTERVALS **********
%R15,inf = [0B,32r:0)[80r,112r:1)  0@0B-phidef 1@80r
%RBP,inf = [0B,16r:0)[96r,112r:1)  0@0B-phidef 1@96r
%vreg0 = [32r,48r:0)  0@32r
%vreg1 = [16r,64r:0)  0@16r
%vreg2 = [48r,80r:0)  0@48r
%vreg3 = [64r,96r:0)  0@64r
********** MACHINEINSTRS **********
# Machine code for function test_nocall_hipecc: Post SSA
Function Live Ins: %R15 in %vreg0, %RBP in %vreg1
Function Live Outs: %R15 %RBP

0B	BB#0: derived from LLVM BB %0
	    Live Ins: %R15 %RBP
16B		%vreg1<def> = COPY %RBP<kill>; GR64:%vreg1
32B		%vreg0<def> = COPY %R15<kill>; GR64:%vreg0
48B		%vreg2<def> = COPY %vreg0:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg0
64B		%vreg3<def> = COPY %vreg1:sub_32bit<kill>; GR32:%vreg3 GR64:%vreg1
80B		%R15<def> = COPY %vreg2<kill>; GR32:%vreg2
96B		%RBP<def> = COPY %vreg3<kill>; GR32:%vreg3
112B		RET %R15<imp-use,kill>, %RBP<imp-use,kill>

# End machine code for function test_nocall_hipecc.

********** COMPUTING LIVE DEBUG VARIABLES: test_nocall_hipecc **********
********** DEBUG VARIABLES **********
********** SIMPLE REGISTER COALESCING **********
********** Function: test_nocall_hipecc
********** JOINING INTERVALS ***********
:
16B	%vreg1<def> = COPY %RBP<kill>; GR64:%vreg1
	Considering merging %vreg1 with %RBP
	Physreg joins disabled.
32B	%vreg0<def> = COPY %R15<kill>; GR64:%vreg0
	Considering merging %vreg0 with %R15
	Physreg joins disabled.
80B	%R15<def> = COPY %vreg2<kill>; GR32:%vreg2
	Not coalescable.
96B	%RBP<def> = COPY %vreg3<kill>; GR32:%vreg3
	Not coalescable.
48B	%vreg2<def> = COPY %vreg0:sub_32bit<kill>; GR32:%vreg2 GR64:%vreg0
	Considering merging %vreg2 with %vreg0:sub_32bit
	Cross-class to GR64_with_sub_8bit.
		RHS = %vreg2 = [48r,80r:0)  0@48r
		LHS = %vreg0 = [32r,48r:0)  0@32r
		updated: 80B	%R15<def> = COPY %vreg0:sub_32bit<kill>; GR64_with_sub_8bit:%vreg0
	Joined. Result = %vreg0 = [32r,80r:0)  0@32r
64B	%vreg3<def> = COPY %vreg1:sub_32bit<kill>; GR32:%vreg3 GR64:%vreg1
	Considering merging %vreg3 with %vreg1:sub_32bit
	Cross-class to GR64_with_sub_8bit.
		RHS = %vreg3 = [64r,96r:0)  0@64r
		LHS = %vreg1 = [16r,64r:0)  0@16r
		updated: 96B	%RBP<def> = COPY %vreg1:sub_32bit<kill>; GR64_with_sub_8bit:%vreg1
	Joined. Result = %vreg1 = [16r,96r:0)  0@16r
********** INTERVALS POST JOINING **********
%vreg0 = [32r,80r:0)  0@32r
%vreg1 = [16r,96r:0)  0@16r
%RBP,inf = [0B,16r:0)[96r,112r:1)  0@0B-phidef 1@96r
%R15,inf = [0B,32r:0)[80r,112r:1)  0@0B-phidef 1@80r
AllocationOrder(GR64) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 %RBP ]
AllocationOrder(GR64_with_sub_8bit) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 %RBP ]
Trying to inflate 0 regs.
********** INTERVALS **********
%R15,inf = [0B,32r:0)[80r,112r:1)  0@0B-phidef 1@80r
%RBP,inf = [0B,16r:0)[96r,112r:1)  0@0B-phidef 1@96r
%vreg0 = [32r,80r:0)  0@32r
%vreg1 = [16r,96r:0)  0@16r
********** MACHINEINSTRS **********
# Machine code for function test_nocall_hipecc: Post SSA
Function Live Ins: %R15 in %vreg0, %RBP in %vreg1
Function Live Outs: %R15 %RBP

0B	BB#0: derived from LLVM BB %0
	    Live Ins: %R15 %RBP
16B		%vreg1<def> = COPY %RBP<kill>; GR64_with_sub_8bit:%vreg1
32B		%vreg0<def> = COPY %R15<kill>; GR64_with_sub_8bit:%vreg0
80B		%R15<def> = COPY %vreg0:sub_32bit<kill>; GR64_with_sub_8bit:%vreg0
96B		%RBP<def> = COPY %vreg1:sub_32bit<kill>; GR64_with_sub_8bit:%vreg1
112B		RET %R15<imp-use,kill>, %RBP<imp-use,kill>

# End machine code for function test_nocall_hipecc.

********** DEBUG VARIABLES **********
********** Compute Spill Weights **********
********** Function: test_nocall_hipecc
********** GREEDY REGISTER ALLOCATION **********
********** Function: test_nocall_hipecc

selectOrSplit GR64_with_sub_8bit:%vreg1,4.208333e-03 = [16r,96r:0)  0@16r
AllocationOrder(GR64) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 %RBP ]
AllocationOrder(GR64_with_sub_8bit) = [ %RAX %RCX %RDX %RSI %RDI %R8 %R9 %R10 %R11 %RBX %R14 %R15 %R12 %R13 %RBP ]
assigning %vreg1 to %RBP

selectOrSplit GR64_with_sub_8bit:%vreg0,inf = [32r,80r:0)  0@32r
assigning %vreg0 to %R15
********** REWRITE VIRTUAL REGISTERS **********
********** Function: test_nocall_hipecc
********** REGISTER MAP **********
[%vreg0 -> %R15] GR64_with_sub_8bit
[%vreg1 -> %RBP] GR64_with_sub_8bit

0B	BB#0: derived from LLVM BB %0
	    Live Ins: %R15 %RBP
16B		%vreg1<def> = COPY %RBP<kill>; GR64_with_sub_8bit:%vreg1
32B		%vreg0<def> = COPY %R15<kill>; GR64_with_sub_8bit:%vreg0
80B		%R15<def> = COPY %vreg0:sub_32bit<kill>; GR64_with_sub_8bit:%vreg0
96B		%RBP<def> = COPY %vreg1:sub_32bit<kill>; GR64_with_sub_8bit:%vreg1
112B		RET %R15<imp-use,kill>, %RBP<imp-use,kill>
> %RBP<def> = COPY %RBP<kill>
Deleting identity copy.
> %R15<def> = COPY %R15<kill>
Deleting identity copy.
> %R15<def> = COPY %R15D, %R15<imp-use,kill>
> %RBP<def> = COPY %EBP, %RBP<imp-use,kill>
> RET %R15<imp-use,kill>, %RBP<imp-use,kill>
********** EMITTING LIVE DEBUG VARIABLES **********
********** Stack Slot Coloring **********
********** Function: test_nocall_hipecc
******** Post-regalloc Machine LICM: test_nocall_hipecc ********
Machine Function
********** EXPANDING POST-RA PSEUDO INSTRS **********
********** Function: test_nocall_hipecc
real copy:   %R15<def> = COPY %R15D, %R15<imp-use,kill>
Cannot copy R15D to R15
Cannot emit physreg copy instruction
UNREACHABLE executed at X86InstrInfo.cpp:2487!
0  llc             0x000000000147cf1a
1  llc             0x000000000147cd16
2  libpthread.so.0 0x00007f5d01c4e030
3  libc.so.6       0x00007f5d00f47475 gsignal + 53
4  libc.so.6       0x00007f5d00f4a6f0 abort + 384
5  llc             0x0000000001467b27
6  llc             0x0000000000cddd0d llvm::X86InstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineBasicBlock::bundle_iterator<llvm::MachineInstr, llvm::ilist_iterator<llvm::MachineInstr> >, llvm::DebugLoc, unsigned int, unsigned int, bool) const + 1401
7  llc             0x000000000107cb95
8  llc             0x000000000107cf59
9  llc             0x0000000000f7080d llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
10 llc             0x000000000140a7d6 llvm::FPPassManager::runOnFunction(llvm::Function&) + 388
11 llc             0x000000000140a9f1 llvm::FPPassManager::runOnModule(llvm::Module&) + 107
12 llc             0x000000000140ad31 llvm::MPPassManager::runOnModule(llvm::Module&) + 453
13 llc             0x000000000140b231 llvm::PassManagerImpl::run(llvm::Module&) + 125
14 llc             0x000000000140b3e5 llvm::PassManager::run(llvm::Module&) + 39
15 llc             0x00000000008498c7 main + 3132
16 libc.so.6       0x00007f5d00f33ead __libc_start_main + 253
17 llc             0x00000000008485d9
Stack dump:
0.	Program arguments: llc -debug 
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'Post-RA pseudo instruction expansion pass' on function '@test_nocall_hipecc'
