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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'>Committed in r156609.<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'>Regards,<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'>Silviu<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'><o:p> </o:p></span></p>
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<p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:
"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;
font-family:"Tahoma","sans-serif"'> Jim Grosbach [mailto:grosbach@apple.com] <br>
<b>Sent:</b> 10 May 2012 18:10<br>
<b>To:</b> Silviu Baranga<br>
<b>Cc:</b> llvm-commits@cs.uiuc.edu<br>
<b>Subject:</b> Re: [PATCH] Missing bit definition for STR post reg instruction
on ARM<o:p></o:p></span></p>
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<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>LGTM!<o:p></o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal>-Jim<o:p></o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal>On May 10, 2012, at 9:41 AM, Silviu Baranga <<a
href="mailto:silbar01@arm.com">silbar01@arm.com</a>> wrote:<o:p></o:p></p>
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<br>
<o:p></o:p></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Hi,<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>The
4<sup>th</sup><span class=apple-converted-space> </span>bit of the STR
(post reg) instruction in the ARM backend is currently not defined. It should
be set<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>to
0. This is causing other instructions(such as SEL) to be disassembled as STR
instructions. The patch<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>adds
the missing definition.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>The
instructions that were being wrongly disassembled as STR instructions also had
missing unpredictable <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>bitfield
specifications. The patch also sets the bits in the “Unpredictable” mask for
these instructions.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>We
add regression tests for all the affected instructions.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Please
review this patch.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Thanks,<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Silviu<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:13.5pt;font-family:"Helvetica","sans-serif"'><sel.diff><o:p></o:p></span></p>
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<p class=MsoNormal><o:p> </o:p></p>
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