Just FYI, I fixed a warning in this code with r156209. You'll probably want to start using a bootstrapped Clang for builds so you get more of the warnings we care about with LLVM.<div><br></div><div>Thanks for the great contribution.<br>
<br><div class="gmail_quote">On Fri, May 4, 2012 at 1:18 PM, Justin Holewinski <span dir="ltr"><<a href="mailto:jholewinski@nvidia.com" target="_blank">jholewinski@nvidia.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: jholewinski<br>
Date: Fri May 4 15:18:50 2012<br>
New Revision: 156196<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=156196&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=156196&view=rev</a><br>
Log:<br>
This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.<br>
<br>
The new target machines are:<br>
<br>
nvptx (old ptx32) => 32-bit PTX<br>
nvptx64 (old ptx64) => 64-bit PTX<br>
<br>
The sources are based on the internal NVIDIA NVPTX back-end, and<br>
contain more functionality than the current PTX back-end currently<br>
provides.<br>
<br>
NV_CONTRIB<br>
<br>
Added:<br>
llvm/trunk/include/llvm/IntrinsicsNVVM.td<br>
llvm/trunk/lib/Target/NVPTX/<br>
llvm/trunk/lib/Target/NVPTX/CMakeLists.txt<br>
llvm/trunk/lib/Target/NVPTX/InstPrinter/<br>
llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt<br>
llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt<br>
llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile<br>
llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp<br>
llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp<br>
llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h<br>
llvm/trunk/lib/Target/NVPTX/Makefile<br>
llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTX.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTX.td<br>
llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXFrameLowering.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXInstrFormats.td<br>
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.td<br>
llvm/trunk/lib/Target/NVPTX/NVPTXIntrinsics.td<br>
llvm/trunk/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXLowerAggrCopies.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXNumRegisters.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.td<br>
llvm/trunk/lib/Target/NVPTX/NVPTXSection.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXSplitBBatBar.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXSubtarget.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXTargetMachine.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXTargetObjectFile.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXUtilities.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXUtilities.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXVector.td<br>
llvm/trunk/lib/Target/NVPTX/NVPTXutil.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXutil.h<br>
llvm/trunk/lib/Target/NVPTX/TargetInfo/<br>
llvm/trunk/lib/Target/NVPTX/TargetInfo/CMakeLists.txt<br>
llvm/trunk/lib/Target/NVPTX/TargetInfo/LLVMBuild.txt<br>
llvm/trunk/lib/Target/NVPTX/TargetInfo/Makefile<br>
llvm/trunk/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp<br>
llvm/trunk/lib/Target/NVPTX/VectorElementize.cpp<br>
llvm/trunk/lib/Target/NVPTX/cl_common_defines.h<br>
llvm/trunk/lib/Target/NVPTX/gen-register-defs.py<br>
llvm/trunk/test/CodeGen/NVPTX/<br>
llvm/trunk/test/CodeGen/NVPTX/annotations.ll<br>
llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm10.ll<br>
llvm/trunk/test/CodeGen/NVPTX/arithmetic-fp-sm20.ll<br>
llvm/trunk/test/CodeGen/NVPTX/arithmetic-int.ll<br>
llvm/trunk/test/CodeGen/NVPTX/calling-conv.ll<br>
llvm/trunk/test/CodeGen/NVPTX/compare-int.ll<br>
llvm/trunk/test/CodeGen/NVPTX/convert-fp.ll<br>
llvm/trunk/test/CodeGen/NVPTX/convert-int-sm10.ll<br>
llvm/trunk/test/CodeGen/NVPTX/convert-int-sm20.ll<br>
llvm/trunk/test/CodeGen/NVPTX/fma-disable.ll<br>
llvm/trunk/test/CodeGen/NVPTX/fma.ll<br>
llvm/trunk/test/CodeGen/NVPTX/intrinsic-old.ll<br>
llvm/trunk/test/CodeGen/NVPTX/ld-addrspace.ll<br>
llvm/trunk/test/CodeGen/NVPTX/ld-generic.ll<br>
llvm/trunk/test/CodeGen/NVPTX/lit.local.cfg<br>
llvm/trunk/test/CodeGen/NVPTX/st-addrspace.ll<br>
llvm/trunk/test/CodeGen/NVPTX/st-generic.ll<br>
Modified:<br>
llvm/trunk/CMakeLists.txt<br>
llvm/trunk/autoconf/<a href="http://configure.ac" target="_blank">configure.ac</a><br>
llvm/trunk/configure<br>
llvm/trunk/include/llvm/ADT/Triple.h<br>
llvm/trunk/include/llvm/Intrinsics.td<br>
llvm/trunk/lib/Support/Triple.cpp<br>
llvm/trunk/lib/Target/LLVMBuild.txt<br>
llvm/trunk/projects/sample/autoconf/<a href="http://configure.ac" target="_blank">configure.ac</a><br>
llvm/trunk/projects/sample/configure<br>
<br>
Modified: llvm/trunk/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/CMakeLists.txt (original)<br>
+++ llvm/trunk/CMakeLists.txt Fri May 4 15:18:50 2012<br>
@@ -78,6 +78,7 @@<br>
Mips<br>
MBlaze<br>
MSP430<br>
+ NVPTX<br>
PowerPC<br>
PTX<br>
Sparc<br>
<br>
Modified: llvm/trunk/autoconf/<a href="http://configure.ac" target="_blank">configure.ac</a><br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/autoconf/<a href="http://configure.ac" target="_blank">configure.ac</a> (original)<br>
+++ llvm/trunk/autoconf/<a href="http://configure.ac" target="_blank">configure.ac</a> Fri May 4 15:18:50 2012<br>
@@ -370,6 +370,7 @@<br>
hexagon-*) llvm_cv_target_arch="Hexagon" ;;<br>
mblaze-*) llvm_cv_target_arch="MBlaze" ;;<br>
ptx-*) llvm_cv_target_arch="PTX" ;;<br>
+ nvptx-*) llvm_cv_target_arch="NVPTX" ;;<br>
*) llvm_cv_target_arch="Unknown" ;;<br>
esac])<br>
<br>
@@ -517,6 +518,7 @@<br>
Hexagon) AC_SUBST(TARGET_HAS_JIT,0) ;;<br>
MBlaze) AC_SUBST(TARGET_HAS_JIT,0) ;;<br>
PTX) AC_SUBST(TARGET_HAS_JIT,0) ;;<br>
+ NVPTX) AC_SUBST(TARGET_HAS_JIT,0) ;;<br>
*) AC_SUBST(TARGET_HAS_JIT,0) ;;<br>
esac<br>
fi<br>
@@ -628,13 +630,13 @@<br>
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],<br>
[Build specific host targets: all or target1,target2,... Valid targets are:<br>
host, x86, x86_64, sparc, powerpc, arm, mips, spu, hexagon,<br>
- xcore, msp430, ptx, and cpp (default=all)]),,<br>
+ xcore, msp430, ptx, nvptx, and cpp (default=all)]),,<br>
enableval=all)<br>
if test "$enableval" = host-only ; then<br>
enableval=host<br>
fi<br>
case "$enableval" in<br>
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze PTX Hexagon" ;;<br>
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze PTX NVPTX Hexagon" ;;<br>
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do<br>
case "$a_target" in<br>
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;<br>
@@ -651,6 +653,7 @@<br>
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;<br>
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;<br>
ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;<br>
+ nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;<br>
host) case "$llvm_cv_target_arch" in<br>
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;<br>
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;<br>
@@ -664,6 +667,7 @@<br>
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;<br>
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;<br>
PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;<br>
+ NVPTX) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;<br>
*) AC_MSG_ERROR([Can not set target to build]) ;;<br>
esac ;;<br>
*) AC_MSG_ERROR([Unrecognized target $a_target]) ;;<br>
<br>
Modified: llvm/trunk/configure<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/configure (original)<br>
+++ llvm/trunk/configure Fri May 4 15:18:50 2012<br>
@@ -1420,7 +1420,7 @@<br>
--enable-targets Build specific host targets: all or<br>
target1,target2,... Valid targets are: host, x86,<br>
x86_64, sparc, powerpc, arm, mips, spu, hexagon,<br>
- xcore, msp430, ptx, and cpp (default=all)<br>
+ xcore, msp430, ptx, nvptx, and cpp (default=all)<br>
--enable-bindings Build specific language bindings:<br>
all,auto,none,{binding-name} (default=auto)<br>
--enable-libffi Check for the presence of libffi (default is NO)<br>
@@ -3903,6 +3903,7 @@<br>
hexagon-*) llvm_cv_target_arch="Hexagon" ;;<br>
mblaze-*) llvm_cv_target_arch="MBlaze" ;;<br>
ptx-*) llvm_cv_target_arch="PTX" ;;<br>
+ nvptx-*) llvm_cv_target_arch="NVPTX" ;;<br>
*) llvm_cv_target_arch="Unknown" ;;<br>
esac<br>
fi<br>
@@ -5126,6 +5127,8 @@<br>
;;<br>
PTX) TARGET_HAS_JIT=0<br>
;;<br>
+ NVPTX) TARGET_HAS_JIT=0<br>
+ ;;<br>
*) TARGET_HAS_JIT=0<br>
;;<br>
esac<br>
@@ -5310,7 +5313,7 @@<br>
enableval=host<br>
fi<br>
case "$enableval" in<br>
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze PTX Hexagon" ;;<br>
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze PTX NVPTX Hexagon" ;;<br>
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do<br>
case "$a_target" in<br>
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;<br>
@@ -5327,6 +5330,7 @@<br>
hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;<br>
mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;<br>
ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;<br>
+ nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;<br>
host) case "$llvm_cv_target_arch" in<br>
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;<br>
x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;<br>
@@ -5340,6 +5344,7 @@<br>
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;<br>
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;<br>
PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;;<br>
+ NVPTX) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;;<br>
*) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5<br>
echo "$as_me: error: Can not set target to build" >&2;}<br>
{ (exit 1); exit 1; }; } ;;<br>
@@ -10401,7 +10406,7 @@<br>
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2<br>
lt_status=$lt_dlunknown<br>
cat > conftest.$ac_ext <<EOF<br>
-#line 10404 "configure"<br>
+#line 10409 "configure"<br>
#include "confdefs.h"<br>
<br>
#if HAVE_DLFCN_H<br>
<br>
Modified: llvm/trunk/include/llvm/ADT/Triple.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/ADT/Triple.h (original)<br>
+++ llvm/trunk/include/llvm/ADT/Triple.h Fri May 4 15:18:50 2012<br>
@@ -64,6 +64,8 @@<br>
mblaze, // MBlaze: mblaze<br>
ptx32, // PTX: ptx (32-bit)<br>
ptx64, // PTX: ptx (64-bit)<br>
+ nvptx, // NVPTX: 32-bit<br>
+ nvptx64, // NVPTX: 64-bit<br>
le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)<br>
amdil // amdil: amd IL<br>
};<br>
<br>
Modified: llvm/trunk/include/llvm/Intrinsics.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Intrinsics.td (original)<br>
+++ llvm/trunk/include/llvm/Intrinsics.td Fri May 4 15:18:50 2012<br>
@@ -441,3 +441,4 @@<br>
include "llvm/IntrinsicsXCore.td"<br>
include "llvm/IntrinsicsPTX.td"<br>
include "llvm/IntrinsicsHexagon.td"<br>
+include "llvm/IntrinsicsNVVM.td"<br>
<br>
Added: llvm/trunk/include/llvm/IntrinsicsNVVM.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsNVVM.td?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsNVVM.td?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IntrinsicsNVVM.td (added)<br>
+++ llvm/trunk/include/llvm/IntrinsicsNVVM.td Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,872 @@<br>
+//===- IntrinsicsNVVM.td - Defines NVVM intrinsics ---------*- tablegen -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file defines all of the NVVM-specific intrinsics for use with NVPTX.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+def llvm_anyi64ptr_ty : LLVMAnyPointerType<llvm_i64_ty>; // (space)i64*<br>
+<br>
+//<br>
+// MISC<br>
+//<br>
+<br>
+ def int_nvvm_clz_i : GCCBuiltin<"__nvvm_clz_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_clz_ll : GCCBuiltin<"__nvvm_clz_ll">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_popc_i : GCCBuiltin<"__nvvm_popc_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_popc_ll : GCCBuiltin<"__nvvm_popc_ll">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_prmt : GCCBuiltin<"__nvvm_prmt">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Min Max<br>
+//<br>
+<br>
+ def int_nvvm_min_i : GCCBuiltin<"__nvvm_min_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_min_ui : GCCBuiltin<"__nvvm_min_ui">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_min_ll : GCCBuiltin<"__nvvm_min_ll">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_min_ull : GCCBuiltin<"__nvvm_min_ull">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_max_i : GCCBuiltin<"__nvvm_max_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_max_ui : GCCBuiltin<"__nvvm_max_ui">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_max_ll : GCCBuiltin<"__nvvm_max_ll">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_max_ull : GCCBuiltin<"__nvvm_max_ull">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_fmin_f : GCCBuiltin<"__nvvm_fmin_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fmin_ftz_f : GCCBuiltin<"__nvvm_fmin_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_fmax_f : GCCBuiltin<"__nvvm_fmax_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty]<br>
+ , [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fmax_ftz_f : GCCBuiltin<"__nvvm_fmax_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_fmin_d : GCCBuiltin<"__nvvm_fmin_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fmax_d : GCCBuiltin<"__nvvm_fmax_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Multiplication<br>
+//<br>
+<br>
+ def int_nvvm_mulhi_i : GCCBuiltin<"__nvvm_mulhi_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mulhi_ui : GCCBuiltin<"__nvvm_mulhi_ui">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_mulhi_ll : GCCBuiltin<"__nvvm_mulhi_ll">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mulhi_ull : GCCBuiltin<"__nvvm_mulhi_ull">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_mul_rn_ftz_f : GCCBuiltin<"__nvvm_mul_rn_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rn_f : GCCBuiltin<"__nvvm_mul_rn_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rz_ftz_f : GCCBuiltin<"__nvvm_mul_rz_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rz_f : GCCBuiltin<"__nvvm_mul_rz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rm_ftz_f : GCCBuiltin<"__nvvm_mul_rm_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rm_f : GCCBuiltin<"__nvvm_mul_rm_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rp_ftz_f : GCCBuiltin<"__nvvm_mul_rp_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rp_f : GCCBuiltin<"__nvvm_mul_rp_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_mul_rn_d : GCCBuiltin<"__nvvm_mul_rn_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rz_d : GCCBuiltin<"__nvvm_mul_rz_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rm_d : GCCBuiltin<"__nvvm_mul_rm_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul_rp_d : GCCBuiltin<"__nvvm_mul_rp_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_mul24_i : GCCBuiltin<"__nvvm_mul24_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_mul24_ui : GCCBuiltin<"__nvvm_mul24_ui">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Div<br>
+//<br>
+<br>
+ def int_nvvm_div_approx_ftz_f : GCCBuiltin<"__nvvm_div_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_approx_f : GCCBuiltin<"__nvvm_div_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_div_rn_ftz_f : GCCBuiltin<"__nvvm_div_rn_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rn_f : GCCBuiltin<"__nvvm_div_rn_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_div_rz_ftz_f : GCCBuiltin<"__nvvm_div_rz_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rz_f : GCCBuiltin<"__nvvm_div_rz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_div_rm_ftz_f : GCCBuiltin<"__nvvm_div_rm_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rm_f : GCCBuiltin<"__nvvm_div_rm_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_div_rp_ftz_f : GCCBuiltin<"__nvvm_div_rp_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rp_f : GCCBuiltin<"__nvvm_div_rp_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_div_rn_d : GCCBuiltin<"__nvvm_div_rn_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rz_d : GCCBuiltin<"__nvvm_div_rz_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rm_d : GCCBuiltin<"__nvvm_div_rm_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_div_rp_d : GCCBuiltin<"__nvvm_div_rp_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Brev<br>
+//<br>
+<br>
+ def int_nvvm_brev32 : GCCBuiltin<"__nvvm_brev32">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_brev64 : GCCBuiltin<"__nvvm_brev64">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Sad<br>
+//<br>
+<br>
+ def int_nvvm_sad_i : GCCBuiltin<"__nvvm_sad_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_sad_ui : GCCBuiltin<"__nvvm_sad_ui">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Floor Ceil<br>
+//<br>
+<br>
+ def int_nvvm_floor_ftz_f : GCCBuiltin<"__nvvm_floor_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_floor_f : GCCBuiltin<"__nvvm_floor_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_floor_d : GCCBuiltin<"__nvvm_floor_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_ceil_ftz_f : GCCBuiltin<"__nvvm_ceil_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ceil_f : GCCBuiltin<"__nvvm_ceil_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ceil_d : GCCBuiltin<"__nvvm_ceil_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Abs<br>
+//<br>
+<br>
+ def int_nvvm_abs_i : GCCBuiltin<"__nvvm_abs_i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_abs_ll : GCCBuiltin<"__nvvm_abs_ll">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_fabs_ftz_f : GCCBuiltin<"__nvvm_fabs_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_fabs_f : GCCBuiltin<"__nvvm_fabs_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_fabs_d : GCCBuiltin<"__nvvm_fabs_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Round<br>
+//<br>
+<br>
+ def int_nvvm_round_ftz_f : GCCBuiltin<"__nvvm_round_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_round_f : GCCBuiltin<"__nvvm_round_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_round_d : GCCBuiltin<"__nvvm_round_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Trunc<br>
+//<br>
+<br>
+ def int_nvvm_trunc_ftz_f : GCCBuiltin<"__nvvm_trunc_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_trunc_f : GCCBuiltin<"__nvvm_trunc_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_trunc_d : GCCBuiltin<"__nvvm_trunc_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Saturate<br>
+//<br>
+<br>
+ def int_nvvm_saturate_ftz_f : GCCBuiltin<"__nvvm_saturate_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_saturate_f : GCCBuiltin<"__nvvm_saturate_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_saturate_d : GCCBuiltin<"__nvvm_saturate_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Exp2 Log2<br>
+//<br>
+<br>
+ def int_nvvm_ex2_approx_ftz_f : GCCBuiltin<"__nvvm_ex2_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ex2_approx_f : GCCBuiltin<"__nvvm_ex2_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ex2_approx_d : GCCBuiltin<"__nvvm_ex2_approx_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_lg2_approx_ftz_f : GCCBuiltin<"__nvvm_lg2_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_lg2_approx_f : GCCBuiltin<"__nvvm_lg2_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_lg2_approx_d : GCCBuiltin<"__nvvm_lg2_approx_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Sin Cos<br>
+//<br>
+<br>
+ def int_nvvm_sin_approx_ftz_f : GCCBuiltin<"__nvvm_sin_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sin_approx_f : GCCBuiltin<"__nvvm_sin_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_cos_approx_ftz_f : GCCBuiltin<"__nvvm_cos_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_cos_approx_f : GCCBuiltin<"__nvvm_cos_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Fma<br>
+//<br>
+<br>
+ def int_nvvm_fma_rn_ftz_f : GCCBuiltin<"__nvvm_fma_rn_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rn_f : GCCBuiltin<"__nvvm_fma_rn_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rz_ftz_f : GCCBuiltin<"__nvvm_fma_rz_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rz_f : GCCBuiltin<"__nvvm_fma_rz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rm_ftz_f : GCCBuiltin<"__nvvm_fma_rm_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rm_f : GCCBuiltin<"__nvvm_fma_rm_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rp_ftz_f : GCCBuiltin<"__nvvm_fma_rp_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rp_f : GCCBuiltin<"__nvvm_fma_rp_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_fma_rn_d : GCCBuiltin<"__nvvm_fma_rn_d">,<br>
+ Intrinsic<[llvm_double_ty],<br>
+ [llvm_double_ty, llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rz_d : GCCBuiltin<"__nvvm_fma_rz_d">,<br>
+ Intrinsic<[llvm_double_ty],<br>
+ [llvm_double_ty, llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rm_d : GCCBuiltin<"__nvvm_fma_rm_d">,<br>
+ Intrinsic<[llvm_double_ty],<br>
+ [llvm_double_ty, llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_fma_rp_d : GCCBuiltin<"__nvvm_fma_rp_d">,<br>
+ Intrinsic<[llvm_double_ty],<br>
+ [llvm_double_ty, llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Rcp<br>
+//<br>
+<br>
+ def int_nvvm_rcp_rn_ftz_f : GCCBuiltin<"__nvvm_rcp_rn_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rn_f : GCCBuiltin<"__nvvm_rcp_rn_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rz_ftz_f : GCCBuiltin<"__nvvm_rcp_rz_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rz_f : GCCBuiltin<"__nvvm_rcp_rz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rm_ftz_f : GCCBuiltin<"__nvvm_rcp_rm_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rm_f : GCCBuiltin<"__nvvm_rcp_rm_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rp_ftz_f : GCCBuiltin<"__nvvm_rcp_rp_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rp_f : GCCBuiltin<"__nvvm_rcp_rp_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_rcp_rn_d : GCCBuiltin<"__nvvm_rcp_rn_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rz_d : GCCBuiltin<"__nvvm_rcp_rz_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rm_d : GCCBuiltin<"__nvvm_rcp_rm_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rcp_rp_d : GCCBuiltin<"__nvvm_rcp_rp_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_rcp_approx_ftz_d : GCCBuiltin<"__nvvm_rcp_approx_ftz_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Sqrt<br>
+//<br>
+<br>
+ def int_nvvm_sqrt_rn_ftz_f : GCCBuiltin<"__nvvm_sqrt_rn_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rn_f : GCCBuiltin<"__nvvm_sqrt_rn_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rz_ftz_f : GCCBuiltin<"__nvvm_sqrt_rz_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rz_f : GCCBuiltin<"__nvvm_sqrt_rz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rm_ftz_f : GCCBuiltin<"__nvvm_sqrt_rm_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rm_f : GCCBuiltin<"__nvvm_sqrt_rm_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rp_ftz_f : GCCBuiltin<"__nvvm_sqrt_rp_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rp_f : GCCBuiltin<"__nvvm_sqrt_rp_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_approx_ftz_f : GCCBuiltin<"__nvvm_sqrt_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_approx_f : GCCBuiltin<"__nvvm_sqrt_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_sqrt_rn_d : GCCBuiltin<"__nvvm_sqrt_rn_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rz_d : GCCBuiltin<"__nvvm_sqrt_rz_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rm_d : GCCBuiltin<"__nvvm_sqrt_rm_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_sqrt_rp_d : GCCBuiltin<"__nvvm_sqrt_rp_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Rsqrt<br>
+//<br>
+<br>
+ def int_nvvm_rsqrt_approx_ftz_f : GCCBuiltin<"__nvvm_rsqrt_approx_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rsqrt_approx_f : GCCBuiltin<"__nvvm_rsqrt_approx_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_rsqrt_approx_d : GCCBuiltin<"__nvvm_rsqrt_approx_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Add<br>
+//<br>
+<br>
+ def int_nvvm_add_rn_ftz_f : GCCBuiltin<"__nvvm_add_rn_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rn_f : GCCBuiltin<"__nvvm_add_rn_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rz_ftz_f : GCCBuiltin<"__nvvm_add_rz_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rz_f : GCCBuiltin<"__nvvm_add_rz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rm_ftz_f : GCCBuiltin<"__nvvm_add_rm_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rm_f : GCCBuiltin<"__nvvm_add_rm_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rp_ftz_f : GCCBuiltin<"__nvvm_add_rp_ftz_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rp_f : GCCBuiltin<"__nvvm_add_rp_f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_add_rn_d : GCCBuiltin<"__nvvm_add_rn_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rz_d : GCCBuiltin<"__nvvm_add_rz_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rm_d : GCCBuiltin<"__nvvm_add_rm_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+ def int_nvvm_add_rp_d : GCCBuiltin<"__nvvm_add_rp_d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_double_ty, llvm_double_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+//<br>
+// Convert<br>
+//<br>
+<br>
+ def int_nvvm_d2f_rn_ftz : GCCBuiltin<"__nvvm_d2f_rn_ftz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rn : GCCBuiltin<"__nvvm_d2f_rn">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rz_ftz : GCCBuiltin<"__nvvm_d2f_rz_ftz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rz : GCCBuiltin<"__nvvm_d2f_rz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rm_ftz : GCCBuiltin<"__nvvm_d2f_rm_ftz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rm : GCCBuiltin<"__nvvm_d2f_rm">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rp_ftz : GCCBuiltin<"__nvvm_d2f_rp_ftz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2f_rp : GCCBuiltin<"__nvvm_d2f_rp">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_d2i_rn : GCCBuiltin<"__nvvm_d2i_rn">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2i_rz : GCCBuiltin<"__nvvm_d2i_rz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2i_rm : GCCBuiltin<"__nvvm_d2i_rm">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2i_rp : GCCBuiltin<"__nvvm_d2i_rp">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_d2ui_rn : GCCBuiltin<"__nvvm_d2ui_rn">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ui_rz : GCCBuiltin<"__nvvm_d2ui_rz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ui_rm : GCCBuiltin<"__nvvm_d2ui_rm">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ui_rp : GCCBuiltin<"__nvvm_d2ui_rp">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_i2d_rn : GCCBuiltin<"__nvvm_i2d_rn">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_i2d_rz : GCCBuiltin<"__nvvm_i2d_rz">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_i2d_rm : GCCBuiltin<"__nvvm_i2d_rm">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_i2d_rp : GCCBuiltin<"__nvvm_i2d_rp">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_ui2d_rn : GCCBuiltin<"__nvvm_ui2d_rn">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ui2d_rz : GCCBuiltin<"__nvvm_ui2d_rz">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ui2d_rm : GCCBuiltin<"__nvvm_ui2d_rm">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ui2d_rp : GCCBuiltin<"__nvvm_ui2d_rp">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_f2i_rn_ftz : GCCBuiltin<"__nvvm_f2i_rn_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rn : GCCBuiltin<"__nvvm_f2i_rn">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rz_ftz : GCCBuiltin<"__nvvm_f2i_rz_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rz : GCCBuiltin<"__nvvm_f2i_rz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rm_ftz : GCCBuiltin<"__nvvm_f2i_rm_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rm : GCCBuiltin<"__nvvm_f2i_rm">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rp_ftz : GCCBuiltin<"__nvvm_f2i_rp_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2i_rp : GCCBuiltin<"__nvvm_f2i_rp">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_f2ui_rn_ftz : GCCBuiltin<"__nvvm_f2ui_rn_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rn : GCCBuiltin<"__nvvm_f2ui_rn">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rz_ftz : GCCBuiltin<"__nvvm_f2ui_rz_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rz : GCCBuiltin<"__nvvm_f2ui_rz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rm_ftz : GCCBuiltin<"__nvvm_f2ui_rm_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rm : GCCBuiltin<"__nvvm_f2ui_rm">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rp_ftz : GCCBuiltin<"__nvvm_f2ui_rp_ftz">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ui_rp : GCCBuiltin<"__nvvm_f2ui_rp">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_i2f_rn : GCCBuiltin<"__nvvm_i2f_rn">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_i2f_rz : GCCBuiltin<"__nvvm_i2f_rz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_i2f_rm : GCCBuiltin<"__nvvm_i2f_rm">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_i2f_rp : GCCBuiltin<"__nvvm_i2f_rp">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_ui2f_rn : GCCBuiltin<"__nvvm_ui2f_rn">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ui2f_rz : GCCBuiltin<"__nvvm_ui2f_rz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ui2f_rm : GCCBuiltin<"__nvvm_ui2f_rm">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ui2f_rp : GCCBuiltin<"__nvvm_ui2f_rp">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_lohi_i2d : GCCBuiltin<"__nvvm_lohi_i2d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i32_ty, llvm_i32_ty],<br>
+ [IntrNoMem, Commutative]>;<br>
+<br>
+ def int_nvvm_d2i_lo : GCCBuiltin<"__nvvm_d2i_lo">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2i_hi : GCCBuiltin<"__nvvm_d2i_hi">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_f2ll_rn_ftz : GCCBuiltin<"__nvvm_f2ll_rn_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rn : GCCBuiltin<"__nvvm_f2ll_rn">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rz_ftz : GCCBuiltin<"__nvvm_f2ll_rz_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rz : GCCBuiltin<"__nvvm_f2ll_rz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rm_ftz : GCCBuiltin<"__nvvm_f2ll_rm_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rm : GCCBuiltin<"__nvvm_f2ll_rm">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rp_ftz : GCCBuiltin<"__nvvm_f2ll_rp_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ll_rp : GCCBuiltin<"__nvvm_f2ll_rp">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_f2ull_rn_ftz : GCCBuiltin<"__nvvm_f2ull_rn_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rn : GCCBuiltin<"__nvvm_f2ull_rn">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rz_ftz : GCCBuiltin<"__nvvm_f2ull_rz_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rz : GCCBuiltin<"__nvvm_f2ull_rz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rm_ftz : GCCBuiltin<"__nvvm_f2ull_rm_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rm : GCCBuiltin<"__nvvm_f2ull_rm">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rp_ftz : GCCBuiltin<"__nvvm_f2ull_rp_ftz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2ull_rp : GCCBuiltin<"__nvvm_f2ull_rp">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_d2ll_rn : GCCBuiltin<"__nvvm_d2ll_rn">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ll_rz : GCCBuiltin<"__nvvm_d2ll_rz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ll_rm : GCCBuiltin<"__nvvm_d2ll_rm">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ll_rp : GCCBuiltin<"__nvvm_d2ll_rp">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_d2ull_rn : GCCBuiltin<"__nvvm_d2ull_rn">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ull_rz : GCCBuiltin<"__nvvm_d2ull_rz">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ull_rm : GCCBuiltin<"__nvvm_d2ull_rm">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+ def int_nvvm_d2ull_rp : GCCBuiltin<"__nvvm_d2ull_rp">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_ll2f_rn : GCCBuiltin<"__nvvm_ll2f_rn">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ll2f_rz : GCCBuiltin<"__nvvm_ll2f_rz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ll2f_rm : GCCBuiltin<"__nvvm_ll2f_rm">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ll2f_rp : GCCBuiltin<"__nvvm_ll2f_rp">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2f_rn : GCCBuiltin<"__nvvm_ull2f_rn">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2f_rz : GCCBuiltin<"__nvvm_ull2f_rz">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2f_rm : GCCBuiltin<"__nvvm_ull2f_rm">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2f_rp : GCCBuiltin<"__nvvm_ull2f_rp">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_ll2d_rn : GCCBuiltin<"__nvvm_ll2d_rn">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ll2d_rz : GCCBuiltin<"__nvvm_ll2d_rz">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ll2d_rm : GCCBuiltin<"__nvvm_ll2d_rm">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ll2d_rp : GCCBuiltin<"__nvvm_ll2d_rp">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2d_rn : GCCBuiltin<"__nvvm_ull2d_rn">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2d_rz : GCCBuiltin<"__nvvm_ull2d_rz">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2d_rm : GCCBuiltin<"__nvvm_ull2d_rm">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_ull2d_rp : GCCBuiltin<"__nvvm_ull2d_rp">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_f2h_rn_ftz : GCCBuiltin<"__nvvm_f2h_rn_ftz">,<br>
+ Intrinsic<[llvm_i16_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_f2h_rn : GCCBuiltin<"__nvvm_f2h_rn">,<br>
+ Intrinsic<[llvm_i16_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_h2f : GCCBuiltin<"__nvvm_h2f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i16_ty], [IntrNoMem]>;<br>
+<br>
+//<br>
+// Bitcast<br>
+//<br>
+<br>
+ def int_nvvm_bitcast_f2i : GCCBuiltin<"__nvvm_bitcast_f2i">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;<br>
+ def int_nvvm_bitcast_i2f : GCCBuiltin<"__nvvm_bitcast_i2f">,<br>
+ Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+<br>
+ def int_nvvm_bitcast_ll2d : GCCBuiltin<"__nvvm_bitcast_ll2d">,<br>
+ Intrinsic<[llvm_double_ty], [llvm_i64_ty], [IntrNoMem]>;<br>
+ def int_nvvm_bitcast_d2ll : GCCBuiltin<"__nvvm_bitcast_d2ll">,<br>
+ Intrinsic<[llvm_i64_ty], [llvm_double_ty], [IntrNoMem]>;<br>
+<br>
+<br>
+// Atomic not available as an llvm intrinsic.<br>
+ def int_nvvm_atomic_load_add_f32 : Intrinsic<[llvm_float_ty],<br>
+ [LLVMAnyPointerType<llvm_float_ty>, llvm_float_ty],<br>
+ [IntrReadWriteArgMem, NoCapture<0>]>;<br>
+ def int_nvvm_atomic_load_inc_32 : Intrinsic<[llvm_i32_ty],<br>
+ [LLVMAnyPointerType<llvm_i32_ty>, llvm_i32_ty],<br>
+ [IntrReadWriteArgMem, NoCapture<0>]>;<br>
+ def int_nvvm_atomic_load_dec_32 : Intrinsic<[llvm_i32_ty],<br>
+ [LLVMAnyPointerType<llvm_i32_ty>, llvm_i32_ty],<br>
+ [IntrReadWriteArgMem, NoCapture<0>]>;<br>
+<br>
+// Bar.Sync<br>
+ def int_cuda_syncthreads : GCCBuiltin<"__syncthreads">,<br>
+ Intrinsic<[], [], []>;<br>
+ def int_nvvm_barrier0 : GCCBuiltin<"__nvvm_bar0">,<br>
+ Intrinsic<[], [], []>;<br>
+ def int_nvvm_barrier0_popc : GCCBuiltin<"__nvvm_bar0_popc">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;<br>
+ def int_nvvm_barrier0_and : GCCBuiltin<"__nvvm_bar0_and">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;<br>
+ def int_nvvm_barrier0_or : GCCBuiltin<"__nvvm_bar0_or">,<br>
+ Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;<br>
+<br>
+ // Membar<br>
+ def int_nvvm_membar_cta : GCCBuiltin<"__nvvm_membar_cta">,<br>
+ Intrinsic<[], [], []>;<br>
+ def int_nvvm_membar_gl : GCCBuiltin<"__nvvm_membar_gl">,<br>
+ Intrinsic<[], [], []>;<br>
+ def int_nvvm_membar_sys : GCCBuiltin<"__nvvm_membar_sys">,<br>
+ Intrinsic<[], [], []>;<br>
+<br>
+<br>
+// Accessing special registers<br>
+ def int_nvvm_read_ptx_sreg_tid_x :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_tid_x">;<br>
+ def int_nvvm_read_ptx_sreg_tid_y :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_tid_y">;<br>
+ def int_nvvm_read_ptx_sreg_tid_z :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_tid_z">;<br>
+<br>
+ def int_nvvm_read_ptx_sreg_ntid_x :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_ntid_x">;<br>
+ def int_nvvm_read_ptx_sreg_ntid_y :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_ntid_y">;<br>
+ def int_nvvm_read_ptx_sreg_ntid_z :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_ntid_z">;<br>
+<br>
+ def int_nvvm_read_ptx_sreg_ctaid_x :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_ctaid_x">;<br>
+ def int_nvvm_read_ptx_sreg_ctaid_y :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_ctaid_y">;<br>
+ def int_nvvm_read_ptx_sreg_ctaid_z :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_ctaid_z">;<br>
+<br>
+ def int_nvvm_read_ptx_sreg_nctaid_x :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_nctaid_x">;<br>
+ def int_nvvm_read_ptx_sreg_nctaid_y :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_nctaid_y">;<br>
+ def int_nvvm_read_ptx_sreg_nctaid_z :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_nctaid_z">;<br>
+<br>
+ def int_nvvm_read_ptx_sreg_warpsize :<br>
+ Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,<br>
+ GCCBuiltin<"__nvvm_read_ptx_sreg_warpsize">;<br>
+<br>
+<br>
+// Generated within nvvm. Use for ldu on sm_20 or later<br>
+// @TODO: Revisit this, Changed LLVMAnyPointerType to LLVMPointerType<br>
+def int_nvvm_ldu_global_i : Intrinsic<[llvm_anyint_ty],<br>
+ [LLVMPointerType<LLVMMatchType<0>>], [IntrReadMem, NoCapture<0>],<br>
+ "llvm.nvvm.ldu.global.i">;<br>
+def int_nvvm_ldu_global_f : Intrinsic<[llvm_anyfloat_ty],<br>
+ [LLVMPointerType<LLVMMatchType<0>>], [IntrReadMem, NoCapture<0>],<br>
+ "llvm.nvvm.ldu.global.f">;<br>
+def int_nvvm_ldu_global_p : Intrinsic<[llvm_anyptr_ty],<br>
+ [LLVMPointerType<LLVMMatchType<0>>], [IntrReadMem, NoCapture<0>],<br>
+ "llvm.nvvm.ldu.global.p">;<br>
+<br>
+<br>
+// Use for generic pointers<br>
+// - These intrinsics are used to convert address spaces.<br>
+// - The input pointer and output pointer must have the same type, except for<br>
+// the address-space. (This restriction is not enforced here as there is<br>
+// currently no way to describe it).<br>
+// - This complements the llvm bitcast, which can be used to cast one type<br>
+// of pointer to another type of pointer, while the address space remains<br>
+// the same.<br>
+def int_nvvm_ptr_local_to_gen: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.local.to.gen">;<br>
+def int_nvvm_ptr_shared_to_gen: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.shared.to.gen">;<br>
+def int_nvvm_ptr_global_to_gen: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.global.to.gen">;<br>
+def int_nvvm_ptr_constant_to_gen: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.constant.to.gen">;<br>
+<br>
+def int_nvvm_ptr_gen_to_global: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.gen.to.global">;<br>
+def int_nvvm_ptr_gen_to_shared: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.gen.to.shared">;<br>
+def int_nvvm_ptr_gen_to_local: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.gen.to.local">;<br>
+def int_nvvm_ptr_gen_to_constant: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty], [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.gen.to.constant">;<br>
+<br>
+// Used in nvvm internally to help address space opt and ptx code generation<br>
+// This is for params that are passed to kernel functions by pointer by-val.<br>
+def int_nvvm_ptr_gen_to_param: Intrinsic<[llvm_anyptr_ty],<br>
+ [llvm_anyptr_ty],<br>
+ [IntrNoMem, NoCapture<0>],<br>
+ "llvm.nvvm.ptr.gen.to.param">;<br>
+<br>
+// Move intrinsics, used in nvvm internally<br>
+<br>
+def int_nvvm_move_i8 : Intrinsic<[llvm_i8_ty], [llvm_i8_ty], [IntrNoMem],<br>
+ "llvm.nvvm.move.i8">;<br>
+def int_nvvm_move_i16 : Intrinsic<[llvm_i16_ty], [llvm_i16_ty], [IntrNoMem],<br>
+ "llvm.nvvm.move.i16">;<br>
+def int_nvvm_move_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem],<br>
+ "llvm.nvvm.move.i32">;<br>
+def int_nvvm_move_i64 : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem],<br>
+ "llvm.nvvm.move.i64">;<br>
+def int_nvvm_move_float : Intrinsic<[llvm_float_ty], [llvm_float_ty],<br>
+ [IntrNoMem], "llvm.nvvm.move.float">;<br>
+def int_nvvm_move_double : Intrinsic<[llvm_double_ty], [llvm_double_ty],<br>
+ [IntrNoMem], "llvm.nvvm.move.double">;<br>
+def int_nvvm_move_ptr : Intrinsic<[llvm_anyptr_ty], [llvm_anyptr_ty],<br>
+ [IntrNoMem, NoCapture<0>], "llvm.nvvm.move.ptr">;<br>
+<br>
+<br>
+/// Error / Warn<br>
+def int_nvvm_compiler_error :<br>
+ Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.error">;<br>
+def int_nvvm_compiler_warn :<br>
+ Intrinsic<[], [llvm_anyptr_ty], [], "llvm.nvvm.compiler.warn">;<br>
<br>
Modified: llvm/trunk/lib/Support/Triple.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Support/Triple.cpp (original)<br>
+++ llvm/trunk/lib/Support/Triple.cpp Fri May 4 15:18:50 2012<br>
@@ -40,6 +40,8 @@<br>
case mblaze: return "mblaze";<br>
case ptx32: return "ptx32";<br>
case ptx64: return "ptx64";<br>
+ case nvptx: return "nvptx";<br>
+ case nvptx64: return "nvptx64";<br>
case le32: return "le32";<br>
case amdil: return "amdil";<br>
}<br>
@@ -76,6 +78,8 @@<br>
<br>
case ptx32: return "ptx";<br>
case ptx64: return "ptx";<br>
+ case nvptx: return "nvptx";<br>
+ case nvptx64: return "nvptx";<br>
case le32: return "le32";<br>
case amdil: return "amdil";<br>
}<br>
@@ -162,6 +166,8 @@<br>
.Case("xcore", xcore)<br>
.Case("ptx32", ptx32)<br>
.Case("ptx64", ptx64)<br>
+ .Case("nvptx", nvptx)<br>
+ .Case("nvptx64", nvptx64)<br>
.Case("le32", le32)<br>
.Case("amdil", amdil)<br>
.Default(UnknownArch);<br>
@@ -194,6 +200,8 @@<br>
.Case("r600", Triple::r600)<br>
.Case("ptx32", Triple::ptx32)<br>
.Case("ptx64", Triple::ptx64)<br>
+ .Case("nvptx", Triple::nvptx)<br>
+ .Case("nvptx64", Triple::nvptx64)<br>
.Case("amdil", Triple::amdil)<br>
.Default(Triple::UnknownArch);<br>
}<br>
@@ -217,6 +225,8 @@<br>
.Case("r600", "r600")<br>
.Case("ptx32", "ptx32")<br>
.Case("ptx64", "ptx64")<br>
+ .Case("nvptx", "nvptx")<br>
+ .Case("nvptx64", "nvptx64")<br>
.Case("le32", "le32")<br>
.Case("amdil", "amdil")<br>
.Default(NULL);<br>
@@ -251,6 +261,8 @@<br>
.Case("xcore", Triple::xcore)<br>
.Case("ptx32", Triple::ptx32)<br>
.Case("ptx64", Triple::ptx64)<br>
+ .Case("nvptx", Triple::nvptx)<br>
+ .Case("nvptx64", Triple::nvptx64)<br>
.Case("le32", Triple::le32)<br>
.Case("amdil", Triple::amdil)<br>
.Default(Triple::UnknownArch);<br>
@@ -652,6 +664,7 @@<br>
case llvm::Triple::mblaze:<br>
case llvm::Triple::mips:<br>
case llvm::Triple::mipsel:<br>
+ case llvm::Triple::nvptx:<br>
case llvm::Triple::ppc:<br>
case llvm::Triple::ptx32:<br>
case llvm::Triple::r600:<br>
@@ -664,6 +677,7 @@<br>
<br>
case llvm::Triple::mips64:<br>
case llvm::Triple::mips64el:<br>
+ case llvm::Triple::nvptx64:<br>
case llvm::Triple::ppc64:<br>
case llvm::Triple::ptx64:<br>
case llvm::Triple::sparcv9:<br>
@@ -701,6 +715,7 @@<br>
case Triple::mblaze:<br>
case Triple::mips:<br>
case Triple::mipsel:<br>
+ case Triple::nvptx:<br>
case Triple::ppc:<br>
case Triple::ptx32:<br>
case Triple::r600:<br>
@@ -714,6 +729,7 @@<br>
<br>
case Triple::mips64: T.setArch(Triple::mips); break;<br>
case Triple::mips64el: T.setArch(Triple::mipsel); break;<br>
+ case Triple::nvptx64: T.setArch(Triple::nvptx); break;<br>
case Triple::ppc64: T.setArch(Triple::ppc); break;<br>
case Triple::ptx64: T.setArch(Triple::ptx32); break;<br>
case Triple::sparcv9: T.setArch(Triple::sparc); break;<br>
@@ -742,6 +758,7 @@<br>
<br>
case Triple::mips64:<br>
case Triple::mips64el:<br>
+ case Triple::nvptx64:<br>
case Triple::ppc64:<br>
case Triple::ptx64:<br>
case Triple::sparcv9:<br>
@@ -751,6 +768,7 @@<br>
<br>
case Triple::mips: T.setArch(Triple::mips64); break;<br>
case Triple::mipsel: T.setArch(Triple::mips64el); break;<br>
+ case Triple::nvptx: T.setArch(Triple::nvptx64); break;<br>
case Triple::ppc: T.setArch(Triple::ppc64); break;<br>
case Triple::ptx32: T.setArch(Triple::ptx64); break;<br>
case Triple::sparc: T.setArch(Triple::sparcv9); break;<br>
<br>
Modified: llvm/trunk/lib/Target/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=156196&r1=156195&r2=156196&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/LLVMBuild.txt?rev=156196&r1=156195&r2=156196&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/LLVMBuild.txt Fri May 4 15:18:50 2012<br>
@@ -16,7 +16,7 @@<br>
;===------------------------------------------------------------------------===;<br>
<br>
[common]<br>
-subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 Mips PTX PowerPC Sparc X86 XCore<br>
+subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips PTX PowerPC Sparc X86 XCore<br>
<br>
; This is a special group whose required libraries are extended (by llvm-build)<br>
; with the best execution engine (the native JIT, if available, or the<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/CMakeLists.txt?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/CMakeLists.txt?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/CMakeLists.txt (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/CMakeLists.txt Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,33 @@<br>
+set(LLVM_TARGET_DEFINITIONS NVPTX.td)<br>
+<br>
+<br>
+tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)<br>
+tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)<br>
+tablegen(LLVM NVPTXGenAsmWriter.inc -gen-asm-writer)<br>
+tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel)<br>
+tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)<br>
+add_public_tablegen_target(NVPTXCommonTableGen)<br>
+<br>
+set(NVPTXCodeGen_sources<br>
+ NVPTXFrameLowering.cpp<br>
+ NVPTXInstrInfo.cpp<br>
+ NVPTXISelDAGToDAG.cpp<br>
+ NVPTXISelLowering.cpp<br>
+ NVPTXRegisterInfo.cpp<br>
+ NVPTXSubtarget.cpp<br>
+ NVPTXTargetMachine.cpp<br>
+ NVPTXSplitBBatBar.cpp<br>
+ NVPTXLowerAggrCopies.cpp<br>
+ NVPTXutil.cpp<br>
+ NVPTXAllocaHoisting.cpp<br>
+ NVPTXAsmPrinter.cpp<br>
+ NVPTXUtilities.cpp<br>
+ VectorElementize.cpp<br>
+ )<br>
+<br>
+add_llvm_target(NVPTXCodeGen ${NVPTXCodeGen_sources})<br>
+<br>
+<br>
+add_subdirectory(TargetInfo)<br>
+add_subdirectory(InstPrinter)<br>
+add_subdirectory(MCTargetDesc)<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/InstPrinter/CMakeLists.txt Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,7 @@<br>
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )<br>
+<br>
+add_llvm_library(LLVMNVPTXAsmPrinter<br>
+ NVPTXInstPrinter.cpp<br>
+ )<br>
+<br>
+add_dependencies(LLVMNVPTXAsmPrinter NVPTXCommonTableGen)<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/InstPrinter/LLVMBuild.txt Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,23 @@<br>
+;===- ./lib/Target/NVPTX/InstPrinter/LLVMBuild.txt -------------*- Conf -*--===;<br>
+;<br>
+; The LLVM Compiler Infrastructure<br>
+;<br>
+; This file is distributed under the University of Illinois Open Source<br>
+; License. See LICENSE.TXT for details.<br>
+;<br>
+;===------------------------------------------------------------------------===;<br>
+;<br>
+; This is an LLVMBuild description file for the components in this subdirectory.<br>
+;<br>
+; For more information on the LLVMBuild system, please see:<br>
+;<br>
+; <a href="http://llvm.org/docs/LLVMBuild.html" target="_blank">http://llvm.org/docs/LLVMBuild.html</a><br>
+;<br>
+;===------------------------------------------------------------------------===;<br>
+<br>
+[component_0]<br>
+type = Library<br>
+name = NVPTXAsmPrinter<br>
+parent = NVPTX<br>
+required_libraries = MC Support<br>
+add_to_library_groups = NVPTX<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/InstPrinter/Makefile Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,15 @@<br>
+##===- lib/Target/NVPTX/AsmPrinter/Makefile ----------------*- Makefile -*-===##<br>
+#<br>
+# The LLVM Compiler Infrastructure<br>
+#<br>
+# This file is distributed under the University of Illinois Open Source<br>
+# License. See LICENSE.TXT for details.<br>
+#<br>
+##===----------------------------------------------------------------------===##<br>
+LEVEL = ../../../..<br>
+LIBRARYNAME = LLVMNVPTXAsmPrinter<br>
+<br>
+# Hack: we need to include 'main' ptx target directory to grab private headers<br>
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..<br>
+<br>
+include $(LEVEL)/Makefile.common<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.cpp Fri May 4 15:18:50 2012<br>
@@ -0,0 +1 @@<br>
+// Placeholder<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/LLVMBuild.txt Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,32 @@<br>
+;===- ./lib/Target/NVPTX/LLVMBuild.txt -------------------------*- Conf -*--===;<br>
+;<br>
+; The LLVM Compiler Infrastructure<br>
+;<br>
+; This file is distributed under the University of Illinois Open Source<br>
+; License. See LICENSE.TXT for details.<br>
+;<br>
+;===------------------------------------------------------------------------===;<br>
+;<br>
+; This is an LLVMBuild description file for the components in this subdirectory.<br>
+;<br>
+; For more information on the LLVMBuild system, please see:<br>
+;<br>
+; <a href="http://llvm.org/docs/LLVMBuild.html" target="_blank">http://llvm.org/docs/LLVMBuild.html</a><br>
+;<br>
+;===------------------------------------------------------------------------===;<br>
+<br>
+[common]<br>
+subdirectories = InstPrinter MCTargetDesc TargetInfo<br>
+<br>
+[component_0]<br>
+type = TargetGroup<br>
+name = NVPTX<br>
+parent = Target<br>
+has_asmprinter = 1<br>
+<br>
+[component_1]<br>
+type = Library<br>
+name = NVPTXCodeGen<br>
+parent = NVPTX<br>
+required_libraries = Analysis AsmPrinter CodeGen Core MC NVPTXDesc NVPTXInfo SelectionDAG Support Target TransformUtils<br>
+add_to_library_groups = NVPTX<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/CMakeLists.txt Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,9 @@<br>
+add_llvm_library(LLVMNVPTXDesc<br>
+ NVPTXMCAsmInfo.cpp<br>
+ NVPTXMCTargetDesc.cpp<br>
+ )<br>
+<br>
+add_dependencies(LLVMNVPTXDesc NVPTXCommonTableGen)<br>
+<br>
+# Hack: we need to include 'main' target directory to grab private headers<br>
+#include_directories(${CMAKE_CURRENT_SOURCE_DIR}/.. ${CMAKE_CURRENT_BINARY_DIR}/..)<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,23 @@<br>
+;===- ./lib/Target/NVPTX/MCTargetDesc/LLVMBuild.txt ------------*- Conf -*--===;<br>
+;<br>
+; The LLVM Compiler Infrastructure<br>
+;<br>
+; This file is distributed under the University of Illinois Open Source<br>
+; License. See LICENSE.TXT for details.<br>
+;<br>
+;===------------------------------------------------------------------------===;<br>
+;<br>
+; This is an LLVMBuild description file for the components in this subdirectory.<br>
+;<br>
+; For more information on the LLVMBuild system, please see:<br>
+;<br>
+; <a href="http://llvm.org/docs/LLVMBuild.html" target="_blank">http://llvm.org/docs/LLVMBuild.html</a><br>
+;<br>
+;===------------------------------------------------------------------------===;<br>
+<br>
+[component_0]<br>
+type = Library<br>
+name = NVPTXDesc<br>
+parent = NVPTX<br>
+required_libraries = MC NVPTXAsmPrinter NVPTXInfo Support<br>
+add_to_library_groups = NVPTX<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/Makefile Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,16 @@<br>
+##===- lib/Target/NVPTX/TargetDesc/Makefile ----------------*- Makefile -*-===##<br>
+#<br>
+# The LLVM Compiler Infrastructure<br>
+#<br>
+# This file is distributed under the University of Illinois Open Source<br>
+# License. See LICENSE.TXT for details.<br>
+#<br>
+##===----------------------------------------------------------------------===##<br>
+<br>
+LEVEL = ../../../..<br>
+LIBRARYNAME = LLVMNVPTXDesc<br>
+<br>
+# Hack: we need to include 'main' target directory to grab private headers<br>
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..<br>
+<br>
+include $(LEVEL)/Makefile.common<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,88 @@<br>
+//===-- NVPTXBaseInfo.h - Top-level definitions for NVPTX -------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains small standalone helper functions and enum definitions for<br>
+// the NVPTX target useful for the compiler back-end and the MC libraries.<br>
+// As such, it deliberately does not include references to LLVM core<br>
+// code gen types, passes, etc..<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef NVPTXBASEINFO_H<br>
+#define NVPTXBASEINFO_H<br>
+<br>
+namespace llvm {<br>
+<br>
+enum AddressSpace {<br>
+ ADDRESS_SPACE_GENERIC = 0,<br>
+ ADDRESS_SPACE_GLOBAL = 1,<br>
+ ADDRESS_SPACE_CONST_NOT_GEN = 2, // Not part of generic space<br>
+ ADDRESS_SPACE_SHARED = 3,<br>
+ ADDRESS_SPACE_CONST = 4,<br>
+ ADDRESS_SPACE_LOCAL = 5,<br>
+<br>
+ // NVVM Internal<br>
+ ADDRESS_SPACE_PARAM = 101<br>
+};<br>
+<br>
+enum PropertyAnnotation {<br>
+ PROPERTY_MAXNTID_X = 0,<br>
+ PROPERTY_MAXNTID_Y,<br>
+ PROPERTY_MAXNTID_Z,<br>
+ PROPERTY_REQNTID_X,<br>
+ PROPERTY_REQNTID_Y,<br>
+ PROPERTY_REQNTID_Z,<br>
+ PROPERTY_MINNCTAPERSM,<br>
+ PROPERTY_ISTEXTURE,<br>
+ PROPERTY_ISSURFACE,<br>
+ PROPERTY_ISSAMPLER,<br>
+ PROPERTY_ISREADONLY_IMAGE_PARAM,<br>
+ PROPERTY_ISWRITEONLY_IMAGE_PARAM,<br>
+ PROPERTY_ISKERNEL_FUNCTION,<br>
+ PROPERTY_ALIGN,<br>
+<br>
+ // last property<br>
+ PROPERTY_LAST<br>
+};<br>
+<br>
+const unsigned AnnotationNameLen = 8; // length of each annotation name<br>
+const char<br>
+PropertyAnnotationNames[PROPERTY_LAST + 1][AnnotationNameLen + 1] = {<br>
+ "maxntidx", // PROPERTY_MAXNTID_X<br>
+ "maxntidy", // PROPERTY_MAXNTID_Y<br>
+ "maxntidz", // PROPERTY_MAXNTID_Z<br>
+ "reqntidx", // PROPERTY_REQNTID_X<br>
+ "reqntidy", // PROPERTY_REQNTID_Y<br>
+ "reqntidz", // PROPERTY_REQNTID_Z<br>
+ "minctasm", // PROPERTY_MINNCTAPERSM<br>
+ "texture", // PROPERTY_ISTEXTURE<br>
+ "surface", // PROPERTY_ISSURFACE<br>
+ "sampler", // PROPERTY_ISSAMPLER<br>
+ "rdoimage", // PROPERTY_ISREADONLY_IMAGE_PARAM<br>
+ "wroimage", // PROPERTY_ISWRITEONLY_IMAGE_PARAM<br>
+ "kernel", // PROPERTY_ISKERNEL_FUNCTION<br>
+ "align", // PROPERTY_ALIGN<br>
+<br>
+ // last property<br>
+ "proplast", // PROPERTY_LAST<br>
+};<br>
+<br>
+// name of named metadata used for global annotations<br>
+#if defined(__GNUC__)<br>
+// As this is declared to be static but some of the .cpp files that<br>
+// include NVVM.h do not use this array, gcc gives a warning when<br>
+// compiling those .cpp files, hence __attribute__((unused)).<br>
+__attribute__((unused))<br>
+#endif<br>
+static const char* NamedMDForAnnotations = "nvvm.annotations";<br>
+<br>
+}<br>
+<br>
+<br>
+#endif<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,63 @@<br>
+//===-- NVPTXMCAsmInfo.cpp - NVPTX asm properties -------------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains the declarations of the NVPTXMCAsmInfo properties.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "NVPTXMCAsmInfo.h"<br>
+#include "llvm/ADT/Triple.h"<br>
+#include "llvm/Support/CommandLine.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+bool CompileForDebugging;<br>
+<br>
+// -debug-compile - Command line option to inform opt and llc passes to<br>
+// compile for debugging<br>
+static cl::opt<bool, true><br>
+Debug("debug-compile", cl::desc("Compile for debugging"), cl::Hidden,<br>
+ cl::location(CompileForDebugging),<br>
+ cl::init(false));<br>
+<br>
+void NVPTXMCAsmInfo::anchor() { }<br>
+<br>
+NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Target &T, const StringRef &TT) {<br>
+ Triple TheTriple(TT);<br>
+ if (TheTriple.getArch() == Triple::nvptx64)<br>
+ PointerSize = 8;<br>
+<br>
+ CommentString = "//";<br>
+<br>
+ PrivateGlobalPrefix = "$L__";<br>
+<br>
+ AllowPeriodsInName = false;<br>
+<br>
+ HasSetDirective = false;<br>
+<br>
+ HasSingleParameterDotFile = false;<br>
+<br>
+ InlineAsmStart = " inline asm";<br>
+ InlineAsmEnd = " inline asm";<br>
+<br>
+ SupportsDebugInformation = CompileForDebugging;<br>
+ HasDotTypeDotSizeDirective = false;<br>
+<br>
+ Data8bitsDirective = " .b8 ";<br>
+ Data16bitsDirective = " .b16 ";<br>
+ Data32bitsDirective = " .b32 ";<br>
+ Data64bitsDirective = " .b64 ";<br>
+ PrivateGlobalPrefix = "";<br>
+ ZeroDirective = " .b8";<br>
+ AsciiDirective = " .b8";<br>
+ AscizDirective = " .b8";<br>
+<br>
+ // @TODO: Can we just disable this?<br>
+ GlobalDirective = "\t// .globl\t";<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,30 @@<br>
+//===-- NVPTXMCAsmInfo.h - NVPTX asm properties ----------------*- C++ -*--===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains the declaration of the NVPTXMCAsmInfo class.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef NVPTX_MCASM_INFO_H<br>
+#define NVPTX_MCASM_INFO_H<br>
+<br>
+#include "llvm/MC/MCAsmInfo.h"<br>
+<br>
+namespace llvm {<br>
+class Target;<br>
+class StringRef;<br>
+<br>
+class NVPTXMCAsmInfo : public MCAsmInfo {<br>
+ virtual void anchor();<br>
+public:<br>
+ explicit NVPTXMCAsmInfo(const Target &T, const StringRef &TT);<br>
+};<br>
+} // namespace llvm<br>
+<br>
+#endif // NVPTX_MCASM_INFO_H<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,91 @@<br>
+//===-- NVPTXMCTargetDesc.cpp - NVPTX Target Descriptions -------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file provides NVPTX specific target descriptions.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "NVPTXMCTargetDesc.h"<br>
+#include "NVPTXMCAsmInfo.h"<br>
+#include "llvm/MC/MCCodeGenInfo.h"<br>
+#include "llvm/MC/MCInstrInfo.h"<br>
+#include "llvm/MC/MCRegisterInfo.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+<br>
+#define GET_INSTRINFO_MC_DESC<br>
+#include "NVPTXGenInstrInfo.inc"<br>
+<br>
+#define GET_SUBTARGETINFO_MC_DESC<br>
+#include "NVPTXGenSubtargetInfo.inc"<br>
+<br>
+#define GET_REGINFO_MC_DESC<br>
+#include "NVPTXGenRegisterInfo.inc"<br>
+<br>
+<br>
+using namespace llvm;<br>
+<br>
+static MCInstrInfo *createNVPTXMCInstrInfo() {<br>
+ MCInstrInfo *X = new MCInstrInfo();<br>
+ InitNVPTXMCInstrInfo(X);<br>
+ return X;<br>
+}<br>
+<br>
+static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) {<br>
+ MCRegisterInfo *X = new MCRegisterInfo();<br>
+ // PTX does not have a return address register.<br>
+ InitNVPTXMCRegisterInfo(X, 0);<br>
+ return X;<br>
+}<br>
+<br>
+static MCSubtargetInfo *createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU,<br>
+ StringRef FS) {<br>
+ MCSubtargetInfo *X = new MCSubtargetInfo();<br>
+ InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);<br>
+ return X;<br>
+}<br>
+<br>
+static MCCodeGenInfo *createNVPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM,<br>
+ CodeModel::Model CM,<br>
+ CodeGenOpt::Level OL) {<br>
+ MCCodeGenInfo *X = new MCCodeGenInfo();<br>
+ X->InitMCCodeGenInfo(RM, CM, OL);<br>
+ return X;<br>
+}<br>
+<br>
+<br>
+// Force static initialization.<br>
+extern "C" void LLVMInitializeNVPTXTargetMC() {<br>
+ // Register the MC asm info.<br>
+ RegisterMCAsmInfo<NVPTXMCAsmInfo> X(TheNVPTXTarget32);<br>
+ RegisterMCAsmInfo<NVPTXMCAsmInfo> Y(TheNVPTXTarget64);<br>
+<br>
+ // Register the MC codegen info.<br>
+ TargetRegistry::RegisterMCCodeGenInfo(TheNVPTXTarget32,<br>
+ createNVPTXMCCodeGenInfo);<br>
+ TargetRegistry::RegisterMCCodeGenInfo(TheNVPTXTarget64,<br>
+ createNVPTXMCCodeGenInfo);<br>
+<br>
+ // Register the MC instruction info.<br>
+ TargetRegistry::RegisterMCInstrInfo(TheNVPTXTarget32, createNVPTXMCInstrInfo);<br>
+ TargetRegistry::RegisterMCInstrInfo(TheNVPTXTarget64, createNVPTXMCInstrInfo);<br>
+<br>
+ // Register the MC register info.<br>
+ TargetRegistry::RegisterMCRegInfo(TheNVPTXTarget32,<br>
+ createNVPTXMCRegisterInfo);<br>
+ TargetRegistry::RegisterMCRegInfo(TheNVPTXTarget64,<br>
+ createNVPTXMCRegisterInfo);<br>
+<br>
+ // Register the MC subtarget info.<br>
+ TargetRegistry::RegisterMCSubtargetInfo(TheNVPTXTarget32,<br>
+ createNVPTXMCSubtargetInfo);<br>
+ TargetRegistry::RegisterMCSubtargetInfo(TheNVPTXTarget64,<br>
+ createNVPTXMCSubtargetInfo);<br>
+<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.h Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,36 @@<br>
+//===-- NVPTXMCTargetDesc.h - NVPTX Target Descriptions ---------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file provides NVPTX specific target descriptions.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef NVPTXMCTARGETDESC_H<br>
+#define NVPTXMCTARGETDESC_H<br>
+<br>
+namespace llvm {<br>
+class Target;<br>
+<br>
+extern Target TheNVPTXTarget32;<br>
+extern Target TheNVPTXTarget64;<br>
+<br>
+} // End llvm namespace<br>
+<br>
+// Defines symbolic names for PTX registers.<br>
+#define GET_REGINFO_ENUM<br>
+#include "NVPTXGenRegisterInfo.inc"<br>
+<br>
+// Defines symbolic names for the PTX instructions.<br>
+#define GET_INSTRINFO_ENUM<br>
+#include "NVPTXGenInstrInfo.inc"<br>
+<br>
+#define GET_SUBTARGETINFO_ENUM<br>
+#include "NVPTXGenSubtargetInfo.inc"<br>
+<br>
+#endif<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/Makefile?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/Makefile?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/Makefile (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/Makefile Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,23 @@<br>
+##===- lib/Target/NVPTX/Makefile ---------------------------*- Makefile -*-===##<br>
+#<br>
+# The LLVM Compiler Infrastructure<br>
+#<br>
+# This file is distributed under the University of Illinois Open Source<br>
+# License. See LICENSE.TXT for details.<br>
+#<br>
+##===----------------------------------------------------------------------===##<br>
+<br>
+LEVEL = ../../..<br>
+LIBRARYNAME = LLVMNVPTXCodeGen<br>
+TARGET = NVPTX<br>
+<br>
+# Make sure that tblgen is run, first thing.<br>
+BUILT_SOURCES = NVPTXGenAsmWriter.inc \<br>
+ NVPTXGenDAGISel.inc \<br>
+ NVPTXGenInstrInfo.inc \<br>
+ NVPTXGenRegisterInfo.inc \<br>
+ NVPTXGenSubtargetInfo.inc<br>
+<br>
+DIRS = InstPrinter TargetInfo MCTargetDesc<br>
+<br>
+include $(LEVEL)/Makefile.common<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/ManagedStringPool.h Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,49 @@<br>
+//===-- ManagedStringPool.h - Managed String Pool ---------------*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// The strings allocated from a managed string pool are owned by the string<br>
+// pool and will be deleted together with the managed string pool.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+<br>
+#ifndef LLVM_SUPPORT_MANAGED_STRING_H<br>
+#define LLVM_SUPPORT_MANAGED_STRING_H<br>
+<br>
+#include "llvm/ADT/SmallVector.h"<br>
+#include <string><br>
+<br>
+namespace llvm {<br>
+<br>
+/// ManagedStringPool - The strings allocated from a managed string pool are<br>
+/// owned by the string pool and will be deleted together with the managed<br>
+/// string pool.<br>
+class ManagedStringPool {<br>
+ SmallVector<std::string *, 8> Pool;<br>
+<br>
+public:<br>
+ ManagedStringPool() {}<br>
+ ~ManagedStringPool() {<br>
+ SmallVector<std::string *, 8>::iterator Current = Pool.begin();<br>
+ while (Current != Pool.end()) {<br>
+ delete *Current;<br>
+ Current++;<br>
+ }<br>
+ }<br>
+<br>
+ std::string *getManagedString(const char *S) {<br>
+ std::string *Str = new std::string(S);<br>
+ Pool.push_back(Str);<br>
+ return Str;<br>
+ }<br>
+};<br>
+<br>
+}<br>
+<br>
+#endif<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/NVPTX.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.h?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.h?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTX.h (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTX.h Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,137 @@<br>
+//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains the entry points for global functions defined in<br>
+// the LLVM NVPTX back-end.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef LLVM_TARGET_NVPTX_H<br>
+#define LLVM_TARGET_NVPTX_H<br>
+<br>
+#include <cassert><br>
+#include <iosfwd><br>
+#include "llvm/Value.h"<br>
+#include "llvm/Module.h"<br>
+#include "llvm/Support/ErrorHandling.h"<br>
+#include "llvm/Target/TargetMachine.h"<br>
+#include "MCTargetDesc/NVPTXBaseInfo.h"<br>
+<br>
+namespace llvm {<br>
+class NVPTXTargetMachine;<br>
+class FunctionPass;<br>
+class formatted_raw_ostream;<br>
+<br>
+namespace NVPTXCC {<br>
+enum CondCodes {<br>
+ EQ,<br>
+ NE,<br>
+ LT,<br>
+ LE,<br>
+ GT,<br>
+ GE<br>
+};<br>
+}<br>
+<br>
+inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {<br>
+ switch (CC) {<br>
+ default: assert(0 && "Unknown condition code");<br>
+ case NVPTXCC::NE: return "ne";<br>
+ case NVPTXCC::EQ: return "eq";<br>
+ case NVPTXCC::LT: return "lt";<br>
+ case NVPTXCC::LE: return "le";<br>
+ case NVPTXCC::GT: return "gt";<br>
+ case NVPTXCC::GE: return "ge";<br>
+ }<br>
+}<br>
+<br>
+FunctionPass *createNVPTXISelDag(NVPTXTargetMachine &TM,<br>
+ llvm::CodeGenOpt::Level OptLevel);<br>
+FunctionPass *createVectorElementizePass(NVPTXTargetMachine &);<br>
+FunctionPass *createLowerStructArgsPass(NVPTXTargetMachine &);<br>
+FunctionPass *createNVPTXReMatPass(NVPTXTargetMachine &);<br>
+FunctionPass *createNVPTXReMatBlockPass(NVPTXTargetMachine &);<br>
+<br>
+bool isImageOrSamplerVal(const Value *, const Module *);<br>
+<br>
+extern Target TheNVPTXTarget32;<br>
+extern Target TheNVPTXTarget64;<br>
+<br>
+namespace NVPTX<br>
+{<br>
+enum DrvInterface {<br>
+ NVCL,<br>
+ CUDA,<br>
+ TEST<br>
+};<br>
+<br>
+// A field inside TSFlags needs a shift and a mask. The usage is<br>
+// always as follows :<br>
+// ((TSFlags & fieldMask) >> fieldShift)<br>
+// The enum keeps the mask, the shift, and all valid values of the<br>
+// field in one place.<br>
+enum VecInstType {<br>
+ VecInstTypeShift = 0,<br>
+ VecInstTypeMask = 0xF,<br>
+<br>
+ VecNOP = 0,<br>
+ VecLoad = 1,<br>
+ VecStore = 2,<br>
+ VecBuild = 3,<br>
+ VecShuffle = 4,<br>
+ VecExtract = 5,<br>
+ VecInsert = 6,<br>
+ VecDest = 7,<br>
+ VecOther = 15<br>
+};<br>
+<br>
+enum SimpleMove {<br>
+ SimpleMoveMask = 0x10,<br>
+ SimpleMoveShift = 4<br>
+};<br>
+enum LoadStore {<br>
+ isLoadMask = 0x20,<br>
+ isLoadShift = 5,<br>
+ isStoreMask = 0x40,<br>
+ isStoreShift = 6<br>
+};<br>
+<br>
+namespace PTXLdStInstCode {<br>
+enum AddressSpace{<br>
+ GENERIC = 0,<br>
+ GLOBAL = 1,<br>
+ CONSTANT = 2,<br>
+ SHARED = 3,<br>
+ PARAM = 4,<br>
+ LOCAL = 5<br>
+};<br>
+enum FromType {<br>
+ Unsigned = 0,<br>
+ Signed,<br>
+ Float<br>
+};<br>
+enum VecType {<br>
+ Scalar = 1,<br>
+ V2 = 2,<br>
+ V4 = 4<br>
+};<br>
+}<br>
+}<br>
+} // end namespace llvm;<br>
+<br>
+// Defines symbolic names for NVPTX registers. This defines a mapping from<br>
+// register name to register number.<br>
+#define GET_REGINFO_ENUM<br>
+#include "NVPTXGenRegisterInfo.inc"<br>
+<br>
+// Defines symbolic names for the NVPTX instructions.<br>
+#define GET_INSTRINFO_ENUM<br>
+#include "NVPTXGenInstrInfo.inc"<br>
+<br>
+#endif<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/NVPTX.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.td?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTX.td?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTX.td (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTX.td Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,44 @@<br>
+//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+// This is the top level entry point for the NVPTX target.<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Target-independent interfaces<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+include "llvm/Target/Target.td"<br>
+<br>
+include "NVPTXRegisterInfo.td"<br>
+include "NVPTXInstrInfo.td"<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Subtarget Features.<br>
+// - We use the SM version number instead of explicit feature table.<br>
+// - Need at least one feature to avoid generating zero sized array by<br>
+// TableGen in NVPTXGenSubtarget.inc.<br>
+//===----------------------------------------------------------------------===//<br>
+def FeatureDummy : SubtargetFeature<"dummy", "dummy", "true", "">;<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// NVPTX supported processors.<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+class Proc<string Name, list<SubtargetFeature> Features><br>
+ : Processor<Name, NoItineraries, Features>;<br>
+<br>
+def : Proc<"sm_10", [FeatureDummy]>;<br>
+<br>
+<br>
+def NVPTXInstrInfo : InstrInfo {<br>
+}<br>
+<br>
+def NVPTX : Target {<br>
+ let InstructionSet = NVPTXInstrInfo;<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,48 @@<br>
+//===-- AllocaHoisting.cpp - Hosist allocas to the entry block --*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// Hoist the alloca instructions in the non-entry blocks to the entry blocks.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "llvm/Function.h"<br>
+#include "llvm/Instructions.h"<br>
+#include "llvm/Constants.h"<br>
+#include "NVPTXAllocaHoisting.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+bool NVPTXAllocaHoisting::runOnFunction(Function &function) {<br>
+ bool functionModified = false;<br>
+ Function::iterator I = function.begin();<br>
+ TerminatorInst *firstTerminatorInst = (I++)->getTerminator();<br>
+<br>
+ for (Function::iterator E = function.end(); I != E; ++I) {<br>
+ for (BasicBlock::iterator BI = I->begin(), BE = I->end(); BI != BE;) {<br>
+ AllocaInst *allocaInst = dyn_cast<AllocaInst>(BI++);<br>
+ if (allocaInst && isa<ConstantInt>(allocaInst->getArraySize())) {<br>
+ allocaInst->moveBefore(firstTerminatorInst);<br>
+ functionModified = true;<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ return functionModified;<br>
+}<br>
+<br>
+char NVPTXAllocaHoisting::ID = 1;<br>
+RegisterPass<NVPTXAllocaHoisting> X("alloca-hoisting",<br>
+ "Hoisting alloca instructsion in non-entry "<br>
+ "blocks to the entry block");<br>
+<br>
+FunctionPass *createAllocaHoisting() {<br>
+ return new NVPTXAllocaHoisting();<br>
+}<br>
+<br>
+} // end namespace llvm<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXAllocaHoisting.h Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,49 @@<br>
+//===-- AllocaHoisting.h - Hosist allocas to the entry block ----*- C++ -*-===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// Hoist the alloca instructions in the non-entry blocks to the entry blocks.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef NVPTX_ALLOCA_HOISTING_H_<br>
+#define NVPTX_ALLOCA_HOISTING_H_<br>
+<br>
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"<br>
+#include "llvm/Pass.h"<br>
+#include "llvm/Target/TargetData.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+class FunctionPass;<br>
+class Function;<br>
+<br>
+// Hoisting the alloca instructions in the non-entry blocks to the entry<br>
+// block.<br>
+class NVPTXAllocaHoisting : public FunctionPass {<br>
+public:<br>
+ static char ID; // Pass ID<br>
+ NVPTXAllocaHoisting() : FunctionPass(ID) {}<br>
+<br>
+ void getAnalysisUsage(AnalysisUsage &AU) const {<br>
+ AU.addRequired<TargetData>();<br>
+ AU.addPreserved<MachineFunctionAnalysis>();<br>
+ }<br>
+<br>
+ virtual const char *getPassName() const {<br>
+ return "NVPTX specific alloca hoisting";<br>
+ }<br>
+<br>
+ virtual bool runOnFunction(Function &function);<br>
+};<br>
+<br>
+extern FunctionPass *createAllocaHoisting();<br>
+<br>
+} // end namespace llvm<br>
+<br>
+#endif // NVPTX_ALLOCA_HOISTING_H_<br>
<br>
Added: llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp?rev=156196&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp?rev=156196&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp (added)<br>
+++ llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp Fri May 4 15:18:50 2012<br>
@@ -0,0 +1,2068 @@<br>
+//===-- NVPTXAsmPrinter.cpp - NVPTX LLVM assembly writer ------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This file contains a printer that converts from our internal representation<br>
+// of machine-dependent LLVM code to NVPTX assembly language.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "NVPTX.h"<br>
+#include "NVPTXInstrInfo.h"<br>
+#include "NVPTXTargetMachine.h"<br>
+#include "NVPTXRegisterInfo.h"<br>
+#include "NVPTXAsmPrinter.h"<br>
+#include "MCTargetDesc/NVPTXMCAsmInfo.h"<br>
+#include "NVPTXNumRegisters.h"<br>
+#include "../lib/CodeGen/AsmPrinter/DwarfDebug.h"<br>
+#include "llvm/ADT/StringExtras.h"<br>
+#include "llvm/GlobalVariable.h"<br>
+#include "llvm/Function.h"<br>
+#include "llvm/Module.h"<br>
+#include "llvm/CodeGen/Analysis.h"<br>
+#include "llvm/CodeGen/MachineRegisterInfo.h"<br>
+#include "llvm/CodeGen/MachineFrameInfo.h"<br>
+#include "llvm/CodeGen/MachineModuleInfo.h"<br>
+#include "llvm/MC/MCStreamer.h"<br>
+#include "llvm/MC/MCSymbol.h"<br>
+#include "llvm/Target/Mangler.h"<br>
+#include "llvm/Target/TargetLoweringObjectFile.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
+#include "llvm/Support/ErrorHandling.h"<br>
+#include "llvm/Support/FormattedStream.h"<br>
+#include "llvm/DerivedTypes.h"<br>
+#include "NVPTXUtilities.h"<br>
+#include "llvm/Support/TimeValue.h"<br>
+#include <sstream><br>
+#include "llvm/Support/CommandLine.h"<br>
+#include "llvm/Analysis/DebugInfo.h"<br>
+#include "llvm/Analysis/ConstantFolding.h"<br>
+#include "llvm/Support/Path.h"<br>
+#include "llvm/Assembly/Writer.h"<br>
+#include "cl_common_defines.h"<br>
+<br>
+<br>
+using namespace llvm;<br>
+<br>
+<br>
+#include "NVPTXGenAsmWriter.inc"<br>
+<br>
+bool RegAllocNilUsed = true;<br>
+<br>
+#define DEPOTNAME "__local_depot"<br>
+<br>
+static cl::opt<bool><br>
+EmitLineNumbers("nvptx-emit-line-numbers",<br>
+ cl::desc("NVPTX Specific: Emit Line numbers even without -G"),<br>
+ cl::init(true));<br>
+<br>
+namespace llvm {<br>
+bool InterleaveSrcInPtx = false;<br>
+}<br>
+<br>
+static cl::opt<bool, true>InterleaveSrc("nvptx-emit-src",<br>
+ cl::ZeroOrMore,<br>
+ cl::desc("NVPTX Specific: Emit source line in ptx file"),<br>
+ cl::location(llvm::InterleaveSrcInPtx));<br>
+<br>
+<br>
+<br>
+<br>
+// @TODO: This is a copy from AsmPrinter.cpp. The function is static, so we<br>
+// cannot just link to the existing version.<br>
+/// LowerConstant - Lower the specified LLVM Constant to an MCExpr.<br>
+///<br>
+using namespace nvptx;<br>
+const MCExpr *nvptx::LowerConstant(const Constant *CV, AsmPrinter &AP) {<br>
+ MCContext &Ctx = AP.OutContext;<br>
+<br>
+ if (CV->isNullValue() || isa<UndefValue>(CV))<br>
+ return MCConstantExpr::Create(0, Ctx);<br>
+<br>
+ if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV))<br>
+ return MCConstantExpr::Create(CI->getZExtValue(), Ctx);<br>
+<br>
+ if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV))<br>
+ return MCSymbolRefExpr::Create(AP.Mang->getSymbol(GV), Ctx);<br>
+<br>
+ if (const BlockAddress *BA = dyn_cast<BlockAddress>(CV))<br>
+ return MCSymbolRefExpr::Create(AP.GetBlockAddressSymbol(BA), Ctx);<br>
+<br>
+ const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV);<br>
+ if (CE == 0)<br>
+ llvm_unreachable("Unknown constant value to lower!");<br>
+<br>
+<br>
+ switch (CE->getOpcode()) {<br>
+ default:<br>
+ // If the code isn't optimized, there may be outstanding folding<br>
+ // opportunities. Attempt to fold the expression using TargetData as a<br>
+ // last resort before giving up.<br>
+ if (Constant *C =<br>
+ ConstantFoldConstantExpression(CE, AP.TM.getTargetData()))<br>
+ if (C != CE)<br>
+ return LowerConstant(C, AP);<br>
+<br>
+ // Otherwise report the problem to the user.<br>
+ {<br>
+ std::string S;<br>
+ raw_string_ostream OS(S);<br>
+ OS << "Unsupported expression in static initializer: ";<br>
+ WriteAsOperand(OS, CE, /*PrintType=*/false,<br>
+ !AP.MF ? 0 : AP.MF->getFunction()->getParent());<br>
+ report_fatal_error(OS.str());<br>
+ }<br>
+ case Instruction::GetElementPtr: {<br>
+ const TargetData &TD = *AP.TM.getTargetData();<br>
+ // Generate a symbolic expression for the byte address<br>
+ const Constant *PtrVal = CE->getOperand(0);<br>
+ SmallVector<Value*, 8> IdxVec(CE->op_begin()+1, CE->op_end());<br>
+ int64_t Offset = TD.getIndexedOffset(PtrVal->getType(), IdxVec);<br>
+<br>
+ const MCExpr *Base = LowerConstant(CE->getOperand(0), AP);<br>
+ if (Offset == 0)<br>
+ return Base;<br>
+<br>
+ // Truncate/sext the offset to the pointer size.<br>
+ if (TD.getPointerSizeInBits() != 64) {<br>
+ int SExtAmount = 64-TD.getPointerSizeInBits();<br>
+ Offset = (Offset << SExtAmount) >> SExtAmount;<br>
+ }<br>
+<br>
+ return MCBinaryExpr::CreateAdd(Base, MCConstantExpr::Create(Offset, Ctx),<br>
+ Ctx);<br>
+ }<br>
+<br>
+ case Instruction::Trunc:<br>
+ // We emit the value and depend on the assembler to truncate the generated<br>
+ // expression properly. This is important for differences between<br>
+ // blockaddress labels. Since the two labels are in the same function, it<br>
+ // is reasonable to treat their delta as a 32-bit value.<br>
+ // FALL THROUGH.<br>
+ case Instruction::BitCast:<br>
+ return LowerConstant(CE->getOperand(0), AP);<br>
+<br>
+ case Instruction::IntToPtr: {<br>
+ const TargetData &TD = *AP.TM.getTargetData();<br>
+ // Handle casts to pointers by changing them into casts to the appropriate<br>
+ // integer type. This promotes constant folding and simplifies this code.<br>
+ Constant *Op = CE->getOperand(0);<br>
+ Op = ConstantExpr::getIntegerCast(Op, TD.getIntPtrType(CV->getContext()),<br>
+ false/*ZExt*/);<br>
+ return LowerConstant(Op, AP);<br>
+ }<br>
+<br>
+ case Instruction::PtrToInt: {<br>
+ const TargetData &TD = *AP.TM.getTargetData();<br>
+ // Support only foldable casts to/from pointers that can be eliminated by<br>
+ // changing the pointer to the appropriately sized integer type.<br>
+ Constant *Op = CE->getOperand(0);<br>
+ Type *Ty = CE->getType();<br>
+<br>
+ const MCExpr *OpExpr = LowerConstant(Op, AP);<br>
+<br>
+ // We can emit the pointer value into this slot if the slot is an<br>
+ // integer slot equal to the size of the pointer.<br>
+ if (TD.getTypeAllocSize(Ty) == TD.getTypeAllocSize(Op->getType()))<br>
+ return OpExpr;<br>
+<br>
+ // Otherwise the pointer is smaller than the resultant integer, mask off<br>
+ // the high bits so we are sure to get a proper truncation if the input is<br>
+ // a constant expr.<br>
+ unsigned InBits = TD.getTypeAllocSizeInBits(Op->getType());<br>
+ const MCExpr *MaskExpr = MCConstantExpr::Create(~0ULL >> (64-InBits), Ctx);<br>
+ return MCBinaryExpr::CreateAnd(OpExpr, MaskExpr, Ctx);<br>
+ }<br>
+<br>
+ // The MC library also has a right-shift operator, but it isn't consistently<br>
+ // signed or unsigned between different targets.<br>
+ case Instruction::Add:<br>
+ case Instruction::Sub:<br>
+ case Instruction::Mul:<br>
+ case Instruction::SDiv:<br>
+ case Instruction::SRem:<br>
+ case Instruction::Shl:<br>
+ case Instruction::And:<br>
+ case Instruction::Or:<br>
+ case Instruction::Xor: {<br>
+ const MCExpr *LHS = LowerConstant(CE->getOperand(0), AP);<br>
+ const MCExpr *RHS = LowerConstant(CE->getOperand(1), AP);<br>
+ switch (CE->getOpcode()) {<br>
+ default: llvm_unreachable("Unknown binary operator constant cast expr");<br>
+ case Instruction::Add: return MCBinaryExpr::CreateAdd(LHS, RHS, Ctx);<br>
+ case Instruction::Sub: return MCBinaryExpr::CreateSub(LHS, RHS, Ctx);<br>
+ case Instruction::Mul: return MCBinaryExpr::CreateMul(LHS, RHS, Ctx);<br>
+ case Instruction::SDiv: return MCBinaryExpr::CreateDiv(LHS, RHS, Ctx);<br>
+ case Instruction::SRem: return MCBinaryExpr::CreateMod(LHS, RHS, Ctx);<br>
+ case Instruction::Shl: return MCBinaryExpr::CreateShl(LHS, RHS, Ctx);<br>
+ case Instruction::And: return MCBinaryExpr::CreateAnd(LHS, RHS, Ctx);<br>
+ case Instruction::Or: return MCBinaryExpr::CreateOr (LHS, RHS, Ctx);<br>
+ case Instruction::Xor: return MCBinaryExpr::CreateXor(LHS, RHS, Ctx);<br>
+ }<br>
+ }<br>
+ }<br>
+}<br>
+<br>
+<br>
+void NVPTXAsmPrinter::emitLineNumberAsDotLoc(const MachineInstr &MI)<br>
+{<br>
+ if (!EmitLineNumbers)<br>
+ return;<br>
+ if (ignoreLoc(MI))<br>
+ return;<br>
+<br>
+ DebugLoc curLoc = MI.getDebugLoc();<br>
+<br>
+ if (prevDebugLoc.isUnknown() && curLoc.isUnknown())<br>
+ return;<br>
+<br>
+ if (prevDebugLoc == curLoc)<br>
+ return;<br>
+<br>
+ prevDebugLoc = curLoc;<br>
+<br>
+ if (curLoc.isUnknown())<br>
+ return;<br>
+<br>
+<br>
+ const MachineFunction *MF = MI.getParent()->getParent();<br>
+ //const TargetMachine &TM = MF->getTarget();<br>
+<br>
+ const LLVMContext &ctx = MF->getFunction()->getContext();<br>
+ DIScope Scope(curLoc.getSc...<br><br>[Message clipped] </blockquote></div><br></div>