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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks very much, Jakob! Here is a revised and greatly simplified patch, as per your suggestion.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">This patch marks the X86 floating point stack registers ST0-ST7 as reserved in order to avoid assertion failures in the register scavenger. The assertion failures
were “Bad machine code: Using an undefined physical register” and “Bad machine code: MBB exits via unconditional fall-through but its successor differs from its CFG successor!”.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Please review.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Preston<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Jakob Stoklund Olesen [mailto:stoklund@2pi.dk]
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<b>Sent:</b> Monday, April 30, 2012 8:14 PM<br>
<b>To:</b> Gurd, Preston<br>
<b>Cc:</b> llvm-commits@cs.uiuc.edu<br>
<b>Subject:</b> Re: [llvm][PATCH][Review Requested]<o:p></o:p></span></p>
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<p class="MsoNormal">On Apr 30, 2012, at 3:09 PM, "Gurd, Preston" <<a href="mailto:preston.gurd@intel.com">preston.gurd@intel.com</a>> wrote:<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">The problem which we are trying to solve is that when we enable register scavenging for X86, the register scavenger sees X87 stack registers (which are unallocatable)
and then triggers an assertion failure saying “Using an undefined physical register”. We want to ignore unallocatable registers in the registers as per the patch that you committed last July (r136541). That patch was reverted because it apparently negatively
affected ARM. We want to ignore unallocatable registers for X86 so that we can use the register scavenger which in turn we need for post RA scheduling for Intel Atom.</span><o:p></o:p></p>
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<p class="MsoNormal">Actually, I think this is exposing a real problem. The ST registers can't be treated as normal unallocatable registers because they are really stack positions. This means that the PostRA scheduler can't properly reason about their dependencies
either.<o:p></o:p></p>
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<p class="MsoNormal">I would prefer if the ST registers were reserved. Then the scheduler would know to leave them alone.<o:p></o:p></p>
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<p class="MsoNormal">The ST registers are also used before register allocation to pass fixed stack parameters to and from inline assembly. Previously, reserving the ST registers broke some tests in inline-asm-fpstack.ll because of missing dead flags, but that
seems to have been fixed.<o:p></o:p></p>
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<p class="MsoNormal">/jakob<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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