No reason not to. I just didn't scroll down far enough in the file. I'll fix it tonight.<br><br><div class="gmail_quote">On Mon, Apr 30, 2012 at 9:27 AM, Roman Divacky <span dir="ltr"><<a href="mailto:rdivacky@freebsd.org" target="_blank">rdivacky@freebsd.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Any reason to not enable this on AMD too? ie. on bdver1/bdver2<br>
<div class="HOEnZb"><div class="h5"><br>
On Thu, Apr 26, 2012 at 06:40:15AM -0000, Craig Topper wrote:<br>
> Author: ctopper<br>
> Date: Thu Apr 26 01:40:15 2012<br>
> New Revision: 155618<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=155618&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=155618&view=rev</a><br>
> Log:<br>
> Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.<br>
><br>
> Modified:<br>
>     llvm/trunk/lib/Target/X86/X86.td<br>
>     llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=155618&r1=155617&r2=155618&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=155618&r1=155617&r2=155618&view=diff</a><br>

> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86.td Thu Apr 26 01:40:15 2012<br>
> @@ -173,21 +173,19 @@<br>
>  // Sandy Bridge<br>
>  // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,<br>
>  // rather than a superset.<br>
> -// FIXME: Disabling AVX for now since it's not ready.<br>
> -def : Proc<"corei7-avx",      [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,<br>
> +def : Proc<"corei7-avx",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,<br>
>                                 FeatureAES, FeatureCLMUL]>;<br>
>  // Ivy Bridge<br>
> -def : Proc<"core-avx-i",      [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,<br>
> +def : Proc<"core-avx-i",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,<br>
>                                 FeatureAES, FeatureCLMUL,<br>
>                                 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;<br>
><br>
>  // Haswell<br>
> -// FIXME: Disabling AVX/AVX2/FMA3 for now since it's not ready.<br>
> -def : Proc<"core-avx2",       [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,<br>
> +def : Proc<"core-avx2",       [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT,<br>
>                                 FeatureAES, FeatureCLMUL, FeatureRDRAND,<br>
>                                 FeatureF16C, FeatureFSGSBase,<br>
>                                 FeatureMOVBE, FeatureLZCNT, FeatureBMI,<br>
> -                               FeatureBMI2]>;<br>
> +                               FeatureBMI2, FeatureFMA3]>;<br>
><br>
>  def : Proc<"k6",              [FeatureMMX]>;<br>
>  def : Proc<"k6-2",            [Feature3DNow]>;<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=155618&r1=155617&r2=155618&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=155618&r1=155617&r2=155618&view=diff</a><br>

> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Apr 26 01:40:15 2012<br>
> @@ -196,8 +196,7 @@<br>
>    if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}<br>
>    if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}<br>
>    if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}<br>
> -  // FIXME: AVX codegen support is not ready.<br>
> -  //if ((ECX >> 28) & 1) { X86SSELevel = AVX;  ToggleFeature(X86::FeatureAVX); }<br>
> +  if ((ECX >> 28) & 1) { X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX); }<br>
><br>
>    bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;<br>
>    bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;<br>
> @@ -299,11 +298,10 @@<br>
>          HasBMI = true;<br>
>          ToggleFeature(X86::FeatureBMI);<br>
>        }<br>
> -      // FIXME: AVX2 codegen support is not ready.<br>
> -      //if ((EBX >> 5) & 0x1) {<br>
> -      //  X86SSELevel = AVX2;<br>
> -      //  ToggleFeature(X86::FeatureAVX2);<br>
> -      //}<br>
> +      if ((EBX >> 5) & 0x1) {<br>
> +        X86SSELevel = AVX2;<br>
> +        ToggleFeature(X86::FeatureAVX2);<br>
> +      }<br>
>        if ((EBX >> 8) & 0x1) {<br>
>          HasBMI2 = true;<br>
>          ToggleFeature(X86::FeatureBMI2);<br>
><br>
><br>
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</div></div></blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>