<div class="gmail_extra"><div class="gmail_quote">On Tue, Apr 24, 2012 at 10:56 AM, Andrew Trick <span dir="ltr"><<a href="mailto:atrick@apple.com" target="_blank">atrick@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: atrick<br>
Date: Tue Apr 24 12:56:43 2012<br>
New Revision: 155456<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=155456&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=155456&view=rev</a><br>
Log:<br>
misched: DAG builder support for tracking register pressure within the current scheduling region.<br>
<br>
The DAG builder is a convenient place to do it. Hopefully this is more<br>
efficient than a separate traversal over the same region.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MachineScheduler.h<br>
llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h<br>
llvm/trunk/lib/CodeGen/MachineScheduler.cpp<br>
llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineScheduler.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=155456&r1=155455&r2=155456&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=155456&r1=155455&r2=155456&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineScheduler.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineScheduler.h Tue Apr 24 12:56:43 2012<br>
@@ -27,6 +27,7 @@<br>
#ifndef MACHINESCHEDULER_H<br>
#define MACHINESCHEDULER_H<br>
<br>
+#include "RegisterClassInfo.h"<br></blockquote><div><br></div><div>This doesn't seem right Andy... we're including a header from lib/CodeGen into a file in include/llvm/CodeGen. The latter files get installed, the former don't... It's breaking installed library usage (and it's breaking our layering checked builds).</div>
<div><br></div><div>Thoughts? Should this include go away? Should RegisterClassInfo.h move?</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
#include "llvm/CodeGen/MachinePassRegistry.h"<br>
<br>
namespace llvm {<br>
@@ -47,7 +48,10 @@<br>
AliasAnalysis *AA;<br>
LiveIntervals *LIS;<br>
<br>
- MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}<br>
+ RegisterClassInfo RegClassInfo;<br>
+<br>
+ MachineSchedContext():<br>
+ MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}<br>
};<br>
<br>
/// MachineSchedRegistry provides a selection of available machine instruction<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h?rev=155456&r1=155455&r2=155456&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h?rev=155456&r1=155455&r2=155456&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAGInstrs.h Tue Apr 24 12:56:43 2012<br>
@@ -28,6 +28,7 @@<br>
class MachineLoopInfo;<br>
class MachineDominatorTree;<br>
class LiveIntervals;<br>
+ class RegPressureTracker;<br>
<br>
/// LoopDependencies - This class analyzes loop-oriented register<br>
/// dependencies, which are used to guide scheduling decisions.<br>
@@ -275,7 +276,7 @@<br>
<br>
/// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are<br>
/// input.<br>
- void buildSchedGraph(AliasAnalysis *AA);<br>
+ void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0);<br>
<br>
/// addSchedBarrierDeps - Add dependencies from instructions in the current<br>
/// list of instructions being scheduled to scheduling barrier. We want to<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=155456&r1=155455&r2=155456&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=155456&r1=155455&r2=155456&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Apr 24 12:56:43 2012<br>
@@ -14,6 +14,7 @@<br>
<br>
#define DEBUG_TYPE "misched"<br>
<br>
+#include "RegisterPressure.h"<br>
#include "llvm/CodeGen/LiveIntervalAnalysis.h"<br>
#include "llvm/CodeGen/MachineScheduler.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
@@ -149,6 +150,8 @@<br>
LIS = &getAnalysis<LiveIntervals>();<br>
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();<br>
<br>
+ RegClassInfo.runOnMachineFunction(*MF);<br>
+<br>
// Select the scheduler, or set the default.<br>
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;<br>
if (Ctor == useDefaultMachineSched) {<br>
@@ -163,6 +166,9 @@<br>
OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));<br>
<br>
// Visit all machine basic blocks.<br>
+ //<br>
+ // TODO: Visit blocks in global postorder or postorder within the bottom-up<br>
+ // loop tree. Then we can optionally compute global RegPressure.<br>
for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();<br>
MBB != MBBEnd; ++MBB) {<br>
<br>
@@ -181,6 +187,7 @@<br>
unsigned RemainingCount = MBB->size();<br>
for(MachineBasicBlock::iterator RegionEnd = MBB->end();<br>
RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {<br>
+<br>
// Avoid decrementing RegionEnd for blocks with no terminator.<br>
if (RegionEnd != MBB->end()<br>
|| TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {<br>
@@ -279,8 +286,13 @@<br>
/// machine instructions while updating LiveIntervals.<br>
class ScheduleDAGMI : public ScheduleDAGInstrs {<br>
AliasAnalysis *AA;<br>
+ RegisterClassInfo *RegClassInfo;<br>
MachineSchedStrategy *SchedImpl;<br>
<br>
+ // Register pressure in this region computed by buildSchedGraph.<br>
+ IntervalPressure RegPressure;<br>
+ RegPressureTracker RPTracker;<br>
+<br>
/// The top of the unscheduled zone.<br>
MachineBasicBlock::iterator CurrentTop;<br>
<br>
@@ -293,7 +305,8 @@<br>
public:<br>
ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):<br>
ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),<br>
- AA(C->AA), SchedImpl(S), CurrentTop(), CurrentBottom(),<br>
+ AA(C->AA), RegClassInfo(&C->RegClassInfo), SchedImpl(S),<br>
+ RPTracker(RegPressure), CurrentTop(), CurrentBottom(),<br>
NumInstrsScheduled(0) {}<br>
<br>
~ScheduleDAGMI() {<br>
@@ -303,7 +316,16 @@<br>
MachineBasicBlock::iterator top() const { return CurrentTop; }<br>
MachineBasicBlock::iterator bottom() const { return CurrentBottom; }<br>
<br>
- /// Implement ScheduleDAGInstrs interface.<br>
+ /// Implement the ScheduleDAGInstrs interface for handling the next scheduling<br>
+ /// region. This covers all instructions in a block, while schedule() may only<br>
+ /// cover a subset.<br>
+ void enterRegion(MachineBasicBlock *bb,<br>
+ MachineBasicBlock::iterator begin,<br>
+ MachineBasicBlock::iterator end,<br>
+ unsigned endcount);<br>
+<br>
+ /// Implement ScheduleDAGInstrs interface for scheduling a sequence of<br>
+ /// reorderable instructions.<br>
void schedule();<br>
<br>
protected:<br>
@@ -392,10 +414,32 @@<br>
return true;<br>
}<br>
<br>
+/// enterRegion - Called back from MachineScheduler::runOnMachineFunction after<br>
+/// crossing a scheduling boundary. [begin, end) includes all instructions in<br>
+/// the region, including the boundary itself and single-instruction regions<br>
+/// that don't get scheduled.<br>
+void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,<br>
+ MachineBasicBlock::iterator begin,<br>
+ MachineBasicBlock::iterator end,<br>
+ unsigned endcount)<br>
+{<br>
+ ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount);<br>
+ // Setup the register pressure tracker to begin tracking at the end of this<br>
+ // region.<br>
+ RPTracker.init(&MF, RegClassInfo, LIS, BB, end);<br>
+}<br>
+<br>
/// schedule - Called back from MachineScheduler::runOnMachineFunction<br>
-/// after setting up the current scheduling region.<br>
+/// after setting up the current scheduling region. [RegionBegin, RegionEnd)<br>
+/// only includes instructions that have DAG nodes, not scheduling boundaries.<br>
void ScheduleDAGMI::schedule() {<br>
- buildSchedGraph(AA);<br>
+ while(RPTracker.getPos() != RegionEnd) {<br>
+ bool Moved = RPTracker.recede();<br>
+ assert(Moved && "Regpressure tracker cannot find RegionEnd"); (void)Moved;<br>
+ }<br>
+<br>
+ // Build the DAG.<br>
+ buildSchedGraph(AA, &RPTracker);<br>
<br>
DEBUG(dbgs() << "********** MI Scheduling **********\n");<br>
DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)<br>
<br>
Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=155456&r1=155455&r2=155456&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=155456&r1=155455&r2=155456&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Apr 24 12:56:43 2012<br>
@@ -13,6 +13,7 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
#define DEBUG_TYPE "sched-instrs"<br>
+#include "RegisterPressure.h"<br>
#include "llvm/Operator.h"<br>
#include "llvm/Analysis/AliasAnalysis.h"<br>
#include "llvm/Analysis/ValueTracking.h"<br>
@@ -504,7 +505,11 @@<br>
}<br>
}<br>
<br>
-void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA) {<br>
+/// If RegPressure is non null, compute register pressure as a side effect. The<br>
+/// DAG builder is an efficient place to do it because it already visits<br>
+/// operands.<br>
+void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,<br>
+ RegPressureTracker *RPTracker) {<br>
// Create an SUnit for each real instruction.<br>
initSUnits();<br>
<br>
@@ -555,6 +560,10 @@<br>
PrevMI = MI;<br>
continue;<br>
}<br>
+ if (RPTracker) {<br>
+ RPTracker->recede();<br>
+ assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI");<br>
+ }<br>
<br>
assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() &&<br>
"Cannot schedule terminators or labels!");<br>
<br>
<br>
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</blockquote></div><br></div>