<div class="gmail_extra">Why do we need a pattern for 2f64? There's not a load version of that type. Also don't you need integer versions?<br><br><div class="gmail_quote">On Tue, Apr 24, 2012 at 4:07 AM, Nadav Rotem <span dir="ltr"><<a href="mailto:nadav.rotem@intel.com" target="_blank">nadav.rotem@intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: nadav<br>
Date: Tue Apr 24 06:07:03 2012<br>
New Revision: 155437<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=155437&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=155437&view=rev</a><br>
Log:<br>
AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions<br>
using the pattern (vbroadcast (i32load src)). In some cases, after we generate<br>
this pattern new users are added to the load node, which prevent the selection<br>
of the blend pattern. This commit provides fallback patterns which perform<br>
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=155437&r1=155436&r2=155437&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=155437&r1=155436&r2=155437&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Apr 24 06:07:03 2012<br>
@@ -7723,6 +7723,20 @@<br>
(VPBROADCASTQrm addr:$src)>;<br>
def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),<br>
(VPBROADCASTQYrm addr:$src)>;<br>
+<br>
+ // Provide fallback in case the load node that is used in the patterns above<br>
+ // is used by additional users, which prevents the pattern selection.<br>
+ let AddedComplexity = 20 in {<br>
+ def : Pat<(v4f32 (X86VBroadcast FR32:$src)),<br>
+ (VBROADCASTSSrr<br>
+ (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;<br>
+ def : Pat<(v8f32 (X86VBroadcast FR32:$src)),<br>
+ (VBROADCASTSSYrr<br>
+ (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;<br>
+ def : Pat<(v4f64 (X86VBroadcast FR64:$src)),<br>
+ (VBROADCASTSDrr<br>
+ (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;<br>
+ }<br>
}<br>
<br>
// AVX1 broadcast patterns<br>
@@ -7735,11 +7749,38 @@<br>
(VBROADCASTSSYrm addr:$src)>;<br>
def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),<br>
(VBROADCASTSDrm addr:$src)>;<br>
-<br>
def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),<br>
(VBROADCASTSSrm addr:$src)>;<br>
def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),<br>
(VBROADCASTSSrm addr:$src)>;<br>
+<br>
+ // Provide fallback in case the load node that is used in the patterns above<br>
+ // is used by additional users, which prevents the pattern selection.<br>
+ let AddedComplexity = 20 in {<br>
+ // 128bit broadcasts:<br>
+ def : Pat<(v2f64 (X86VBroadcast FR64:$src)),<br>
+ (VPSHUFDri<br>
+ (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0)>;<br>
+ def : Pat<(v4f32 (X86VBroadcast FR32:$src)),<br>
+ (VPSHUFDri<br>
+ (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;<br>
+ def : Pat<(v8f32 (X86VBroadcast FR32:$src)),<br>
+ (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),<br>
+ (VPSHUFDri<br>
+ (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),<br>
+ sub_xmm),<br>
+ (VPSHUFDri<br>
+ (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),<br>
+ 0), 1)>;<br>
+ def : Pat<(v4f64 (X86VBroadcast FR64:$src)),<br>
+ (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),<br>
+ (VPSHUFDri<br>
+ (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),<br>
+ sub_xmm),<br>
+ (VPSHUFDri<br>
+ (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),<br>
+ 0), 1)>;<br>
+ }<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll?rev=155437&r1=155436&r2=155437&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll?rev=155437&r1=155436&r2=155437&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx2-vbroadcast.ll Tue Apr 24 06:07:03 2012<br>
@@ -160,6 +160,15 @@<br>
ret <8 x i32> %g<br>
}<br>
<br>
+; CHECK: V113<br>
+; CHECK: vbroadcastss<br>
+; CHECK: ret<br>
+define <8 x float> @V113(<8 x float> %in) nounwind uwtable readnone ssp {<br>
+entry:<br>
+ %g = fadd <8 x float> %in, <float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000><br>
+ ret <8 x float> %g<br>
+}<br>
+<br>
; CHECK: _e2<br>
; CHECK: vbroadcastss<br>
; CHECK: ret<br>
@@ -179,9 +188,37 @@<br>
%vecinit1.i = insertelement <8 x i8> %vecinit0.i, i8 52, i32 1<br>
%vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 52, i32 2<br>
%vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 52, i32 3<br>
- %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 52, i32 3<br>
- %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 52, i32 3<br>
- %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 52, i32 3<br>
- %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 52, i32 3<br>
+ %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 52, i32 4<br>
+ %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 52, i32 5<br>
+ %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 52, i32 6<br>
+ %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 52, i32 7<br>
ret <8 x i8> %vecinit7.i<br>
}<br>
+<br>
+<br>
+define void @crash() nounwind alwaysinline {<br>
+WGLoopsEntry:<br>
+ br i1 undef, label %ret, label %footer329VF<br>
+<br>
+footer329VF:<br>
+ %A.0.inVF = fmul float undef, 6.553600e+04<br>
+ %B.0.in407VF = fmul <8 x float> undef, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04><br>
+ %A.0VF = fptosi float %A.0.inVF to i32<br>
+ %B.0408VF = fptosi <8 x float> %B.0.in407VF to <8 x i32><br>
+ %0 = and <8 x i32> %B.0408VF, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535><br>
+ %1 = and i32 %A.0VF, 65535<br>
+ %temp1098VF = insertelement <8 x i32> undef, i32 %1, i32 0<br>
+ %vector1099VF = shufflevector <8 x i32> %temp1098VF, <8 x i32> undef, <8 x i32> zeroinitializer<br>
+ br i1 undef, label %preload1201VF, label %footer349VF<br>
+<br>
+preload1201VF:<br>
+ br label %footer349VF<br>
+<br>
+footer349VF:<br>
+ %2 = mul nsw <8 x i32> undef, %0<br>
+ %3 = mul nsw <8 x i32> undef, %vector1099VF<br>
+ br label %footer329VF<br>
+<br>
+ret:<br>
+ ret void<br>
+}<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>
</div>