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<p class="MsoNormal">If possible, it would be appreciated if this patch could be reviewed in time for inclusion in the llvm 3.1 release. We would have proposed this patch sooner, were it not for the fact that we have only just discovered the problem.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This patch fixes a problem which arose when using the Post-RA scheduler on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information.
When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to
run the RegisterScavenging code in the BranchFolding pass.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList
pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The patch adds and invokes the new function maintainLiveInsDuringBranchFolding() instead of using the existing requiresRegisterScavenging() function because requiresRegisterScavenging() caused a lot of errors related to using unallocatable
registers in the prolog/epilog code. When we fixed the unallocated registers problem, then the test Codegen/X86/x86-64.asm was failing with an error message relating to an unallocated register on the test’s ret instruction.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Patch by Andy Zhang!<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">--<o:p></o:p></p>
<p class="MsoNormal">Preston Gurd <preston.gurd@intel.com><o:p></o:p></p>
<p class="MsoNormal"> Intel Waterloo<o:p></o:p></p>
<p class="MsoNormal"> SSG/DPD/ECDL/DMP<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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