This caused some warnings in release builds that I've tried to clean up in r154660.<br><br><div class="gmail_quote">On Thu, Apr 12, 2012 at 2:06 PM, Sirish Pande <span dir="ltr"><<a href="mailto:spande@codeaurora.org">spande@codeaurora.org</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: sirish<br>
Date: Thu Apr 12 16:06:38 2012<br>
New Revision: 154616<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=154616&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=154616&view=rev</a><br>
Log:<br>
HexagonPacketizer patch.<br>
<br>
Added:<br>
llvm/trunk/lib/Target/Hexagon/HexagonMCInst.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h<br>
llvm/trunk/lib/CodeGen/DFAPacketizer.cpp<br>
llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br>
llvm/trunk/lib/Target/Hexagon/Hexagon.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/DFAPacketizer.h Thu Apr 12 16:06:38 2012<br>
@@ -28,6 +28,7 @@<br>
<br>
#include "llvm/CodeGen/MachineBasicBlock.h"<br>
#include "llvm/ADT/DenseMap.h"<br>
+#include <map><br>
<br>
namespace llvm {<br>
<br>
@@ -36,7 +37,7 @@<br>
class MachineLoopInfo;<br>
class MachineDominatorTree;<br>
class InstrItineraryData;<br>
-class ScheduleDAGInstrs;<br>
+class DefaultVLIWScheduler;<br>
class SUnit;<br>
<br>
class DFAPacketizer {<br>
@@ -77,6 +78,8 @@<br>
// reserveResources - Reserve the resources occupied by a machine<br>
// instruction and change the current state to reflect that change.<br>
void reserveResources(llvm::MachineInstr *MI);<br>
+<br>
+ const InstrItineraryData *getInstrItins() const { return InstrItins; }<br>
};<br>
<br>
// VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The<br>
@@ -87,20 +90,21 @@<br>
// and machine resource is marked as taken. If any dependency is found, a target<br>
// API call is made to prune the dependence.<br>
class VLIWPacketizerList {<br>
+protected:<br>
const TargetMachine &TM;<br>
const MachineFunction &MF;<br>
const TargetInstrInfo *TII;<br>
<br>
- // Encapsulate data types not exposed to the target interface.<br>
- ScheduleDAGInstrs *SchedulerImpl;<br>
+ // The VLIW Scheduler.<br>
+ DefaultVLIWScheduler *VLIWScheduler;<br>
<br>
-protected:<br>
// Vector of instructions assigned to the current packet.<br>
std::vector<MachineInstr*> CurrentPacketMIs;<br>
// DFA resource tracker.<br>
DFAPacketizer *ResourceTracker;<br>
- // Scheduling units.<br>
- std::vector<SUnit> SUnits;<br>
+<br>
+ // Generate MI -> SU map.<br>
+ std::map<MachineInstr*, SUnit*> MIToSUnit;<br>
<br>
public:<br>
VLIWPacketizerList(<br>
@@ -118,17 +122,32 @@<br>
DFAPacketizer *getResourceTracker() {return ResourceTracker;}<br>
<br>
// addToPacket - Add MI to the current packet.<br>
- void addToPacket(MachineInstr *MI);<br>
+ virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {<br>
+ MachineBasicBlock::iterator MII = MI;<br>
+ CurrentPacketMIs.push_back(MI);<br>
+ ResourceTracker->reserveResources(MI);<br>
+ return MII;<br>
+ }<br>
<br>
// endPacket - End the current packet.<br>
- void endPacket(MachineBasicBlock *MBB, MachineInstr *I);<br>
+ void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);<br>
+<br>
+ // initPacketizerState - perform initialization before packetizing<br>
+ // an instruction. This function is supposed to be overrided by<br>
+ // the target dependent packetizer.<br>
+ virtual void initPacketizerState(void) { return; }<br>
<br>
// ignorePseudoInstruction - Ignore bundling of pseudo instructions.<br>
- bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB);<br>
+ virtual bool ignorePseudoInstruction(MachineInstr *I,<br>
+ MachineBasicBlock *MBB) {<br>
+ return false;<br>
+ }<br>
<br>
- // isSoloInstruction - return true if instruction I must end previous<br>
- // packet.<br>
- bool isSoloInstruction(MachineInstr *I);<br>
+ // isSoloInstruction - return true if instruction MI can not be packetized<br>
+ // with any other instruction, which means that MI itself is a packet.<br>
+ virtual bool isSoloInstruction(MachineInstr *MI) {<br>
+ return true;<br>
+ }<br>
<br>
// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ<br>
// together.<br>
@@ -141,6 +160,7 @@<br>
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {<br>
return false;<br>
}<br>
+<br>
};<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/DFAPacketizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DFAPacketizer.cpp?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/DFAPacketizer.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/DFAPacketizer.cpp Thu Apr 12 16:06:38 2012<br>
@@ -23,10 +23,10 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"<br>
#include "llvm/CodeGen/DFAPacketizer.h"<br>
#include "llvm/CodeGen/MachineInstr.h"<br>
#include "llvm/CodeGen/MachineInstrBundle.h"<br>
-#include "llvm/CodeGen/ScheduleDAGInstrs.h"<br>
#include "llvm/Target/TargetInstrInfo.h"<br>
#include "llvm/MC/MCInstrItineraries.h"<br>
using namespace llvm;<br>
@@ -100,17 +100,17 @@<br>
reserveResources(&MID);<br>
}<br>
<br>
-namespace {<br>
+namespace llvm {<br>
// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides<br>
// Schedule method to build the dependence graph.<br>
class DefaultVLIWScheduler : public ScheduleDAGInstrs {<br>
public:<br>
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,<br>
- MachineDominatorTree &MDT, bool IsPostRA);<br>
+ MachineDominatorTree &MDT, bool IsPostRA);<br>
// Schedule - Actual scheduling work.<br>
void schedule();<br>
};<br>
-} // end anonymous namespace<br>
+}<br>
<br>
DefaultVLIWScheduler::DefaultVLIWScheduler(<br>
MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,<br>
@@ -129,49 +129,25 @@<br>
bool IsPostRA) : TM(MF.getTarget()), MF(MF) {<br>
TII = TM.getInstrInfo();<br>
ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);<br>
- SchedulerImpl = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);<br>
+ VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);<br>
}<br>
<br>
// VLIWPacketizerList Dtor<br>
VLIWPacketizerList::~VLIWPacketizerList() {<br>
- delete SchedulerImpl;<br>
- delete ResourceTracker;<br>
-}<br>
-<br>
-// ignorePseudoInstruction - ignore pseudo instructions.<br>
-bool VLIWPacketizerList::ignorePseudoInstruction(MachineInstr *MI,<br>
- MachineBasicBlock *MBB) {<br>
- if (MI->isDebugValue())<br>
- return true;<br>
-<br>
- if (TII->isSchedulingBoundary(MI, MBB, MF))<br>
- return true;<br>
-<br>
- return false;<br>
-}<br>
-<br>
-// isSoloInstruction - return true if instruction I must end previous<br>
-// packet.<br>
-bool VLIWPacketizerList::isSoloInstruction(MachineInstr *I) {<br>
- if (I->isInlineAsm())<br>
- return true;<br>
-<br>
- return false;<br>
-}<br>
+ if (VLIWScheduler)<br>
+ delete VLIWScheduler;<br>
<br>
-// addToPacket - Add I to the current packet and reserve resource.<br>
-void VLIWPacketizerList::addToPacket(MachineInstr *MI) {<br>
- CurrentPacketMIs.push_back(MI);<br>
- ResourceTracker->reserveResources(MI);<br>
+ if (ResourceTracker)<br>
+ delete ResourceTracker;<br>
}<br>
<br>
// endPacket - End the current packet, bundle packet instructions and reset<br>
// DFA state.<br>
void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,<br>
- MachineInstr *I) {<br>
+ MachineInstr *MI) {<br>
if (CurrentPacketMIs.size() > 1) {<br>
MachineInstr *MIFirst = CurrentPacketMIs.front();<br>
- finalizeBundle(*MBB, MIFirst, I);<br>
+ finalizeBundle(*MBB, MIFirst, MI);<br>
}<br>
CurrentPacketMIs.clear();<br>
ResourceTracker->clearResources();<br>
@@ -181,31 +157,36 @@<br>
void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,<br>
MachineBasicBlock::iterator BeginItr,<br>
MachineBasicBlock::iterator EndItr) {<br>
- assert(MBB->end() == EndItr && "Bad EndIndex");<br>
-<br>
- SchedulerImpl->enterRegion(MBB, BeginItr, EndItr, MBB->size());<br>
-<br>
- // Build the DAG without reordering instructions.<br>
- SchedulerImpl->schedule();<br>
-<br>
- // Remember scheduling units.<br>
- SUnits = SchedulerImpl->SUnits;<br>
+ assert(VLIWScheduler && "VLIW Scheduler is not initialized!");<br>
+ VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());<br>
+ VLIWScheduler->schedule();<br>
+ VLIWScheduler->exitRegion();<br>
+<br>
+ // Generate MI -> SU map.<br>
+ //std::map <MachineInstr*, SUnit*> MIToSUnit;<br>
+ MIToSUnit.clear();<br>
+ for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {<br>
+ SUnit *SU = &VLIWScheduler->SUnits[i];<br>
+ MIToSUnit[SU->getInstr()] = SU;<br>
+ }<br>
<br>
// The main packetizer loop.<br>
for (; BeginItr != EndItr; ++BeginItr) {<br>
MachineInstr *MI = BeginItr;<br>
<br>
- // Ignore pseudo instructions.<br>
- if (ignorePseudoInstruction(MI, MBB))<br>
- continue;<br>
+ this->initPacketizerState();<br>
<br>
// End the current packet if needed.<br>
- if (isSoloInstruction(MI)) {<br>
+ if (this->isSoloInstruction(MI)) {<br>
endPacket(MBB, MI);<br>
continue;<br>
}<br>
<br>
- SUnit *SUI = SchedulerImpl->getSUnit(MI);<br>
+ // Ignore pseudo instructions.<br>
+ if (this->ignorePseudoInstruction(MI, MBB))<br>
+ continue;<br>
+<br>
+ SUnit *SUI = MIToSUnit[MI];<br>
assert(SUI && "Missing SUnit Info!");<br>
<br>
// Ask DFA if machine resource is available for MI.<br>
@@ -215,13 +196,13 @@<br>
for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),<br>
VE = CurrentPacketMIs.end(); VI != VE; ++VI) {<br>
MachineInstr *MJ = *VI;<br>
- SUnit *SUJ = SchedulerImpl->getSUnit(MJ);<br>
+ SUnit *SUJ = MIToSUnit[MJ];<br>
assert(SUJ && "Missing SUnit Info!");<br>
<br>
// Is it legal to packetize SUI and SUJ together.<br>
- if (!isLegalToPacketizeTogether(SUI, SUJ)) {<br>
+ if (!this->isLegalToPacketizeTogether(SUI, SUJ)) {<br>
// Allow packetization if dependency can be pruned.<br>
- if (!isLegalToPruneDependencies(SUI, SUJ)) {<br>
+ if (!this->isLegalToPruneDependencies(SUI, SUJ)) {<br>
// End the packet if dependency cannot be pruned.<br>
endPacket(MBB, MI);<br>
break;<br>
@@ -234,11 +215,9 @@<br>
}<br>
<br>
// Add MI to the current packet.<br>
- addToPacket(MI);<br>
+ BeginItr = this->addToPacket(MI);<br>
} // For all instructions in BB.<br>
<br>
// End any packet left behind.<br>
endPacket(MBB, EndItr);<br>
-<br>
- SchedulerImpl->exitRegion();<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Thu Apr 12 16:06:38 2012<br>
@@ -27,7 +27,7 @@<br>
HexagonSplitTFRCondSets.cpp<br>
HexagonSubtarget.cpp<br>
HexagonTargetMachine.cpp<br>
- HexagonTargetObjectFile.cpp<br>
+ HexagonVLIWPacketizer.cpp<br>
)<br>
<br>
add_subdirectory(TargetInfo)<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.h?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.h?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/Hexagon.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.h Thu Apr 12 16:06:38 2012<br>
@@ -40,6 +40,7 @@<br>
FunctionPass *createHexagonHardwareLoops();<br>
FunctionPass *createHexagonPeephole();<br>
FunctionPass *createHexagonFixupHwLoops();<br>
+ FunctionPass *createHexagonPacketizer();<br>
<br>
/* TODO: object output.<br>
MCCodeEmitter *createHexagonMCCodeEmitter(const Target &,<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Thu Apr 12 16:06:38 2012<br>
@@ -13,11 +13,11 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
-<br>
#define DEBUG_TYPE "asm-printer"<br>
#include "Hexagon.h"<br>
#include "HexagonAsmPrinter.h"<br>
#include "HexagonMachineFunctionInfo.h"<br>
+#include "HexagonMCInst.h"<br>
#include "HexagonTargetMachine.h"<br>
#include "HexagonSubtarget.h"<br>
#include "InstPrinter/HexagonInstPrinter.h"<br>
@@ -54,6 +54,7 @@<br>
#include "llvm/ADT/SmallString.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
#include "llvm/ADT/StringExtras.h"<br>
+#include <map><br>
<br>
using namespace llvm;<br>
<br>
@@ -196,10 +197,45 @@<br>
/// the current output stream.<br>
///<br>
void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {<br>
- MCInst MCI;<br>
+ if (MI->isBundle()) {<br>
+ std::vector<const MachineInstr*> BundleMIs;<br>
+<br>
+ const MachineBasicBlock *MBB = MI->getParent();<br>
+ MachineBasicBlock::const_instr_iterator MII = MI;<br>
+ ++MII;<br>
+ unsigned int IgnoreCount = 0;<br>
+ while (MII != MBB->end() && MII->isInsideBundle()) {<br>
+ const MachineInstr *MInst = MII;<br>
+ if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||<br>
+ MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {<br>
+ IgnoreCount++;<br>
+ ++MII;<br>
+ continue;<br>
+ }<br>
+ //BundleMIs.push_back(&*MII);<br>
+ BundleMIs.push_back(MInst);<br>
+ ++MII;<br>
+ }<br>
+ unsigned Size = BundleMIs.size();<br>
+ assert((Size+IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!");<br>
+ for (unsigned Index = 0; Index < Size; Index++) {<br>
+ HexagonMCInst MCI;<br>
+ MCI.setStartPacket(Index == 0);<br>
+ MCI.setEndPacket(Index == (Size-1));<br>
<br>
- HexagonLowerToMC(MI, MCI, *this);<br>
- OutStreamer.EmitInstruction(MCI);<br>
+ HexagonLowerToMC(BundleMIs[Index], MCI, *this);<br>
+ OutStreamer.EmitInstruction(MCI);<br>
+ }<br>
+ }<br>
+ else {<br>
+ HexagonMCInst MCI;<br>
+ if (MI->getOpcode() == Hexagon::ENDLOOP0) {<br>
+ MCI.setStartPacket(true);<br>
+ MCI.setEndPacket(true);<br>
+ }<br>
+ HexagonLowerToMC(MI, MCI, *this);<br>
+ OutStreamer.EmitInstruction(MCI);<br>
+ }<br>
<br>
return;<br>
}<br>
@@ -242,17 +278,17 @@<br>
raw_ostream &O) {<br>
const MachineOperand &MO = MI->getOperand(OpNo);<br>
assert( (MO.getType() == MachineOperand::MO_JumpTableIndex) &&<br>
- "Expecting jump table index");<br>
+ "Expecting jump table index");<br>
<br>
// Hexagon_TODO: Do we need name mangling?<br>
O << *GetJTISymbol(MO.getIndex());<br>
}<br>
<br>
void HexagonAsmPrinter::printConstantPool(const MachineInstr *MI, int OpNo,<br>
- raw_ostream &O) {<br>
+ raw_ostream &O) {<br>
const MachineOperand &MO = MI->getOperand(OpNo);<br>
assert( (MO.getType() == MachineOperand::MO_ConstantPoolIndex) &&<br>
- "Expecting constant pool index");<br>
+ "Expecting constant pool index");<br>
<br>
// Hexagon_TODO: Do we need name mangling?<br>
O << *GetCPISymbol(MO.getIndex());<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Thu Apr 12 16:06:38 2012<br>
@@ -13,13 +13,26 @@<br>
// *** Must match HexagonBaseInfo.h ***<br>
//===----------------------------------------------------------------------===//<br>
<br>
+class Type<bits<5> t> {<br>
+ bits<5> Value = t;<br>
+}<br>
+def TypePSEUDO : Type<0>;<br>
+def TypeALU32 : Type<1>;<br>
+def TypeCR : Type<2>;<br>
+def TypeJR : Type<3>;<br>
+def TypeJ : Type<4>;<br>
+def TypeLD : Type<5>;<br>
+def TypeST : Type<6>;<br>
+def TypeSYSTEM : Type<7>;<br>
+def TypeXTYPE : Type<8>;<br>
+def TypeMARKER : Type<31>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Intruction Class Declaration +<br>
//===----------------------------------------------------------------------===//<br>
<br>
class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
- string cstr, InstrItinClass itin> : Instruction {<br>
+ string cstr, InstrItinClass itin, Type type> : Instruction {<br>
field bits<32> Inst;<br>
<br>
let Namespace = "Hexagon";<br>
@@ -31,11 +44,15 @@<br>
let Constraints = cstr;<br>
let Itinerary = itin;<br>
<br>
- // *** The code below must match HexagonBaseInfo.h ***<br>
+ // *** Must match HexagonBaseInfo.h ***<br>
+ Type HexagonType = type;<br>
+ let TSFlags{4-0} = HexagonType.Value;<br>
+ bits<1> isHexagonSolo = 0;<br>
+ let TSFlags{5} = isHexagonSolo;<br>
<br>
// Predicated instructions.<br>
bits<1> isPredicated = 0;<br>
- let TSFlags{1} = isPredicated;<br>
+ let TSFlags{6} = isPredicated;<br>
<br>
// *** The code above must match HexagonBaseInfo.h ***<br>
}<br>
@@ -47,28 +64,40 @@<br>
// LD Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", LD> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<13> imm13;<br>
+ let mayLoad = 1;<br>
}<br>
<br>
// LD Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
string cstr><br>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, LD> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
bits<13> imm13;<br>
+ let mayLoad = 1;<br>
}<br>
<br>
// ST Instruction Class in V2/V3 can take SLOT0 only.<br>
// ST Instruction Class in V4 can take SLOT0 & SLOT1.<br>
// Definition of the instruction class CHANGED from V2/V3 to V4.<br>
class STInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", ST> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {<br>
+ bits<5> rd;<br>
+ bits<5> rs;<br>
+ bits<13> imm13;<br>
+ let mayStore = 1;<br>
+}<br>
+<br>
+// SYSTEM Instruction Class in V4 can take SLOT0 only<br>
+// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.<br>
+class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<13> imm13;<br>
@@ -79,17 +108,18 @@<br>
// Definition of the instruction class CHANGED from V2/V3 to V4.<br>
class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
string cstr><br>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, ST> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
bits<13> imm13;<br>
+ let mayStore = 1;<br>
}<br>
<br>
// ALU32 Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", ALU32> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
@@ -102,7 +132,17 @@<br>
// Definition of the instruction class NOT CHANGED.<br>
// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.<br>
class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", ALU64> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {<br>
+ bits<5> rd;<br>
+ bits<5> rs;<br>
+ bits<5> rt;<br>
+ bits<16> imm16;<br>
+ bits<16> imm16_2;<br>
+}<br>
+<br>
+class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
+ string cstr><br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
@@ -115,7 +155,7 @@<br>
// Definition of the instruction class NOT CHANGED.<br>
// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.<br>
class MInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", M> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
@@ -126,8 +166,8 @@<br>
// Definition of the instruction class NOT CHANGED.<br>
// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.<br>
class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
- string cstr><br>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, M> {<br>
+ string cstr><br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
@@ -138,9 +178,7 @@<br>
// Definition of the instruction class NOT CHANGED.<br>
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.<br>
class SInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
-//: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> {<br>
- : InstHexagon<outs, ins, asmstr, pattern, "", S> {<br>
-// : InstHexagon<outs, ins, asmstr, pattern, "", S> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
@@ -151,8 +189,8 @@<br>
// Definition of the instruction class NOT CHANGED.<br>
// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.<br>
class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
- string cstr><br>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {<br>
+ string cstr><br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {<br>
// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {<br>
// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {<br>
bits<5> rd;<br>
@@ -163,14 +201,14 @@<br>
// J Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
class JType<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", J> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {<br>
bits<16> imm16;<br>
}<br>
<br>
// JR Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
class JRType<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", JR> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {<br>
bits<5> rs;<br>
bits<5> pu; // Predicate register<br>
}<br>
@@ -178,15 +216,22 @@<br>
// CR Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", CR> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {<br>
bits<5> rs;<br>
bits<10> imm10;<br>
}<br>
<br>
+class Marker<dag outs, dag ins, string asmstr, list<dag> pattern><br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {<br>
+ let isCodeGenOnly = 1;<br>
+ let isPseudo = 1;<br>
+}<br>
<br>
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;<br>
-<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {<br>
+ let isCodeGenOnly = 1;<br>
+ let isPseudo = 1;<br>
+}<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Intruction Classes Definitions -<br>
@@ -222,6 +267,11 @@<br>
: ALU64Type<outs, ins, asmstr, pattern> {<br>
}<br>
<br>
+class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern><br>
+ : ALU64Type<outs, ins, asmstr, pattern> {<br>
+ let rt{0-4} = 0;<br>
+}<br>
+<br>
// J Type Instructions.<br>
class JInst<dag outs, dag ins, string asmstr, list<dag> pattern><br>
: JType<outs, ins, asmstr, pattern> {<br>
@@ -237,12 +287,14 @@<br>
class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr><br>
: STInstPost<outs, ins, asmstr, pattern, cstr> {<br>
let rt{0-4} = 0;<br>
+ let mayStore = 1;<br>
}<br>
<br>
// Post increment LD Instruction.<br>
class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr><br>
: LDInstPost<outs, ins, asmstr, pattern, cstr> {<br>
let rt{0-4} = 0;<br>
+ let mayLoad = 1;<br>
}<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Thu Apr 12 16:06:38 2012<br>
@@ -11,11 +11,25 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
+//----------------------------------------------------------------------------//<br>
+// Hexagon Intruction Flags +<br>
+//<br>
+// *** Must match BaseInfo.h ***<br>
+//----------------------------------------------------------------------------//<br>
+<br>
+def TypeMEMOP : Type<9>;<br>
+def TypeNV : Type<10>;<br>
+def TypePREFIX : Type<30>;<br>
+<br>
+//----------------------------------------------------------------------------//<br>
+// Intruction Classes Definitions +<br>
+//----------------------------------------------------------------------------//<br>
+<br>
//<br>
// NV type instructions.<br>
//<br>
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", NV_V4, TypeNV> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<13> imm13;<br>
@@ -24,7 +38,7 @@<br>
// Definition of Post increment new value store.<br>
class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,<br>
string cstr><br>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<5> rt;<br>
@@ -39,8 +53,15 @@<br>
}<br>
<br>
class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern><br>
- : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4> {<br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> {<br>
bits<5> rd;<br>
bits<5> rs;<br>
bits<6> imm6;<br>
}<br>
+<br>
+class Immext<dag outs, dag ins, string asmstr, list<dag> pattern><br>
+ : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX> {<br>
+ let isCodeGenOnly = 1;<br>
+<br>
+ bits<26> imm26;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Thu Apr 12 16:06:38 2012<br>
@@ -11,10 +11,10 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
-#include "Hexagon.h"<br>
#include "HexagonInstrInfo.h"<br>
#include "HexagonRegisterInfo.h"<br>
#include "HexagonSubtarget.h"<br>
+#include "Hexagon.h"<br>
#include "llvm/ADT/STLExtras.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
#include "llvm/CodeGen/DFAPacketizer.h"<br>
@@ -466,7 +466,869 @@<br>
return NewReg;<br>
}<br>
<br>
+bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {<br>
+ switch(MI->getOpcode()) {<br>
+ // JMP_EQri<br>
+ case Hexagon::JMP_EQriPt_nv_V4:<br>
+ case Hexagon::JMP_EQriPnt_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPt_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPnt_nv_V4:<br>
+<br>
+ // JMP_EQri - with -1<br>
+ case Hexagon::JMP_EQriPtneg_nv_V4:<br>
+ case Hexagon::JMP_EQriPntneg_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPtneg_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPntneg_nv_V4:<br>
+<br>
+ // JMP_EQrr<br>
+ case Hexagon::JMP_EQrrPt_nv_V4:<br>
+ case Hexagon::JMP_EQrrPnt_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPt_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPnt_nv_V4:<br>
+<br>
+ // JMP_GTri<br>
+ case Hexagon::JMP_GTriPt_nv_V4:<br>
+ case Hexagon::JMP_GTriPnt_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPnt_nv_V4:<br>
+<br>
+ // JMP_GTri - with -1<br>
+ case Hexagon::JMP_GTriPtneg_nv_V4:<br>
+ case Hexagon::JMP_GTriPntneg_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPtneg_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPntneg_nv_V4:<br>
+<br>
+ // JMP_GTrr<br>
+ case Hexagon::JMP_GTrrPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrPnt_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPnt_nv_V4:<br>
+<br>
+ // JMP_GTrrdn<br>
+ case Hexagon::JMP_GTrrdnPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnPnt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPnt_nv_V4:<br>
+<br>
+ // JMP_GTUri<br>
+ case Hexagon::JMP_GTUriPt_nv_V4:<br>
+ case Hexagon::JMP_GTUriPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPnt_nv_V4:<br>
+<br>
+ // JMP_GTUrr<br>
+ case Hexagon::JMP_GTUrrPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPnt_nv_V4:<br>
+<br>
+ // JMP_GTUrrdn<br>
+ case Hexagon::JMP_GTUrrdnPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:<br>
+ return true;<br>
+<br>
+ // TFR_FI<br>
+ case Hexagon::TFR_FI:<br>
+ return true;<br>
+<br>
+<br>
+ default:<br>
+ return false;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {<br>
+ switch(MI->getOpcode()) {<br>
+ // JMP_EQri<br>
+ case Hexagon::JMP_EQriPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_EQri - with -1<br>
+ case Hexagon::JMP_EQriPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriPntneg_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:<br>
+<br>
+ // JMP_EQrr<br>
+ case Hexagon::JMP_EQrrPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQrrPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTri<br>
+ case Hexagon::JMP_GTriPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTri - with -1<br>
+ case Hexagon::JMP_GTriPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriPntneg_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:<br>
+<br>
+ // JMP_GTrr<br>
+ case Hexagon::JMP_GTrrPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTrrdn<br>
+ case Hexagon::JMP_GTrrdnPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTUri<br>
+ case Hexagon::JMP_GTUriPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUriPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTUrr<br>
+ case Hexagon::JMP_GTUrrPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTUrrdn<br>
+ case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:<br>
+<br>
+ // V4 absolute set addressing.<br>
+ case Hexagon::LDrid_abs_setimm_V4:<br>
+ case Hexagon::LDriw_abs_setimm_V4:<br>
+ case Hexagon::LDrih_abs_setimm_V4:<br>
+ case Hexagon::LDrib_abs_setimm_V4:<br>
+ case Hexagon::LDriuh_abs_setimm_V4:<br>
+ case Hexagon::LDriub_abs_setimm_V4:<br>
+<br>
+ case Hexagon::STrid_abs_setimm_V4:<br>
+ case Hexagon::STrib_abs_setimm_V4:<br>
+ case Hexagon::STrih_abs_setimm_V4:<br>
+ case Hexagon::STriw_abs_setimm_V4:<br>
+<br>
+ // V4 global address load.<br>
+ case Hexagon::LDrid_GP_cPt_V4 :<br>
+ case Hexagon::LDrid_GP_cNotPt_V4 :<br>
+ case Hexagon::LDrid_GP_cdnPt_V4 :<br>
+ case Hexagon::LDrid_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_GP_cPt_V4 :<br>
+ case Hexagon::LDrib_GP_cNotPt_V4 :<br>
+ case Hexagon::LDrib_GP_cdnPt_V4 :<br>
+ case Hexagon::LDrib_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_GP_cPt_V4 :<br>
+ case Hexagon::LDriub_GP_cNotPt_V4 :<br>
+ case Hexagon::LDriub_GP_cdnPt_V4 :<br>
+ case Hexagon::LDriub_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_GP_cPt_V4 :<br>
+ case Hexagon::LDrih_GP_cNotPt_V4 :<br>
+ case Hexagon::LDrih_GP_cdnPt_V4 :<br>
+ case Hexagon::LDrih_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cNotPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_GP_cPt_V4 :<br>
+ case Hexagon::LDriw_GP_cNotPt_V4 :<br>
+ case Hexagon::LDriw_GP_cdnPt_V4 :<br>
+ case Hexagon::LDriw_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDd_GP_cPt_V4 :<br>
+ case Hexagon::LDd_GP_cNotPt_V4 :<br>
+ case Hexagon::LDd_GP_cdnPt_V4 :<br>
+ case Hexagon::LDd_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDb_GP_cPt_V4 :<br>
+ case Hexagon::LDb_GP_cNotPt_V4 :<br>
+ case Hexagon::LDb_GP_cdnPt_V4 :<br>
+ case Hexagon::LDb_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDub_GP_cPt_V4 :<br>
+ case Hexagon::LDub_GP_cNotPt_V4 :<br>
+ case Hexagon::LDub_GP_cdnPt_V4 :<br>
+ case Hexagon::LDub_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDh_GP_cPt_V4 :<br>
+ case Hexagon::LDh_GP_cNotPt_V4 :<br>
+ case Hexagon::LDh_GP_cdnPt_V4 :<br>
+ case Hexagon::LDh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDuh_GP_cPt_V4 :<br>
+ case Hexagon::LDuh_GP_cNotPt_V4 :<br>
+ case Hexagon::LDuh_GP_cdnPt_V4 :<br>
+ case Hexagon::LDuh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDw_GP_cPt_V4 :<br>
+ case Hexagon::LDw_GP_cNotPt_V4 :<br>
+ case Hexagon::LDw_GP_cdnPt_V4 :<br>
+ case Hexagon::LDw_GP_cdnNotPt_V4 :<br>
+<br>
+ // V4 global address store.<br>
+ case Hexagon::STrid_GP_cPt_V4 :<br>
+ case Hexagon::STrid_GP_cNotPt_V4 :<br>
+ case Hexagon::STrid_GP_cdnPt_V4 :<br>
+ case Hexagon::STrid_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_GP_cPt_V4 :<br>
+ case Hexagon::STrib_GP_cNotPt_V4 :<br>
+ case Hexagon::STrib_GP_cdnPt_V4 :<br>
+ case Hexagon::STrib_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_GP_cPt_V4 :<br>
+ case Hexagon::STrih_GP_cNotPt_V4 :<br>
+ case Hexagon::STrih_GP_cdnPt_V4 :<br>
+ case Hexagon::STrih_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_GP_cPt_V4 :<br>
+ case Hexagon::STriw_GP_cNotPt_V4 :<br>
+ case Hexagon::STriw_GP_cdnPt_V4 :<br>
+ case Hexagon::STriw_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STd_GP_cPt_V4 :<br>
+ case Hexagon::STd_GP_cNotPt_V4 :<br>
+ case Hexagon::STd_GP_cdnPt_V4 :<br>
+ case Hexagon::STd_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STb_GP_cPt_V4 :<br>
+ case Hexagon::STb_GP_cNotPt_V4 :<br>
+ case Hexagon::STb_GP_cdnPt_V4 :<br>
+ case Hexagon::STb_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STh_GP_cPt_V4 :<br>
+ case Hexagon::STh_GP_cNotPt_V4 :<br>
+ case Hexagon::STh_GP_cdnPt_V4 :<br>
+ case Hexagon::STh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STw_GP_cPt_V4 :<br>
+ case Hexagon::STw_GP_cNotPt_V4 :<br>
+ case Hexagon::STw_GP_cdnPt_V4 :<br>
+ case Hexagon::STw_GP_cdnNotPt_V4 :<br>
+<br>
+ // V4 predicated global address new value store.<br>
+ case Hexagon::STrib_GP_cPt_nv_V4 :<br>
+ case Hexagon::STrib_GP_cNotPt_nv_V4 :<br>
+ case Hexagon::STrib_GP_cdnPt_nv_V4 :<br>
+ case Hexagon::STrib_GP_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STrih_GP_cPt_nv_V4 :<br>
+ case Hexagon::STrih_GP_cNotPt_nv_V4 :<br>
+ case Hexagon::STrih_GP_cdnPt_nv_V4 :<br>
+ case Hexagon::STrih_GP_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STriw_GP_cPt_nv_V4 :<br>
+ case Hexagon::STriw_GP_cNotPt_nv_V4 :<br>
+ case Hexagon::STriw_GP_cdnPt_nv_V4 :<br>
+ case Hexagon::STriw_GP_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STb_GP_cPt_nv_V4 :<br>
+ case Hexagon::STb_GP_cNotPt_nv_V4 :<br>
+ case Hexagon::STb_GP_cdnPt_nv_V4 :<br>
+ case Hexagon::STb_GP_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STh_GP_cPt_nv_V4 :<br>
+ case Hexagon::STh_GP_cNotPt_nv_V4 :<br>
+ case Hexagon::STh_GP_cdnPt_nv_V4 :<br>
+ case Hexagon::STh_GP_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STw_GP_cPt_nv_V4 :<br>
+ case Hexagon::STw_GP_cNotPt_nv_V4 :<br>
+ case Hexagon::STw_GP_cdnPt_nv_V4 :<br>
+ case Hexagon::STw_GP_cdnNotPt_nv_V4 :<br>
+<br>
+ // TFR_FI<br>
+ case Hexagon::TFR_FI_immext_V4:<br>
+ return true;<br>
+<br>
+ default:<br>
+ return false;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {<br>
+ switch (MI->getOpcode()) {<br>
+ // JMP_EQri<br>
+ case Hexagon::JMP_EQriPt_nv_V4:<br>
+ case Hexagon::JMP_EQriPnt_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPt_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPnt_nv_V4:<br>
+ case Hexagon::JMP_EQriPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_EQri - with -1<br>
+ case Hexagon::JMP_EQriPtneg_nv_V4:<br>
+ case Hexagon::JMP_EQriPntneg_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPtneg_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPntneg_nv_V4:<br>
+ case Hexagon::JMP_EQriPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriPntneg_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:<br>
+<br>
+ // JMP_EQrr<br>
+ case Hexagon::JMP_EQrrPt_nv_V4:<br>
+ case Hexagon::JMP_EQrrPnt_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPt_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPnt_nv_V4:<br>
+ case Hexagon::JMP_EQrrPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQrrPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTri<br>
+ case Hexagon::JMP_GTriPt_nv_V4:<br>
+ case Hexagon::JMP_GTriPnt_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPnt_nv_V4:<br>
+ case Hexagon::JMP_GTriPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTri - with -1<br>
+ case Hexagon::JMP_GTriPtneg_nv_V4:<br>
+ case Hexagon::JMP_GTriPntneg_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPtneg_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPntneg_nv_V4:<br>
+ case Hexagon::JMP_GTriPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriPntneg_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:<br>
+ case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:<br>
+<br>
+ // JMP_GTrr<br>
+ case Hexagon::JMP_GTrrPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrPnt_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPnt_nv_V4:<br>
+ case Hexagon::JMP_GTrrPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTrrdn<br>
+ case Hexagon::JMP_GTrrdnPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnPnt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPnt_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTUri<br>
+ case Hexagon::JMP_GTUriPt_nv_V4:<br>
+ case Hexagon::JMP_GTUriPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUriPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUriPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTUrr<br>
+ case Hexagon::JMP_GTUrrPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:<br>
+<br>
+ // JMP_GTUrrdn<br>
+ case Hexagon::JMP_GTUrrdnPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:<br>
+ case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:<br>
+ return true;<br>
+<br>
+ default:<br>
+ return false;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {<br>
+ switch(MI->getOpcode()) {<br>
+ // JMP_EQri<br>
+ case Hexagon::JMP_EQriPt_nv_V4:<br>
+ return Hexagon::JMP_EQriPt_ie_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPt_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_EQriPnt_nv_V4:<br>
+ return Hexagon::JMP_EQriPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPnt_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_EQri -- with -1<br>
+ case Hexagon::JMP_EQriPtneg_nv_V4:<br>
+ return Hexagon::JMP_EQriPtneg_ie_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPtneg_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;<br>
+ case Hexagon::JMP_EQriPntneg_nv_V4:<br>
+ return Hexagon::JMP_EQriPntneg_ie_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPntneg_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;<br>
+<br>
+ // JMP_EQrr<br>
+ case Hexagon::JMP_EQrrPt_nv_V4:<br>
+ return Hexagon::JMP_EQrrPt_ie_nv_V4;<br>
+ case Hexagon::JMP_EQrrNotPt_nv_V4:<br>
+ return Hexagon::JMP_EQrrNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_EQrrPnt_nv_V4:<br>
+ return Hexagon::JMP_EQrrPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_EQrrNotPnt_nv_V4:<br>
+ return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_GTri<br>
+ case Hexagon::JMP_GTriPt_nv_V4:<br>
+ return Hexagon::JMP_GTriPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPt_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTriPnt_nv_V4:<br>
+ return Hexagon::JMP_GTriPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPnt_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_GTri -- with -1<br>
+ case Hexagon::JMP_GTriPtneg_nv_V4:<br>
+ return Hexagon::JMP_GTriPtneg_ie_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPtneg_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;<br>
+ case Hexagon::JMP_GTriPntneg_nv_V4:<br>
+ return Hexagon::JMP_GTriPntneg_ie_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPntneg_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;<br>
+<br>
+ // JMP_GTrr<br>
+ case Hexagon::JMP_GTrrPt_nv_V4:<br>
+ return Hexagon::JMP_GTrrPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTrrNotPt_nv_V4:<br>
+ return Hexagon::JMP_GTrrNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTrrPnt_nv_V4:<br>
+ return Hexagon::JMP_GTrrPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTrrNotPnt_nv_V4:<br>
+ return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_GTrrdn<br>
+ case Hexagon::JMP_GTrrdnPt_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTrrdnNotPt_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTrrdnPnt_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTrrdnNotPnt_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_GTUri<br>
+ case Hexagon::JMP_GTUriPt_nv_V4:<br>
+ return Hexagon::JMP_GTUriPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUriNotPt_nv_V4:<br>
+ return Hexagon::JMP_GTUriNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUriPnt_nv_V4:<br>
+ return Hexagon::JMP_GTUriPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUriNotPnt_nv_V4:<br>
+ return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_GTUrr<br>
+ case Hexagon::JMP_GTUrrPt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUrrNotPt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUrrPnt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUrrNotPnt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;<br>
+<br>
+ // JMP_GTUrrdn<br>
+ case Hexagon::JMP_GTUrrdnPt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUrrdnNotPt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUrrdnPnt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;<br>
+ case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;<br>
+<br>
+ case Hexagon::TFR_FI:<br>
+ return Hexagon::TFR_FI_immext_V4;<br>
+<br>
+ case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_ADDi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_SUBi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_ADDr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_SUBr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_ANDr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_ORr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMw_ADDSUBi_MEM_V4 :<br>
+ case Hexagon::MEMw_ADDi_MEM_V4 :<br>
+ case Hexagon::MEMw_SUBi_MEM_V4 :<br>
+ case Hexagon::MEMw_ADDr_MEM_V4 :<br>
+ case Hexagon::MEMw_SUBr_MEM_V4 :<br>
+ case Hexagon::MEMw_ANDr_MEM_V4 :<br>
+ case Hexagon::MEMw_ORr_MEM_V4 :<br>
+ case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_ADDi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_SUBi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_ADDr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_SUBr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_ANDr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_ORr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMh_ADDSUBi_MEM_V4 :<br>
+ case Hexagon::MEMh_ADDi_MEM_V4 :<br>
+ case Hexagon::MEMh_SUBi_MEM_V4 :<br>
+ case Hexagon::MEMh_ADDr_MEM_V4 :<br>
+ case Hexagon::MEMh_SUBr_MEM_V4 :<br>
+ case Hexagon::MEMh_ANDr_MEM_V4 :<br>
+ case Hexagon::MEMh_ORr_MEM_V4 :<br>
+ case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_ADDi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_SUBi_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_ADDr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_SUBr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_ANDr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_ORr_indexed_MEM_V4 :<br>
+ case Hexagon::MEMb_ADDSUBi_MEM_V4 :<br>
+ case Hexagon::MEMb_ADDi_MEM_V4 :<br>
+ case Hexagon::MEMb_SUBi_MEM_V4 :<br>
+ case Hexagon::MEMb_ADDr_MEM_V4 :<br>
+ case Hexagon::MEMb_SUBr_MEM_V4 :<br>
+ case Hexagon::MEMb_ANDr_MEM_V4 :<br>
+ case Hexagon::MEMb_ORr_MEM_V4 :<br>
+ assert(0 && "Needs implementing");<br>
+<br>
+ default:<br>
+ assert(0 && "Unknown type of instruction");<br>
+ }<br>
+ assert(0 && "Unknown type of instruction");<br>
+}<br>
+<br>
+unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {<br>
+ switch(MI->getOpcode()) {<br>
+ // JMP_EQri<br>
+ case Hexagon::JMP_EQriPt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriPt_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPt_nv_V4;<br>
+ case Hexagon::JMP_EQriPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriPnt_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPnt_nv_V4;<br>
<br>
+ // JMP_EQri -- with -1<br>
+ case Hexagon::JMP_EQriPtneg_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriPtneg_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPtneg_nv_V4;<br>
+ case Hexagon::JMP_EQriPntneg_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriPntneg_nv_V4;<br>
+ case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:<br>
+ return Hexagon::JMP_EQriNotPntneg_nv_V4;<br>
+<br>
+ // JMP_EQrr<br>
+ case Hexagon::JMP_EQrrPt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQrrPt_nv_V4;<br>
+ case Hexagon::JMP_EQrrNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQrrNotPt_nv_V4;<br>
+ case Hexagon::JMP_EQrrPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQrrPnt_nv_V4;<br>
+ case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_EQrrNotPnt_nv_V4;<br>
+<br>
+ // JMP_GTri<br>
+ case Hexagon::JMP_GTriPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriPt_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPt_nv_V4;<br>
+ case Hexagon::JMP_GTriPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriPnt_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPnt_nv_V4;<br>
+<br>
+ // JMP_GTri -- with -1<br>
+ case Hexagon::JMP_GTriPtneg_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriPtneg_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPtneg_nv_V4;<br>
+ case Hexagon::JMP_GTriPntneg_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriPntneg_nv_V4;<br>
+ case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:<br>
+ return Hexagon::JMP_GTriNotPntneg_nv_V4;<br>
+<br>
+ // JMP_GTrr<br>
+ case Hexagon::JMP_GTrrPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrPt_nv_V4;<br>
+ case Hexagon::JMP_GTrrNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrNotPt_nv_V4;<br>
+ case Hexagon::JMP_GTrrPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrPnt_nv_V4;<br>
+ case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrNotPnt_nv_V4;<br>
+<br>
+ // JMP_GTrrdn<br>
+ case Hexagon::JMP_GTrrdnPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnPt_nv_V4;<br>
+ case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnNotPt_nv_V4;<br>
+ case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnPnt_nv_V4;<br>
+ case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTrrdnNotPnt_nv_V4;<br>
+<br>
+ // JMP_GTUri<br>
+ case Hexagon::JMP_GTUriPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUriPt_nv_V4;<br>
+ case Hexagon::JMP_GTUriNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUriNotPt_nv_V4;<br>
+ case Hexagon::JMP_GTUriPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUriPnt_nv_V4;<br>
+ case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUriNotPnt_nv_V4;<br>
+<br>
+ // JMP_GTUrr<br>
+ case Hexagon::JMP_GTUrrPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrPt_nv_V4;<br>
+ case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrNotPt_nv_V4;<br>
+ case Hexagon::JMP_GTUrrPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrPnt_nv_V4;<br>
+ case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrNotPnt_nv_V4;<br>
+<br>
+ // JMP_GTUrrdn<br>
+ case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnPt_nv_V4;<br>
+ case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnNotPt_nv_V4;<br>
+ case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnPnt_nv_V4;<br>
+ case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:<br>
+ return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;<br>
+<br>
+ default:<br>
+ assert(0 && "Unknown type of jump instruction");<br>
+ }<br>
+ assert(0 && "Unknown type of jump instruction");<br>
+}<br>
+<br>
+<br>
+bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {<br>
+ switch (MI->getOpcode()) {<br>
+<br>
+ // Store Byte<br>
+ case Hexagon::STrib_nv_V4:<br>
+ case Hexagon::STrib_indexed_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_nv_V4:<br>
+ case Hexagon::STrib_shl_nv_V4:<br>
+ case Hexagon::STrib_GP_nv_V4:<br>
+ case Hexagon::STb_GP_nv_V4:<br>
+ case Hexagon::POST_STbri_nv_V4:<br>
+ case Hexagon::STrib_cPt_nv_V4:<br>
+ case Hexagon::STrib_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_cNotPt_nv_V4:<br>
+ case Hexagon::STrib_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_cPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_cNotPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_cPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:<br>
+ case Hexagon::POST_STbri_cPt_nv_V4:<br>
+ case Hexagon::POST_STbri_cdnPt_nv_V4:<br>
+ case Hexagon::POST_STbri_cNotPt_nv_V4:<br>
+ case Hexagon::POST_STbri_cdnNotPt_nv_V4:<br>
+ case Hexagon::STb_GP_cPt_nv_V4:<br>
+ case Hexagon::STb_GP_cNotPt_nv_V4:<br>
+ case Hexagon::STb_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STb_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_GP_cPt_nv_V4:<br>
+ case Hexagon::STrib_GP_cNotPt_nv_V4:<br>
+ case Hexagon::STrib_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_abs_nv_V4:<br>
+ case Hexagon::STrib_abs_cPt_nv_V4:<br>
+ case Hexagon::STrib_abs_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_abs_cNotPt_nv_V4:<br>
+ case Hexagon::STrib_abs_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_imm_abs_nv_V4:<br>
+ case Hexagon::STrib_imm_abs_cPt_nv_V4:<br>
+ case Hexagon::STrib_imm_abs_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_imm_abs_cNotPt_nv_V4:<br>
+ case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:<br>
+<br>
+ // Store Halfword<br>
+ case Hexagon::STrih_nv_V4:<br>
+ case Hexagon::STrih_indexed_nv_V4:<br>
+ case Hexagon::STrih_indexed_shl_nv_V4:<br>
+ case Hexagon::STrih_shl_nv_V4:<br>
+ case Hexagon::STrih_GP_nv_V4:<br>
+ case Hexagon::STh_GP_nv_V4:<br>
+ case Hexagon::POST_SThri_nv_V4:<br>
+ case Hexagon::STrih_cPt_nv_V4:<br>
+ case Hexagon::STrih_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_cNotPt_nv_V4:<br>
+ case Hexagon::STrih_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_cPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_cNotPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_shl_cPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:<br>
+ case Hexagon::POST_SThri_cPt_nv_V4:<br>
+ case Hexagon::POST_SThri_cdnPt_nv_V4:<br>
+ case Hexagon::POST_SThri_cNotPt_nv_V4:<br>
+ case Hexagon::POST_SThri_cdnNotPt_nv_V4:<br>
+ case Hexagon::STh_GP_cPt_nv_V4:<br>
+ case Hexagon::STh_GP_cNotPt_nv_V4:<br>
+ case Hexagon::STh_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STh_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_GP_cPt_nv_V4:<br>
+ case Hexagon::STrih_GP_cNotPt_nv_V4:<br>
+ case Hexagon::STrih_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_abs_nv_V4:<br>
+ case Hexagon::STrih_abs_cPt_nv_V4:<br>
+ case Hexagon::STrih_abs_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_abs_cNotPt_nv_V4:<br>
+ case Hexagon::STrih_abs_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_imm_abs_nv_V4:<br>
+ case Hexagon::STrih_imm_abs_cPt_nv_V4:<br>
+ case Hexagon::STrih_imm_abs_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_imm_abs_cNotPt_nv_V4:<br>
+ case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:<br>
+<br>
+ // Store Word<br>
+ case Hexagon::STriw_nv_V4:<br>
+ case Hexagon::STriw_indexed_nv_V4:<br>
+ case Hexagon::STriw_indexed_shl_nv_V4:<br>
+ case Hexagon::STriw_shl_nv_V4:<br>
+ case Hexagon::STriw_GP_nv_V4:<br>
+ case Hexagon::STw_GP_nv_V4:<br>
+ case Hexagon::POST_STwri_nv_V4:<br>
+ case Hexagon::STriw_cPt_nv_V4:<br>
+ case Hexagon::STriw_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_cNotPt_nv_V4:<br>
+ case Hexagon::STriw_cdnNotPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_cPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_cNotPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_cdnNotPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_shl_cPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:<br>
+ case Hexagon::POST_STwri_cPt_nv_V4:<br>
+ case Hexagon::POST_STwri_cdnPt_nv_V4:<br>
+ case Hexagon::POST_STwri_cNotPt_nv_V4:<br>
+ case Hexagon::POST_STwri_cdnNotPt_nv_V4:<br>
+ case Hexagon::STw_GP_cPt_nv_V4:<br>
+ case Hexagon::STw_GP_cNotPt_nv_V4:<br>
+ case Hexagon::STw_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STw_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STriw_GP_cPt_nv_V4:<br>
+ case Hexagon::STriw_GP_cNotPt_nv_V4:<br>
+ case Hexagon::STriw_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STriw_abs_nv_V4:<br>
+ case Hexagon::STriw_abs_cPt_nv_V4:<br>
+ case Hexagon::STriw_abs_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_abs_cNotPt_nv_V4:<br>
+ case Hexagon::STriw_abs_cdnNotPt_nv_V4:<br>
+ case Hexagon::STriw_imm_abs_nv_V4:<br>
+ case Hexagon::STriw_imm_abs_cPt_nv_V4:<br>
+ case Hexagon::STriw_imm_abs_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_imm_abs_cNotPt_nv_V4:<br>
+ case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:<br>
+ return true;<br>
+<br>
+ default:<br>
+ return false;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {<br>
+ switch (MI->getOpcode())<br>
+ {<br>
+ // Load Byte<br>
+ case Hexagon::POST_LDrib:<br>
+ case Hexagon::POST_LDrib_cPt:<br>
+ case Hexagon::POST_LDrib_cNotPt:<br>
+ case Hexagon::POST_LDrib_cdnPt_V4:<br>
+ case Hexagon::POST_LDrib_cdnNotPt_V4:<br>
+<br>
+ // Load unsigned byte<br>
+ case Hexagon::POST_LDriub:<br>
+ case Hexagon::POST_LDriub_cPt:<br>
+ case Hexagon::POST_LDriub_cNotPt:<br>
+ case Hexagon::POST_LDriub_cdnPt_V4:<br>
+ case Hexagon::POST_LDriub_cdnNotPt_V4:<br>
+<br>
+ // Load halfword<br>
+ case Hexagon::POST_LDrih:<br>
+ case Hexagon::POST_LDrih_cPt:<br>
+ case Hexagon::POST_LDrih_cNotPt:<br>
+ case Hexagon::POST_LDrih_cdnPt_V4:<br>
+ case Hexagon::POST_LDrih_cdnNotPt_V4:<br>
+<br>
+ // Load unsigned halfword<br>
+ case Hexagon::POST_LDriuh:<br>
+ case Hexagon::POST_LDriuh_cPt:<br>
+ case Hexagon::POST_LDriuh_cNotPt:<br>
+ case Hexagon::POST_LDriuh_cdnPt_V4:<br>
+ case Hexagon::POST_LDriuh_cdnNotPt_V4:<br>
+<br>
+ // Load word<br>
+ case Hexagon::POST_LDriw:<br>
+ case Hexagon::POST_LDriw_cPt:<br>
+ case Hexagon::POST_LDriw_cNotPt:<br>
+ case Hexagon::POST_LDriw_cdnPt_V4:<br>
+ case Hexagon::POST_LDriw_cdnNotPt_V4:<br>
+<br>
+ // Load double word<br>
+ case Hexagon::POST_LDrid:<br>
+ case Hexagon::POST_LDrid_cPt:<br>
+ case Hexagon::POST_LDrid_cNotPt:<br>
+ case Hexagon::POST_LDrid_cdnPt_V4:<br>
+ case Hexagon::POST_LDrid_cdnNotPt_V4:<br>
+<br>
+ // Store byte<br>
+ case Hexagon::POST_STbri:<br>
+ case Hexagon::POST_STbri_cPt:<br>
+ case Hexagon::POST_STbri_cNotPt:<br>
+ case Hexagon::POST_STbri_cdnPt_V4:<br>
+ case Hexagon::POST_STbri_cdnNotPt_V4:<br>
+<br>
+ // Store halfword<br>
+ case Hexagon::POST_SThri:<br>
+ case Hexagon::POST_SThri_cPt:<br>
+ case Hexagon::POST_SThri_cNotPt:<br>
+ case Hexagon::POST_SThri_cdnPt_V4:<br>
+ case Hexagon::POST_SThri_cdnNotPt_V4:<br>
+<br>
+ // Store word<br>
+ case Hexagon::POST_STwri:<br>
+ case Hexagon::POST_STwri_cPt:<br>
+ case Hexagon::POST_STwri_cNotPt:<br>
+ case Hexagon::POST_STwri_cdnPt_V4:<br>
+ case Hexagon::POST_STwri_cdnNotPt_V4:<br>
+<br>
+ // Store double word<br>
+ case Hexagon::POST_STdri:<br>
+ case Hexagon::POST_STdri_cPt:<br>
+ case Hexagon::POST_STdri_cNotPt:<br>
+ case Hexagon::POST_STdri_cdnPt_V4:<br>
+ case Hexagon::POST_STdri_cdnNotPt_V4:<br>
+ return true;<br>
+<br>
+ default:<br>
+ return false;<br>
+ }<br>
+}<br>
+<br>
+bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {<br>
+ return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;<br>
+}<br>
<br>
bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {<br>
bool isPred = MI->getDesc().isPredicable();<br>
@@ -1587,6 +2449,24 @@<br>
return false;<br>
}<br>
<br>
+bool HexagonInstrInfo::<br>
+isConditionalTransfer (const MachineInstr *MI) const {<br>
+ switch (MI->getOpcode()) {<br>
+ case Hexagon::TFR_cPt:<br>
+ case Hexagon::TFR_cNotPt:<br>
+ case Hexagon::TFRI_cPt:<br>
+ case Hexagon::TFRI_cNotPt:<br>
+ case Hexagon::TFR_cdnPt:<br>
+ case Hexagon::TFR_cdnNotPt:<br>
+ case Hexagon::TFRI_cdnPt:<br>
+ case Hexagon::TFRI_cdnNotPt:<br>
+ return true;<br>
+<br>
+ default:<br>
+ return false;<br>
+ }<br>
+ return false;<br>
+}<br>
<br>
bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {<br>
const HexagonRegisterInfo& QRI = getRegisterInfo();<br>
@@ -1626,7 +2506,6 @@<br>
}<br>
}<br>
<br>
-<br>
bool HexagonInstrInfo::<br>
isConditionalLoad (const MachineInstr* MI) const {<br>
const HexagonRegisterInfo& QRI = getRegisterInfo();<br>
@@ -1700,6 +2579,136 @@<br>
}<br>
}<br>
<br>
+// Returns true if an instruction is a conditional store.<br>
+//<br>
+// Note: It doesn't include conditional new-value stores as they can't be<br>
+// converted to .new predicate.<br>
+//<br>
+// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]<br>
+// ^ ^<br>
+// / \ (not OK. it will cause new-value store to be<br>
+// / X conditional on p0.new while R2 producer is<br>
+// / \ on p0)<br>
+// / \.<br>
+// p.new store p.old NV store<br>
+// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]<br>
+// ^ ^<br>
+// \ /<br>
+// \ /<br>
+// \ /<br>
+// p.old store<br>
+// [if (p0)memw(R0+#0)=R2]<br>
+//<br>
+// The above diagram shows the steps involoved in the conversion of a predicated<br>
+// store instruction to its .new predicated new-value form.<br>
+//<br>
+// The following set of instructions further explains the scenario where<br>
+// conditional new-value store becomes invalid when promoted to .new predicate<br>
+// form.<br>
+//<br>
+// { 1) if (p0) r0 = add(r1, r2)<br>
+// 2) p0 = cmp.eq(r3, #0) }<br>
+//<br>
+// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with<br>
+// the first two instructions because in instr 1, r0 is conditional on old value<br>
+// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which<br>
+// is not valid for new-value stores.<br>
+bool HexagonInstrInfo::<br>
+isConditionalStore (const MachineInstr* MI) const {<br>
+ const HexagonRegisterInfo& QRI = getRegisterInfo();<br>
+ switch (MI->getOpcode())<br>
+ {<br>
+ case Hexagon::STrib_imm_cPt_V4 :<br>
+ case Hexagon::STrib_imm_cNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::STrib_cPt :<br>
+ case Hexagon::STrib_cNotPt :<br>
+ case Hexagon::POST_STbri_cPt :<br>
+ case Hexagon::POST_STbri_cNotPt :<br>
+ case Hexagon::STrid_indexed_cPt :<br>
+ case Hexagon::STrid_indexed_cNotPt :<br>
+ case Hexagon::STrid_indexed_shl_cPt_V4 :<br>
+ case Hexagon::POST_STdri_cPt :<br>
+ case Hexagon::POST_STdri_cNotPt :<br>
+ case Hexagon::STrih_cPt :<br>
+ case Hexagon::STrih_cNotPt :<br>
+ case Hexagon::STrih_indexed_cPt :<br>
+ case Hexagon::STrih_indexed_cNotPt :<br>
+ case Hexagon::STrih_imm_cPt_V4 :<br>
+ case Hexagon::STrih_imm_cNotPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::POST_SThri_cPt :<br>
+ case Hexagon::POST_SThri_cNotPt :<br>
+ case Hexagon::STriw_cPt :<br>
+ case Hexagon::STriw_cNotPt :<br>
+ case Hexagon::STriw_indexed_cPt :<br>
+ case Hexagon::STriw_indexed_cNotPt :<br>
+ case Hexagon::STriw_imm_cPt_V4 :<br>
+ case Hexagon::STriw_imm_cNotPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::POST_STwri_cPt :<br>
+ case Hexagon::POST_STwri_cNotPt :<br>
+ return QRI.Subtarget.hasV4TOps();<br>
+<br>
+ // V4 global address store before promoting to dot new.<br>
+ case Hexagon::STrid_GP_cPt_V4 :<br>
+ case Hexagon::STrid_GP_cNotPt_V4 :<br>
+ case Hexagon::STrib_GP_cPt_V4 :<br>
+ case Hexagon::STrib_GP_cNotPt_V4 :<br>
+ case Hexagon::STrih_GP_cPt_V4 :<br>
+ case Hexagon::STrih_GP_cNotPt_V4 :<br>
+ case Hexagon::STriw_GP_cPt_V4 :<br>
+ case Hexagon::STriw_GP_cNotPt_V4 :<br>
+ case Hexagon::STd_GP_cPt_V4 :<br>
+ case Hexagon::STd_GP_cNotPt_V4 :<br>
+ case Hexagon::STb_GP_cPt_V4 :<br>
+ case Hexagon::STb_GP_cNotPt_V4 :<br>
+ case Hexagon::STh_GP_cPt_V4 :<br>
+ case Hexagon::STh_GP_cNotPt_V4 :<br>
+ case Hexagon::STw_GP_cPt_V4 :<br>
+ case Hexagon::STw_GP_cNotPt_V4 :<br>
+ return QRI.Subtarget.hasV4TOps();<br>
+<br>
+ // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded<br>
+ // from the "Conditional Store" list. Because a predicated new value store<br>
+ // would NOT be promoted to a double dot new store. See diagram below:<br>
+ // This function returns yes for those stores that are predicated but not<br>
+ // yet promoted to predicate dot new instructions.<br>
+ //<br>
+ // +---------------------+<br>
+ // /-----| if (p0) memw(..)=r0 |---------\~<br>
+ // || +---------------------+ ||<br>
+ // promote || /\ /\ || promote<br>
+ // || /||\ /||\ ||<br>
+ // \||/ demote || \||/<br>
+ // \/ || || \/<br>
+ // +-------------------------+ || +-------------------------+<br>
+ // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |<br>
+ // +-------------------------+ || +-------------------------+<br>
+ // || || ||<br>
+ // || demote \||/<br>
+ // promote || \/ NOT possible<br>
+ // || || /\~<br>
+ // \||/ || /||\~<br>
+ // \/ || ||<br>
+ // +-----------------------------+<br>
+ // | if (p0.new) memw(..)=r0.new |<br>
+ // +-----------------------------+<br>
+ // Double Dot New Store<br>
+ //<br>
+<br>
+ default:<br>
+ return false;<br>
+<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+<br>
+<br>
DFAPacketizer *HexagonInstrInfo::<br>
CreateTargetScheduleState(const TargetMachine *TM,<br>
const ScheduleDAG *DAG) const {<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Thu Apr 12 16:06:38 2012<br>
@@ -160,10 +160,20 @@<br>
bool isS8_Immediate(const int value) const;<br>
bool isS6_Immediate(const int value) const;<br>
<br>
+ bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;<br>
+ bool isConditionalTransfer(const MachineInstr* MI) const;<br>
bool isConditionalALU32 (const MachineInstr* MI) const;<br>
bool isConditionalLoad (const MachineInstr* MI) const;<br>
+ bool isConditionalStore(const MachineInstr* MI) const;<br>
bool isDeallocRet(const MachineInstr *MI) const;<br>
unsigned getInvertedPredicatedOpcode(const int Opc) const;<br>
+ bool isExtendable(const MachineInstr* MI) const;<br>
+ bool isExtended(const MachineInstr* MI) const;<br>
+ bool isPostIncrement(const MachineInstr* MI) const;<br>
+ bool isNewValueStore(const MachineInstr* MI) const;<br>
+ bool isNewValueJump(const MachineInstr* MI) const;<br>
+ unsigned getImmExtForm(const MachineInstr* MI) const;<br>
+ unsigned getNormalBranchForm(const MachineInstr* MI) const;<br>
<br>
private:<br>
int getMatchingCondBranchOpcode(int Opc, bool sense) const;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Thu Apr 12 16:06:38 2012<br>
@@ -3046,3 +3046,7 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
include "HexagonInstrInfoV4.td"<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// V4 Instructions -<br>
+//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td Thu Apr 12 16:06:38 2012<br>
@@ -41,10 +41,11 @@<br>
}<br>
<br>
<br>
+// Jump to address from register<br>
// if(p?.new) jumpr:t r?<br>
let isReturn = 1, isTerminator = 1, isBarrier = 1,<br>
Defs = [PC], Uses = [R31] in {<br>
- def JMPR_cPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
+ def JMPR_cdnPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
"if ($src1.new) jumpr:t $src2",<br>
[]>, Requires<[HasV3T]>;<br>
}<br>
@@ -52,7 +53,7 @@<br>
// if (!p?.new) jumpr:t r?<br>
let isReturn = 1, isTerminator = 1, isBarrier = 1,<br>
Defs = [PC], Uses = [R31] in {<br>
- def JMPR_cNotPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
+ def JMPR_cdnNotPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
"if (!$src1.new) jumpr:t $src2",<br>
[]>, Requires<[HasV3T]>;<br>
}<br>
@@ -61,7 +62,7 @@<br>
// if(p?.new) jumpr:nt r?<br>
let isReturn = 1, isTerminator = 1, isBarrier = 1,<br>
Defs = [PC], Uses = [R31] in {<br>
- def JMPR_cPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
+ def JMPR_cdnPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
"if ($src1.new) jumpr:nt $src2",<br>
[]>, Requires<[HasV3T]>;<br>
}<br>
@@ -69,7 +70,7 @@<br>
// if (!p?.new) jumpr:nt r?<br>
let isReturn = 1, isTerminator = 1, isBarrier = 1,<br>
Defs = [PC], Uses = [R31] in {<br>
- def JMPR_cNotPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
+ def JMPR_cdnNotPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),<br>
"if (!$src1.new) jumpr:nt $src2",<br>
[]>, Requires<[HasV3T]>;<br>
}<br>
@@ -86,20 +87,22 @@<br>
def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,<br>
DoubleRegs:$src2),<br>
"$dst = max($src2, $src1)",<br>
- [(set DoubleRegs:$dst, (select (i1 (setlt DoubleRegs:$src2,<br>
- DoubleRegs:$src1)),<br>
- DoubleRegs:$src1,<br>
- DoubleRegs:$src2))]>,<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),<br>
+ (i64 DoubleRegs:$src1))),<br>
+ (i64 DoubleRegs:$src1),<br>
+ (i64 DoubleRegs:$src2))))]>,<br>
Requires<[HasV3T]>;<br>
<br>
let AddedComplexity = 200 in<br>
def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,<br>
DoubleRegs:$src2),<br>
"$dst = min($src2, $src1)",<br>
- [(set DoubleRegs:$dst, (select (i1 (setgt DoubleRegs:$src2,<br>
- DoubleRegs:$src1)),<br>
- DoubleRegs:$src1,<br>
- DoubleRegs:$src2))]>,<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),<br>
+ (i64 DoubleRegs:$src1))),<br>
+ (i64 DoubleRegs:$src1),<br>
+ (i64 DoubleRegs:$src2))))]>,<br>
Requires<[HasV3T]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
@@ -109,25 +112,25 @@<br>
<br>
<br>
<br>
-//def : Pat <(brcond (i1 (seteq IntRegs:$src1, 0)), bb:$offset),<br>
-// (JMP_RegEzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;<br>
+//def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),<br>
+// (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;<br>
<br>
-//def : Pat <(brcond (i1 (setne IntRegs:$src1, 0)), bb:$offset),<br>
-// (JMP_RegNzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;<br>
+//def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),<br>
+// (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;<br>
<br>
-//def : Pat <(brcond (i1 (setle IntRegs:$src1, 0)), bb:$offset),<br>
-// (JMP_RegLezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;<br>
+//def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),<br>
+// (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;<br>
<br>
-//def : Pat <(brcond (i1 (setge IntRegs:$src1, 0)), bb:$offset),<br>
-// (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;<br>
+//def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),<br>
+// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;<br>
<br>
-//def : Pat <(brcond (i1 (setgt IntRegs:$src1, -1)), bb:$offset),<br>
-// (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;<br>
+//def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),<br>
+// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;<br>
<br>
<br>
// Map call instruction<br>
-def : Pat<(call IntRegs:$dst),<br>
- (CALLRv3 IntRegs:$dst)>, Requires<[HasV3T]>;<br>
+def : Pat<(call (i32 IntRegs:$dst)),<br>
+ (CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;<br>
def : Pat<(call tglobaladdr:$dst),<br>
(CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;<br>
def : Pat<(call texternalsym:$dst),<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Thu Apr 12 16:06:38 2012<br>
@@ -11,6 +11,11 @@<br>
//<br>
//===----------------------------------------------------------------------===//<br>
<br>
+def IMMEXT : Immext<(outs), (ins),<br>
+ "##immext //should never emit this",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
// Hexagon V4 Architecture spec defines 8 instruction classes:<br>
// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the<br>
// compiler)<br>
@@ -250,23 +255,151 @@<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
+// Generate frame index addresses.<br>
+let neverHasSideEffects = 1, isReMaterializable = 1 in<br>
+def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),<br>
+ (ins IntRegs:$src1, s32Imm:$offset),<br>
+ "$dst = add($src1, ##$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
<br>
//===----------------------------------------------------------------------===//<br>
// ALU32 -<br>
//===----------------------------------------------------------------------===//<br>
<br>
<br>
+//===----------------------------------------------------------------------===//<br>
+// ALU32/PERM +<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+// Combine<br>
+// Rdd=combine(Rs, #s8)<br>
+let neverHasSideEffects = 1 in<br>
+def COMBINE_ri_V4 : ALU32_ri<(outs DoubleRegs:$dst),<br>
+ (ins IntRegs:$src1, s8Imm:$src2),<br>
+ "$dst = combine($src1, #$src2)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+// Rdd=combine(#s8, Rs)<br>
+let neverHasSideEffects = 1 in<br>
+def COMBINE_ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),<br>
+ (ins s8Imm:$src1, IntRegs:$src2),<br>
+ "$dst = combine(#$src1, $src2)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+//===----------------------------------------------------------------------===//<br>
+// ALU32/PERM +<br>
+//===----------------------------------------------------------------------===//<br>
<br>
//===----------------------------------------------------------------------===//<br>
// LD +<br>
//===----------------------------------------------------------------------===//<br>
-///<br>
-/// Make sure that in post increment load, the first operand is always the post<br>
-/// increment operand.<br>
-///<br>
-//// Load doubleword.<br>
-// Rdd=memd(Re=#U6)<br>
+//<br>
+// These absolute set addressing mode instructions accept immediate as<br>
+// an operand. We have duplicated these patterns to take global address.<br>
+<br>
+let neverHasSideEffects = 1 in<br>
+def LDrid_abs_setimm_V4 : LDInst<(outs DoubleRegs:$dst1, IntRegs:$dst2),<br>
+ (ins u6Imm:$addr),<br>
+ "$dst1 = memd($dst2=#$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memb(Re=#U6)<br>
+let neverHasSideEffects = 1 in<br>
+def LDrib_abs_setimm_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins u6Imm:$addr),<br>
+ "$dst1 = memb($dst2=#$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memh(Re=#U6)<br>
+let neverHasSideEffects = 1 in<br>
+def LDrih_abs_setimm_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins u6Imm:$addr),<br>
+ "$dst1 = memh($dst2=#$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memub(Re=#U6)<br>
+let neverHasSideEffects = 1 in<br>
+def LDriub_abs_setimm_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins u6Imm:$addr),<br>
+ "$dst1 = memub($dst2=#$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
+// Rd=memuh(Re=#U6)<br>
+let neverHasSideEffects = 1 in<br>
+def LDriuh_abs_setimm_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins u6Imm:$addr),<br>
+ "$dst1 = memuh($dst2=#$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memw(Re=#U6)<br>
+let neverHasSideEffects = 1 in<br>
+def LDriw_abs_setimm_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins u6Imm:$addr),<br>
+ "$dst1 = memw($dst2=#$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Following patterns are defined for absolute set addressing mode<br>
+// instruction which take global address as operand.<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDrid_abs_set_V4 : LDInst<(outs DoubleRegs:$dst1, IntRegs:$dst2),<br>
+ (ins globaladdress:$addr),<br>
+ "$dst1 = memd($dst2=##$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memb(Re=#U6)<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDrib_abs_set_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins globaladdress:$addr),<br>
+ "$dst1 = memb($dst2=##$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memh(Re=#U6)<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDrih_abs_set_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins globaladdress:$addr),<br>
+ "$dst1 = memh($dst2=##$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memub(Re=#U6)<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriub_abs_set_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins globaladdress:$addr),<br>
+ "$dst1 = memub($dst2=##$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memuh(Re=#U6)<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriuh_abs_set_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins globaladdress:$addr),<br>
+ "$dst1 = memuh($dst2=##$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Rd=memw(Re=#U6)<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriw_abs_set_V4 : LDInst<(outs IntRegs:$dst1, IntRegs:$dst2),<br>
+ (ins globaladdress:$addr),<br>
+ "$dst1 = memw($dst2=##$addr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Load doubleword.<br>
+//<br>
+// Make sure that in post increment load, the first operand is always the post<br>
+// increment operand.<br>
+//<br>
// Rdd=memd(Rs+Rt<<#u2)<br>
// Special case pattern for indexed load without offset which is easier to<br>
// match. AddedComplexity of this pattern should be lower than base+offset load<br>
@@ -276,17 +409,19 @@<br>
def LDrid_indexed_V4 : LDInst<(outs DoubleRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memd($src1+$src2<<#0)",<br>
- [(set DoubleRegs:$dst, (load (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (i64 (load (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 40, isPredicable = 1 in<br>
def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memd($src1+$src2<<#$offset)",<br>
- [(set DoubleRegs:$dst, (load (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (i64 (load (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
//// Load doubleword conditionally.<br>
@@ -362,60 +497,62 @@<br>
// Rdd=memd(Rt<<#u2+#U6)<br>
<br>
//// Load byte.<br>
-// Rd=memb(Re=#U6)<br>
-<br>
// Rd=memb(Rs+Rt<<#u2)<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memb($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (sextloadi8 (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def LDriub_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memub($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (zextloadi8 (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (zextloadi8 (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def LDriub_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memub($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (extloadi8 (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 40, isPredicable = 1 in<br>
def LDrib_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memb($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst,<br>
- (sextloadi8 (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (sextloadi8 (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 40, isPredicable = 1 in<br>
def LDriub_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memub($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst,<br>
- (zextloadi8 (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (zextloadi8 (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 40, isPredicable = 1 in<br>
def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memub($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst, (extloadi8 (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (extloadi8 (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
//// Load byte conditionally.<br>
@@ -561,31 +698,32 @@<br>
// Rd=memb(Rt<<#u2+#U6)<br>
<br>
//// Load halfword<br>
-// Rd=memh(Re=#U6)<br>
-<br>
// Rd=memh(Rs+Rt<<#u2)<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def LDrih_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memh($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (sextloadi16 (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (sextloadi16 (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def LDriuh_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memuh($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (zextloadi16 (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (zextloadi16 (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def LDriuh_ae_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memuh($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (extloadi16 (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (extloadi16 (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rd=memh(Rs+Rt<<#u2)<br>
@@ -593,30 +731,30 @@<br>
def LDrih_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memh($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst,<br>
- (sextloadi16 (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (sextloadi16 (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 40, isPredicable = 1 in<br>
def LDriuh_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memuh($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst,<br>
- (zextloadi16 (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (zextloadi16 (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 40, isPredicable = 1 in<br>
def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memuh($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst,<br>
- (extloadi16 (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (extloadi16 (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
//// Load halfword conditionally.<br>
@@ -762,6 +900,14 @@<br>
// Rd=memh(Rt<<#u2+#U6)<br>
<br>
//// Load word.<br>
+// Load predicate: Fix for bug 5279.<br>
+let mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriw_pred_V4 : LDInst<(outs PredRegs:$dst),<br>
+ (ins MEMri:$addr),<br>
+ "Error; should not emit",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
// Rd=memw(Re=#U6)<br>
<br>
// Rd=memw(Rs+Rt<<#u2)<br>
@@ -769,8 +915,9 @@<br>
def LDriw_indexed_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst=memw($src1+$src2<<#0)",<br>
- [(set IntRegs:$dst, (load (add IntRegs:$src1,<br>
- IntRegs:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (load (add (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rd=memw(Rs+Rt<<#u2)<br>
@@ -778,9 +925,10 @@<br>
def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),<br>
"$dst=memw($src1+$src2<<#$offset)",<br>
- [(set IntRegs:$dst, (load (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$offset))))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (i32 (load (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$offset)))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
//// Load word conditionally.<br>
@@ -955,261 +1103,956 @@<br>
"$src2 = $dst2">,<br>
Requires<[HasV4T]>;<br>
<br>
+/// Load from global offset<br>
<br>
-//===----------------------------------------------------------------------===//<br>
-// LD -<br>
-//===----------------------------------------------------------------------===//<br>
-<br>
-//===----------------------------------------------------------------------===//<br>
-// ST +<br>
-//===----------------------------------------------------------------------===//<br>
-///<br>
-/// Assumptions::: ****** DO NOT IGNORE ********<br>
-/// 1. Make sure that in post increment store, the zero'th operand is always the<br>
-/// post increment operand.<br>
-/// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the<br>
-/// last operand.<br>
-///<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDrid_GP_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins globaladdress:$global, u16Imm:$offset),<br>
+ "$dst=memd(#$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
-// Store doubleword.<br>
-// memd(Re=#U6)=Rtt<br>
-// TODO: needs to be implemented<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrid_GP_cPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1) $dst=memd(##$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
-// memd(Rs+#s11:3)=Rtt<br>
-// memd(Rs+Ru<<#u2)=Rtt<br>
-let AddedComplexity = 10, isPredicable = 1 in<br>
-def STrid_indexed_shl_V4 : STInst<(outs),<br>
- (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),<br>
- "memd($src1+$src2<<#$src3) = $src4",<br>
- [(store DoubleRegs:$src4, (add IntRegs:$src1,<br>
- (shl IntRegs:$src2, u2ImmPred:$src3)))]>,<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrid_GP_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1) $dst=memd(##$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// memd(Ru<<#u2+#U6)=Rtt<br>
-let AddedComplexity = 10 in<br>
-def STrid_shl_V4 : STInst<(outs),<br>
- (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),<br>
- "memd($src1<<#$src2+#$src3) = $src4",<br>
- [(store DoubleRegs:$src4, (shl IntRegs:$src1,<br>
- (add u2ImmPred:$src2,<br>
- u6ImmPred:$src3)))]>,<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrid_GP_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1.new) $dst=memd(##$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// memd(Rx++#s4:3)=Rtt<br>
-// memd(Rx++#s4:3:circ(Mu))=Rtt<br>
-// memd(Rx++I:circ(Mu))=Rtt<br>
-// memd(Rx++Mu)=Rtt<br>
-// memd(Rx++Mu:brev)=Rtt<br>
-// memd(gp+#u16:3)=Rtt<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrid_GP_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1.new) $dst=memd(##$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
-// Store doubleword conditionally.<br>
-// if ([!]Pv[.new]) memd(#u6)=Rtt<br>
-// TODO: needs to be implemented.<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDrib_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global, u16Imm:$offset),<br>
+ "$dst=memb(#$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
-// if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt<br>
-// if (Pv) memd(Rs+#u6:3)=Rtt<br>
-// if (Pv.new) memd(Rs+#u6:3)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_cdnPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),<br>
- "if ($src1.new) memd($addr) = $src2",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrib_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1) $dst=memb(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memd(Rs+#u6:3)=Rtt<br>
-// if (!Pv.new) memd(Rs+#u6:3)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_cdnNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),<br>
- "if (!$src1.new) memd($addr) = $src2",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrib_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1) $dst=memb(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (Pv) memd(Rs+#u6:3)=Rtt<br>
-// if (Pv.new) memd(Rs+#u6:3)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_indexed_cdnPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,<br>
- DoubleRegs:$src4),<br>
- "if ($src1.new) memd($src2+#$src3) = $src4",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrib_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1.new) $dst=memb(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memd(Rs+#u6:3)=Rtt<br>
-// if (!Pv.new) memd(Rs+#u6:3)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_indexed_cdnNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,<br>
- DoubleRegs:$src4),<br>
- "if (!$src1.new) memd($src2+#$src3) = $src4",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrib_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1.new) $dst=memb(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt<br>
-// if (Pv) memd(Rs+Ru<<#u2)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_indexed_shl_cPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
- DoubleRegs:$src5),<br>
- "if ($src1) memd($src2+$src3<<#$src4) = $src5",<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriub_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global, u16Imm:$offset),<br>
+ "$dst=memub(#$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (Pv.new) memd(Rs+Ru<<#u2)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_indexed_shl_cdnPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
- DoubleRegs:$src5),<br>
- "if ($src1) memd($src2+$src3<<#$src4) = $src5",<br>
+<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriub_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1) $dst=memub(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
-// if (!Pv) memd(Rs+Ru<<#u2)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_indexed_shl_cNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
- DoubleRegs:$src5),<br>
- "if (!$src1) memd($src2+$src3<<#$src4) = $src5",<br>
+<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriub_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1) $dst=memub(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
-// if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrid_indexed_shl_cdnNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
- DoubleRegs:$src5),<br>
- "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",<br>
+<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriub_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1.new) $dst=memub(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt<br>
-// if (Pv) memd(Rx++#s4:3)=Rtt<br>
-// if (Pv.new) memd(Rx++#s4:3)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def POST_STdri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
- (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,<br>
- s4_3Imm:$offset),<br>
- "if ($src1.new) memd($src3++#$offset) = $src2",<br>
- [],<br>
- "$src3 = $dst">,<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriub_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1.new) $dst=memub(##$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memd(Rx++#s4:3)=Rtt<br>
-// if (!Pv.new) memd(Rx++#s4:3)=Rtt<br>
-let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in<br>
-def POST_STdri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
- (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,<br>
- s4_3Imm:$offset),<br>
- "if (!$src1.new) memd($src3++#$offset) = $src2",<br>
- [],<br>
- "$src3 = $dst">,<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDrih_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global, u16Imm:$offset),<br>
+ "$dst=memh(#$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
<br>
-// Store byte.<br>
-// memb(Re=#U6)=Rt<br>
-// TODO: needs to be implemented.<br>
-// memb(Rs+#s11:0)=Rt<br>
-// memb(Rs+#u6:0)=#S8<br>
-let AddedComplexity = 10, isPredicable = 1 in<br>
-def STrib_imm_V4 : STInst<(outs),<br>
- (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),<br>
- "memb($src1+#$src2) = #$src3",<br>
- [(truncstorei8 s8ImmPred:$src3, (add IntRegs:$src1,<br>
- u6_0ImmPred:$src2))]>,<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrih_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1) $dst=memh(##$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// memb(Rs+Ru<<#u2)=Rt<br>
-let AddedComplexity = 10, isPredicable = 1 in<br>
-def STrib_indexed_shl_V4 : STInst<(outs),<br>
- (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),<br>
- "memb($src1+$src2<<#$src3) = $src4",<br>
- [(truncstorei8 IntRegs:$src4, (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$src3)))]>,<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrih_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1) $dst=memh(##$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// memb(Ru<<#u2+#U6)=Rt<br>
-let AddedComplexity = 10 in<br>
-def STrib_shl_V4 : STInst<(outs),<br>
- (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),<br>
- "memb($src1<<#$src2+#$src3) = $src4",<br>
- [(truncstorei8 IntRegs:$src4, (shl IntRegs:$src1,<br>
- (add u2ImmPred:$src2,<br>
- u6ImmPred:$src3)))]>,<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrih_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1.new) $dst=memh(##$global+$offset)",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// memb(Rx++#s4:0:circ(Mu))=Rt<br>
-// memb(Rx++I:circ(Mu))=Rt<br>
-// memb(Rx++Mu)=Rt<br>
-// memb(Rx++Mu:brev)=Rt<br>
-// memb(gp+#u16:0)=Rt<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDrih_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1.new) $dst=memh(##$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
<br>
-// Store byte conditionally.<br>
-// if ([!]Pv[.new]) memb(#u6)=Rt<br>
-// if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6<br>
-// if (Pv) memb(Rs+#u6:0)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_imm_cPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
- "if ($src1) memb($src2+#$src3) = #$src4",<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriuh_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global, u16Imm:$offset),<br>
+ "$dst=memuh(#$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (Pv.new) memb(Rs+#u6:0)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_imm_cdnPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
- "if ($src1.new) memb($src2+#$src3) = #$src4",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriuh_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1) $dst=memuh(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memb(Rs+#u6:0)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_imm_cNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
- "if (!$src1) memb($src2+#$src3) = #$src4",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriuh_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1) $dst=memuh(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv.new) memb(Rs+#u6:0)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_imm_cdnNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
- "if (!$src1.new) memb($src2+#$src3) = #$src4",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriuh_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1.new) $dst=memuh(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt<br>
-// if (Pv) memb(Rs+#u6:0)=Rt<br>
-// if (Pv.new) memb(Rs+#u6:0)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_cdnPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
- "if ($src1.new) memb($addr) = $src2",<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriuh_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1.new) $dst=memuh(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memb(Rs+#u6:0)=Rt<br>
-// if (!Pv.new) memb(Rs+#u6:0)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_cdnNotPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
- "if (!$src1.new) memb($addr) = $src2",<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDriw_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global, u16Imm:$offset),<br>
+ "$dst=memw(#$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (Pv) memb(Rs+#u6:0)=Rt<br>
-// if (!Pv) memb(Rs+#u6:0)=Rt<br>
-// if (Pv.new) memb(Rs+#u6:0)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
-def STrib_indexed_cdnPt_V4 : STInst<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
- "if ($src1.new) memb($src2+#$src3) = $src4",<br>
+<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriw_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1) $dst=memw(##$global+$offset)",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv.new) memb(Rs+#u6:0)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriw_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1) $dst=memw(##$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriw_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if ($src1.new) $dst=memw(##$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDriw_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset),<br>
+ "if (!$src1.new) $dst=memw(##$global+$offset)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDd_GP_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins globaladdress:$global),<br>
+ "$dst=memd(#$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rtt=memd(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDd_GP_cPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1) $dst=memd(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// if (!Pv) Rtt=memd(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDd_GP_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1) $dst=memd(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rtt=memd(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDd_GP_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1.new) $dst=memd(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// if (!Pv) Rtt=memd(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDd_GP_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1.new) $dst=memd(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDb_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global),<br>
+ "$dst=memb(#$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memb(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDb_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1) $dst=memb(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) Rt=memb(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDb_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1) $dst=memb(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memb(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDb_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1.new) $dst=memb(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) Rt=memb(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDb_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1.new) $dst=memb(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDub_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global),<br>
+ "$dst=memub(#$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memub(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDub_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1) $dst=memub(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// if (!Pv) Rt=memub(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDub_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1) $dst=memub(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memub(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDub_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1.new) $dst=memub(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// if (!Pv) Rt=memub(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDub_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1.new) $dst=memub(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDh_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global),<br>
+ "$dst=memh(#$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDh_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1) $dst=memh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) Rt=memh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDh_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1) $dst=memh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDh_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1.new) $dst=memh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) Rt=memh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDh_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1.new) $dst=memh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDuh_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global),<br>
+ "$dst=memuh(#$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memuh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDuh_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1) $dst=memuh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) Rt=memuh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDuh_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1) $dst=memuh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memuh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDuh_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1.new) $dst=memuh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) Rt=memuh(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDuh_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1.new) $dst=memuh(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayLoad = 1, neverHasSideEffects = 1 in<br>
+def LDw_GP_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$global),<br>
+ "$dst=memw(#$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memw(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDw_GP_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1) $dst=memw(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// if (!Pv) Rt=memw(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDw_GP_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1) $dst=memw(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) Rt=memw(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDw_GP_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if ($src1.new) $dst=memw(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// if (!Pv) Rt=memw(##global)<br>
+let mayLoad = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def LDw_GP_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$global),<br>
+ "if (!$src1.new) $dst=memw(##$global)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+<br>
+def : Pat <(atomic_load_64 (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (i64 (LDd_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_32 (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (i32 (LDw_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_16 (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (i32 (LDuh_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_8 (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (i32 (LDub_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memw(#foo + 0)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i64 (load (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i64 (LDd_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from Pd = load(globaladdress) -> Rd = memb(globaladdress), Pd = Rd<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i1 (load (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i1 (TFR_PdRs (i32 (LDb_GP_V4 tglobaladdr:$global))))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// When the Interprocedural Global Variable optimizer realizes that a certain<br>
+// global variable takes only two constant values, it shrinks the global to<br>
+// a boolean. Catch those loads here in the following 3 patterns.<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (extloadi1 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDb_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (sextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDb_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memb(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (extloadi8 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDb_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memb(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (sextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDb_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (zextloadi1 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDub_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memub(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (zextloadi8 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDub_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memh(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (extloadi16 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDh_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memh(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (sextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDh_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memuh(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (zextloadi16 (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDuh_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress) -> memw(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (load (HexagonCONST32_GP tglobaladdr:$global))),<br>
+ (i32 (LDw_GP_V4 tglobaladdr:$global))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_64 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_32 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_16 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat <(atomic_load_8 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memd(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i64 (load (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i64 (LDrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memb(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (extloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memb(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (sextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memub(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (zextloadi8 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDriub_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memuh(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (extloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memh(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (sextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// Map from load(globaladdress + x) -> memuh(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (zextloadi16 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDriuh_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from load(globaladdress + x) -> memw(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(i32 (load (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset))),<br>
+ (i32 (LDriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// LD -<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// ST +<br>
+//===----------------------------------------------------------------------===//<br>
+///<br>
+/// Assumptions::: ****** DO NOT IGNORE ********<br>
+/// 1. Make sure that in post increment store, the zero'th operand is always the<br>
+/// post increment operand.<br>
+/// 2. Make sure that the store value operand(Rt/Rtt) in a store is always the<br>
+/// last operand.<br>
+///<br>
+<br>
+// memd(Re=#U6)=Rtt<br>
+def STrid_abs_setimm_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins DoubleRegs:$src1, u6Imm:$src2),<br>
+ "memd($dst1=#$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memb(Re=#U6)=Rs<br>
+def STrib_abs_setimm_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins IntRegs:$src1, u6Imm:$src2),<br>
+ "memb($dst1=#$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memh(Re=#U6)=Rs<br>
+def STrih_abs_setimm_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins IntRegs:$src1, u6Imm:$src2),<br>
+ "memh($dst1=#$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memw(Re=#U6)=Rs<br>
+def STriw_abs_setimm_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins IntRegs:$src1, u6Imm:$src2),<br>
+ "memw($dst1=#$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memd(Re=#U6)=Rtt<br>
+def STrid_abs_set_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins DoubleRegs:$src1, globaladdress:$src2),<br>
+ "memd($dst1=##$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memb(Re=#U6)=Rs<br>
+def STrib_abs_set_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins IntRegs:$src1, globaladdress:$src2),<br>
+ "memb($dst1=##$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memh(Re=#U6)=Rs<br>
+def STrih_abs_set_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins IntRegs:$src1, globaladdress:$src2),<br>
+ "memh($dst1=##$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memw(Re=#U6)=Rs<br>
+def STriw_abs_set_V4 : STInst<(outs IntRegs:$dst1),<br>
+ (ins IntRegs:$src1, globaladdress:$src2),<br>
+ "memw($dst1=##$src2) = $src1",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memd(Rs+Ru<<#u2)=Rtt<br>
+let AddedComplexity = 10, isPredicable = 1 in<br>
+def STrid_indexed_shl_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, DoubleRegs:$src4),<br>
+ "memd($src1+$src2<<#$src3) = $src4",<br>
+ [(store (i64 DoubleRegs:$src4),<br>
+ (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2), u2ImmPred:$src3)))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memd(Ru<<#u2+#U6)=Rtt<br>
+let AddedComplexity = 10 in<br>
+def STrid_shl_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, DoubleRegs:$src4),<br>
+ "memd($src1<<#$src2+#$src3) = $src4",<br>
+ [(store (i64 DoubleRegs:$src4),<br>
+ (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),<br>
+ u6ImmPred:$src3))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memd(Rx++#s4:3)=Rtt<br>
+// memd(Rx++#s4:3:circ(Mu))=Rtt<br>
+// memd(Rx++I:circ(Mu))=Rtt<br>
+// memd(Rx++Mu)=Rtt<br>
+// memd(Rx++Mu:brev)=Rtt<br>
+// memd(gp+#u16:3)=Rtt<br>
+<br>
+// Store doubleword conditionally.<br>
+// if ([!]Pv[.new]) memd(#u6)=Rtt<br>
+// TODO: needs to be implemented.<br>
+<br>
+// if ([!]Pv[.new]) memd(Rs+#u6:3)=Rtt<br>
+// if (Pv) memd(Rs+#u6:3)=Rtt<br>
+// if (Pv.new) memd(Rs+#u6:3)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),<br>
+ "if ($src1.new) memd($addr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memd(Rs+#u6:3)=Rtt<br>
+// if (!Pv.new) memd(Rs+#u6:3)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, MEMri:$addr, DoubleRegs:$src2),<br>
+ "if (!$src1.new) memd($addr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memd(Rs+#u6:3)=Rtt<br>
+// if (Pv.new) memd(Rs+#u6:3)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_indexed_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,<br>
+ DoubleRegs:$src4),<br>
+ "if ($src1.new) memd($src2+#$src3) = $src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memd(Rs+#u6:3)=Rtt<br>
+// if (!Pv.new) memd(Rs+#u6:3)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_indexed_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_3Imm:$src3,<br>
+ DoubleRegs:$src4),<br>
+ "if (!$src1.new) memd($src2+#$src3) = $src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if ([!]Pv[.new]) memd(Rs+Ru<<#u2)=Rtt<br>
+// if (Pv) memd(Rs+Ru<<#u2)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_indexed_shl_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
+ DoubleRegs:$src5),<br>
+ "if ($src1) memd($src2+$src3<<#$src4) = $src5",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv.new) memd(Rs+Ru<<#u2)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_indexed_shl_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
+ DoubleRegs:$src5),<br>
+ "if ($src1.new) memd($src2+$src3<<#$src4) = $src5",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+// if (!Pv) memd(Rs+Ru<<#u2)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_indexed_shl_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
+ DoubleRegs:$src5),<br>
+ "if (!$src1) memd($src2+$src3<<#$src4) = $src5",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+// if (!Pv.new) memd(Rs+Ru<<#u2)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrid_indexed_shl_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
+ DoubleRegs:$src5),<br>
+ "if (!$src1.new) memd($src2+$src3<<#$src4) = $src5",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt<br>
+// if (Pv) memd(Rx++#s4:3)=Rtt<br>
+// if (Pv.new) memd(Rx++#s4:3)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def POST_STdri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,<br>
+ s4_3Imm:$offset),<br>
+ "if ($src1.new) memd($src3++#$offset) = $src2",<br>
+ [],<br>
+ "$src3 = $dst">,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memd(Rx++#s4:3)=Rtt<br>
+// if (!Pv.new) memd(Rx++#s4:3)=Rtt<br>
+let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def POST_STdri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,<br>
+ s4_3Imm:$offset),<br>
+ "if (!$src1.new) memd($src3++#$offset) = $src2",<br>
+ [],<br>
+ "$src3 = $dst">,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// Store byte.<br>
+// memb(Rs+#u6:0)=#S8<br>
+let AddedComplexity = 10, isPredicable = 1 in<br>
+def STrib_imm_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u6_0Imm:$src2, s8Imm:$src3),<br>
+ "memb($src1+#$src2) = #$src3",<br>
+ [(truncstorei8 s8ImmPred:$src3, (add (i32 IntRegs:$src1),<br>
+ u6_0ImmPred:$src2))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memb(Rs+Ru<<#u2)=Rt<br>
+let AddedComplexity = 10, isPredicable = 1 in<br>
+def STrib_indexed_shl_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),<br>
+ "memb($src1+$src2<<#$src3) = $src4",<br>
+ [(truncstorei8 (i32 IntRegs:$src4),<br>
+ (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$src3)))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memb(Ru<<#u2+#U6)=Rt<br>
+let AddedComplexity = 10 in<br>
+def STrib_shl_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),<br>
+ "memb($src1<<#$src2+#$src3) = $src4",<br>
+ [(truncstorei8 (i32 IntRegs:$src4),<br>
+ (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),<br>
+ u6ImmPred:$src3))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memb(Rx++#s4:0:circ(Mu))=Rt<br>
+// memb(Rx++I:circ(Mu))=Rt<br>
+// memb(Rx++Mu)=Rt<br>
+// memb(Rx++Mu:brev)=Rt<br>
+// memb(gp+#u16:0)=Rt<br>
+<br>
+<br>
+// Store byte conditionally.<br>
+// if ([!]Pv[.new]) memb(#u6)=Rt<br>
+// if ([!]Pv[.new]) memb(Rs+#u6:0)=#S6<br>
+// if (Pv) memb(Rs+#u6:0)=#S6<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_imm_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
+ "if ($src1) memb($src2+#$src3) = #$src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv.new) memb(Rs+#u6:0)=#S6<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_imm_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
+ "if ($src1.new) memb($src2+#$src3) = #$src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memb(Rs+#u6:0)=#S6<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_imm_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
+ "if (!$src1) memb($src2+#$src3) = #$src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv.new) memb(Rs+#u6:0)=#S6<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_imm_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, s6Imm:$src4),<br>
+ "if (!$src1.new) memb($src2+#$src3) = #$src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if ([!]Pv[.new]) memb(Rs+#u6:0)=Rt<br>
+// if (Pv) memb(Rs+#u6:0)=Rt<br>
+// if (Pv.new) memb(Rs+#u6:0)=Rt<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
+ "if ($src1.new) memb($addr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memb(Rs+#u6:0)=Rt<br>
+// if (!Pv.new) memb(Rs+#u6:0)=Rt<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
+ "if (!$src1.new) memb($addr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memb(Rs+#u6:0)=Rt<br>
+// if (!Pv) memb(Rs+#u6:0)=Rt<br>
+// if (Pv.new) memb(Rs+#u6:0)=Rt<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
+def STrib_indexed_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
+ "if ($src1.new) memb($src2+#$src3) = $src4",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv.new) memb(Rs+#u6:0)=Rt<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
"if (!$src1.new) memb($src2+#$src3) = $src4",<br>
@@ -1218,7 +2061,8 @@<br>
<br>
// if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Rt<br>
// if (Pv) memb(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1227,7 +2071,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memb(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1236,7 +2081,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memb(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1245,7 +2091,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memb(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1256,7 +2103,8 @@<br>
// if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt<br>
// if (Pv) memb(Rx++#s4:0)=Rt<br>
// if (Pv.new) memb(Rx++#s4:0)=Rt<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STbri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),<br>
"if ($src1.new) memb($src3++#$offset) = $src2",<br>
@@ -1265,7 +2113,8 @@<br>
<br>
// if (!Pv) memb(Rx++#s4:0)=Rt<br>
// if (!Pv.new) memb(Rx++#s4:0)=Rt<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STbri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),<br>
"if (!$src1.new) memb($src3++#$offset) = $src2",<br>
@@ -1274,20 +2123,15 @@<br>
<br>
<br>
// Store halfword.<br>
-// memh(Re=#U6)=Rt.H<br>
-// TODO: needs to be implemented<br>
-<br>
-// memh(Re=#U6)=Rt<br>
// TODO: needs to be implemented<br>
-<br>
+// memh(Re=#U6)=Rt.H<br>
// memh(Rs+#s11:1)=Rt.H<br>
-// memh(Rs+#s11:1)=Rt<br>
// memh(Rs+#u6:1)=#S8<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def STrih_imm_V4 : STInst<(outs),<br>
(ins IntRegs:$src1, u6_1Imm:$src2, s8Imm:$src3),<br>
"memh($src1+#$src2) = #$src3",<br>
- [(truncstorei16 s8ImmPred:$src3, (add IntRegs:$src1,<br>
+ [(truncstorei16 s8ImmPred:$src3, (add (i32 IntRegs:$src1),<br>
u6_1ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -1299,9 +2143,10 @@<br>
def STrih_indexed_shl_V4 : STInst<(outs),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),<br>
"memh($src1+$src2<<#$src3) = $src4",<br>
- [(truncstorei16 IntRegs:$src4, (add IntRegs:$src1,<br>
- (shl IntRegs:$src2,<br>
- u2ImmPred:$src3)))]>,<br>
+ [(truncstorei16 (i32 IntRegs:$src4),<br>
+ (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$src3)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// memh(Ru<<#u2+#U6)=Rt.H<br>
@@ -1310,9 +2155,9 @@<br>
def STrih_shl_V4 : STInst<(outs),<br>
(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),<br>
"memh($src1<<#$src2+#$src3) = $src4",<br>
- [(truncstorei16 IntRegs:$src4, (shl IntRegs:$src1,<br>
- (add u2ImmPred:$src2,<br>
- u6ImmPred:$src3)))]>,<br>
+ [(truncstorei16 (i32 IntRegs:$src4),<br>
+ (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),<br>
+ u6ImmPred:$src3))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// memh(Rx++#s4:1:circ(Mu))=Rt.H<br>
@@ -1323,17 +2168,14 @@<br>
// memh(Rx++Mu)=Rt<br>
// memh(Rx++Mu:brev)=Rt.H<br>
// memh(Rx++Mu:brev)=Rt<br>
-// memh(gp+#u16:1)=Rt.H<br>
// memh(gp+#u16:1)=Rt<br>
-<br>
-<br>
-// Store halfword conditionally.<br>
// if ([!]Pv[.new]) memh(#u6)=Rt.H<br>
// if ([!]Pv[.new]) memh(#u6)=Rt<br>
<br>
// if ([!]Pv[.new]) memh(Rs+#u6:1)=#S6<br>
// if (Pv) memh(Rs+#u6:1)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_imm_cPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),<br>
"if ($src1) memh($src2+#$src3) = #$src4",<br>
@@ -1341,7 +2183,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rs+#u6:1)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_imm_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),<br>
"if ($src1.new) memh($src2+#$src3) = #$src4",<br>
@@ -1349,7 +2192,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memh(Rs+#u6:1)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_imm_cNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),<br>
"if (!$src1) memh($src2+#$src3) = #$src4",<br>
@@ -1357,7 +2201,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rs+#u6:1)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_imm_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, s6Imm:$src4),<br>
"if (!$src1.new) memh($src2+#$src3) = #$src4",<br>
@@ -1370,7 +2215,8 @@<br>
// if ([!]Pv[.new]) memh(Rs+#u6:1)=Rt<br>
// if (Pv) memh(Rs+#u6:1)=Rt<br>
// if (Pv.new) memh(Rs+#u6:1)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1.new) memh($addr) = $src2",<br>
@@ -1379,7 +2225,8 @@<br>
<br>
// if (!Pv) memh(Rs+#u6:1)=Rt<br>
// if (!Pv.new) memh(Rs+#u6:1)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1.new) memh($addr) = $src2",<br>
@@ -1387,7 +2234,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rs+#u6:1)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),<br>
"if ($src1.new) memh($src2+#$src3) = $src4",<br>
@@ -1395,7 +2243,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rs+#u6:1)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),<br>
"if (!$src1.new) memh($src2+#$src3) = $src4",<br>
@@ -1405,7 +2254,8 @@<br>
// if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt.H<br>
// if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Rt<br>
// if (Pv) memh(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1414,6 +2264,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rs+Ru<<#u2)=Rt<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1422,7 +2274,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memh(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1431,7 +2284,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1445,7 +2299,8 @@<br>
// if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt<br>
// if (Pv) memh(Rx++#s4:1)=Rt<br>
// if (Pv.new) memh(Rx++#s4:1)=Rt<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_SThri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),<br>
"if ($src1.new) memh($src3++#$offset) = $src2",<br>
@@ -1454,7 +2309,8 @@<br>
<br>
// if (!Pv) memh(Rx++#s4:1)=Rt<br>
// if (!Pv.new) memh(Rx++#s4:1)=Rt<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_SThri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),<br>
"if (!$src1.new) memh($src3++#$offset) = $src2",<br>
@@ -1466,13 +2322,22 @@<br>
// memw(Re=#U6)=Rt<br>
// TODO: Needs to be implemented.<br>
<br>
-// memw(Rs+#s11:2)=Rt<br>
+// Store predicate:<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STriw_pred_V4 : STInst<(outs),<br>
+ (ins MEMri:$addr, PredRegs:$src1),<br>
+ "Error; should not emit",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
// memw(Rs+#u6:2)=#S8<br>
let AddedComplexity = 10, isPredicable = 1 in<br>
def STriw_imm_V4 : STInst<(outs),<br>
(ins IntRegs:$src1, u6_2Imm:$src2, s8Imm:$src3),<br>
"memw($src1+#$src2) = #$src3",<br>
- [(store s8ImmPred:$src3, (add IntRegs:$src1, u6_2ImmPred:$src2))]>,<br>
+ [(store s8ImmPred:$src3, (add (i32 IntRegs:$src1),<br>
+ u6_2ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// memw(Rs+Ru<<#u2)=Rt<br>
@@ -1480,8 +2345,9 @@<br>
def STriw_indexed_shl_V4 : STInst<(outs),<br>
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, IntRegs:$src4),<br>
"memw($src1+$src2<<#$src3) = $src4",<br>
- [(store IntRegs:$src4, (add IntRegs:$src1,<br>
- (shl IntRegs:$src2, u2ImmPred:$src3)))]>,<br>
+ [(store (i32 IntRegs:$src4), (add (i32 IntRegs:$src1),<br>
+ (shl (i32 IntRegs:$src2),<br>
+ u2ImmPred:$src3)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// memw(Ru<<#u2+#U6)=Rt<br>
@@ -1489,8 +2355,9 @@<br>
def STriw_shl_V4 : STInst<(outs),<br>
(ins IntRegs:$src1, u2Imm:$src2, u6Imm:$src3, IntRegs:$src4),<br>
"memw($src1<<#$src2+#$src3) = $src4",<br>
- [(store IntRegs:$src4, (shl IntRegs:$src1,<br>
- (add u2ImmPred:$src2, u6ImmPred:$src3)))]>,<br>
+ [(store (i32 IntRegs:$src4),<br>
+ (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),<br>
+ u6ImmPred:$src3))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// memw(Rx++#s4:2)=Rt<br>
@@ -1502,12 +2369,11 @@<br>
<br>
<br>
// Store word conditionally.<br>
-// if ([!]Pv[.new]) memw(#u6)=Rt<br>
-// TODO: Needs to be implemented.<br>
<br>
// if ([!]Pv[.new]) memw(Rs+#u6:2)=#S6<br>
// if (Pv) memw(Rs+#u6:2)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_imm_cPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),<br>
"if ($src1) memw($src2+#$src3) = #$src4",<br>
@@ -1515,7 +2381,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memw(Rs+#u6:2)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_imm_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),<br>
"if ($src1.new) memw($src2+#$src3) = #$src4",<br>
@@ -1523,7 +2390,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memw(Rs+#u6:2)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_imm_cNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),<br>
"if (!$src1) memw($src2+#$src3) = #$src4",<br>
@@ -1531,7 +2399,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memw(Rs+#u6:2)=#S6<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_imm_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, s6Imm:$src4),<br>
"if (!$src1.new) memw($src2+#$src3) = #$src4",<br>
@@ -1541,7 +2410,8 @@<br>
// if ([!]Pv[.new]) memw(Rs+#u6:2)=Rt<br>
// if (Pv) memw(Rs+#u6:2)=Rt<br>
// if (Pv.new) memw(Rs+#u6:2)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1.new) memw($addr) = $src2",<br>
@@ -1550,7 +2420,8 @@<br>
<br>
// if (!Pv) memw(Rs+#u6:2)=Rt<br>
// if (!Pv.new) memw(Rs+#u6:2)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1.new) memw($addr) = $src2",<br>
@@ -1560,7 +2431,8 @@<br>
// if (Pv) memw(Rs+#u6:2)=Rt<br>
// if (!Pv) memw(Rs+#u6:2)=Rt<br>
// if (Pv.new) memw(Rs+#u6:2)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),<br>
"if ($src1.new) memw($src2+#$src3) = $src4",<br>
@@ -1568,7 +2440,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memw(Rs+#u6:2)=Rt<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),<br>
"if (!$src1.new) memw($src2+#$src3) = $src4",<br>
@@ -1577,7 +2450,8 @@<br>
<br>
// if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Rt<br>
// if (Pv) memw(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_shl_cPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1586,7 +2460,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memw(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_shl_cdnPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1595,7 +2470,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memw(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_shl_cNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1604,7 +2480,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memw(Rs+Ru<<#u2)=Rt<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_shl_cdnNotPt_V4 : STInst<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1615,7 +2492,8 @@<br>
// if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt<br>
// if (Pv) memw(Rx++#s4:2)=Rt<br>
// if (Pv.new) memw(Rx++#s4:2)=Rt<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STwri_cdnPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
"if ($src1.new) memw($src3++#$offset) = $src2",<br>
@@ -1624,7 +2502,8 @@<br>
<br>
// if (!Pv) memw(Rx++#s4:2)=Rt<br>
// if (!Pv.new) memw(Rx++#s4:2)=Rt<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STwri_cdnNotPt_V4 : STInstPI<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
"if (!$src1.new) memw($src3++#$offset) = $src2",<br>
@@ -1632,6 +2511,439 @@<br>
Requires<[HasV4T]>;<br>
<br>
<br>
+/// store to global address<br>
+<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrid_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, u16Imm:$offset, DoubleRegs:$src),<br>
+ "memd(#$global+$offset) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrid_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ DoubleRegs:$src2),<br>
+ "if ($src1) memd(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrid_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ DoubleRegs:$src2),<br>
+ "if (!$src1) memd(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrid_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ DoubleRegs:$src2),<br>
+ "if ($src1.new) memd(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrid_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ DoubleRegs:$src2),<br>
+ "if (!$src1.new) memd(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrib_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),<br>
+ "memb(#$global+$offset) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrib_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1) memb(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrib_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1) memb(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrib_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1.new) memb(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrib_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1.new) memb(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrih_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),<br>
+ "memh(#$global+$offset) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrih_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1) memh(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrih_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1) memh(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrih_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1.new) memh(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STrih_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1.new) memh(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STriw_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),<br>
+ "memw(#$global+$offset) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STriw_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1) memw(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STriw_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1) memw(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STriw_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1.new) memw(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STriw_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1.new) memw(##$global+$offset) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memd(#global)=Rtt<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STd_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, DoubleRegs:$src),<br>
+ "memd(#$global) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memd(##global) = Rtt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STd_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),<br>
+ "if ($src1) memd(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memd(##global) = Rtt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STd_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),<br>
+ "if (!$src1) memd(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memd(##global) = Rtt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STd_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),<br>
+ "if ($src1.new) memd(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memd(##global) = Rtt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STd_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, DoubleRegs:$src2),<br>
+ "if (!$src1.new) memd(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memb(#global)=Rt<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STb_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, IntRegs:$src),<br>
+ "memb(#$global) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STb_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1) memb(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STb_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1) memb(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STb_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1.new) memb(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STb_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1.new) memb(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memh(#global)=Rt<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STh_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, IntRegs:$src),<br>
+ "memh(#$global) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STh_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1) memh(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STh_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1) memh(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STh_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1.new) memh(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STh_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1.new) memh(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// memw(#global)=Rt<br>
+let isPredicable = 1, mayStore = 1, neverHasSideEffects = 1 in<br>
+def STw_GP_V4 : STInst<(outs),<br>
+ (ins globaladdress:$global, IntRegs:$src),<br>
+ "memw(#$global) = $src",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STw_GP_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1) memw(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STw_GP_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1) memw(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STw_GP_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1.new) memw(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def STw_GP_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1.new) memw(##$global) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// 64 bit atomic store<br>
+def : Pat <(atomic_store_64 (HexagonCONST32_GP tglobaladdr:$global),<br>
+ (i64 DoubleRegs:$src1)),<br>
+ (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress) -> memd(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat <(store (i64 DoubleRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (STd_GP_V4 tglobaladdr:$global, (i64 DoubleRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// 8 bit atomic store<br>
+def : Pat < (atomic_store_8 (HexagonCONST32_GP tglobaladdr:$global),<br>
+ (i32 IntRegs:$src1)),<br>
+ (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress) -> memb(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(truncstorei8 (i32 IntRegs:$src1),<br>
+ (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (STb_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from "i1 = constant<-1>; memw(CONST32(#foo)) = i1"<br>
+// to "r0 = 1; memw(#foo) = r0"<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(store (i1 -1), (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (STb_GP_V4 tglobaladdr:$global, (TFRI 1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat<(atomic_store_16 (HexagonCONST32_GP tglobaladdr:$global),<br>
+ (i32 IntRegs:$src1)),<br>
+ (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress) -> memh(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(truncstorei16 (i32 IntRegs:$src1),<br>
+ (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (STh_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// 32 bit atomic store<br>
+def : Pat<(atomic_store_32 (HexagonCONST32_GP tglobaladdr:$global),<br>
+ (i32 IntRegs:$src1)),<br>
+ (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress) -> memw(#foo)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32_GP tglobaladdr:$global)),<br>
+ (STw_GP_V4 tglobaladdr:$global, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat<(atomic_store_64 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset),<br>
+ (i64 DoubleRegs:$src1)),<br>
+ (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,<br>
+ (i64 DoubleRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat<(atomic_store_32 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset),<br>
+ (i32 IntRegs:$src1)),<br>
+ (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat<(atomic_store_16 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset),<br>
+ (i32 IntRegs:$src1)),<br>
+ (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+def : Pat<(atomic_store_8 (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset),<br>
+ (i32 IntRegs:$src1)),<br>
+ (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress + x) -> memd(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(store (i64 DoubleRegs:$src1), (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (STrid_GP_V4 tglobaladdr:$global, u16ImmPred:$offset,<br>
+ (i64 DoubleRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress + x) -> memb(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(truncstorei8 (i32 IntRegs:$src1),<br>
+ (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (STrib_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress + x) -> memh(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(truncstorei16 (i32 IntRegs:$src1),<br>
+ (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (STrih_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// Map from store(globaladdress + x) -> memw(#foo + x)<br>
+let AddedComplexity = 100 in<br>
+def : Pat<(store (i32 IntRegs:$src1),<br>
+ (add (HexagonCONST32_GP tglobaladdr:$global),<br>
+ u16ImmPred:$offset)),<br>
+ (STriw_GP_V4 tglobaladdr:$global, u16ImmPred:$offset, (i32 IntRegs:$src1))>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+<br>
//===----------------------------------------------------------------------===<br>
// ST -<br>
//===----------------------------------------------------------------------===<br>
@@ -1696,11 +3008,19 @@<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
+// memb(#global)=Nt.new<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STb_GP_nv_V4 : NVInst_V4<(outs),<br>
+ (ins globaladdress:$global, IntRegs:$src),<br>
+ "memb(#$global) = $src.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
// Store new-value byte conditionally.<br>
// if ([!]Pv[.new]) memb(#u6)=Nt.new<br>
// if (Pv) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1) memb($addr) = $src2.new",<br>
@@ -1708,7 +3028,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1.new) memb($addr) = $src2.new",<br>
@@ -1716,7 +3037,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1) memb($addr) = $src2.new",<br>
@@ -1724,7 +3046,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1.new) memb($addr) = $src2.new",<br>
@@ -1732,7 +3055,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
"if ($src1) memb($src2+#$src3) = $src4.new",<br>
@@ -1740,7 +3064,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
"if ($src1.new) memb($src2+#$src3) = $src4.new",<br>
@@ -1748,7 +3073,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
"if (!$src1) memb($src2+#$src3) = $src4.new",<br>
@@ -1756,7 +3082,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memb(Rs+#u6:0)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_0Imm:$src3, IntRegs:$src4),<br>
"if (!$src1.new) memb($src2+#$src3) = $src4.new",<br>
@@ -1766,7 +3093,8 @@<br>
<br>
// if ([!]Pv[.new]) memb(Rs+Ru<<#u2)=Nt.new<br>
// if (Pv) memb(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1775,7 +3103,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memb(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1784,7 +3113,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memb(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1793,7 +3123,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memb(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrib_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1803,7 +3134,8 @@<br>
<br>
// if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new<br>
// if (Pv) memb(Rx++#s4:0)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),<br>
"if ($src1) memb($src3++#$offset) = $src2.new",<br>
@@ -1811,7 +3143,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memb(Rx++#s4:0)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),<br>
"if ($src1.new) memb($src3++#$offset) = $src2.new",<br>
@@ -1819,7 +3152,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memb(Rx++#s4:0)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),<br>
"if (!$src1) memb($src3++#$offset) = $src2.new",<br>
@@ -1827,7 +3161,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memb(Rx++#s4:0)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),<br>
"if (!$src1.new) memb($src3++#$offset) = $src2.new",<br>
@@ -1889,6 +3224,14 @@<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
+// memh(#global)=Nt.new<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STh_GP_nv_V4 : NVInst_V4<(outs),<br>
+ (ins globaladdress:$global, IntRegs:$src),<br>
+ "memh(#$global) = $src.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
<br>
// Store new-value halfword conditionally.<br>
<br>
@@ -1896,7 +3239,8 @@<br>
<br>
// if ([!]Pv[.new]) memh(Rs+#u6:1)=Nt.new<br>
// if (Pv) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1) memh($addr) = $src2.new",<br>
@@ -1904,7 +3248,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1.new) memh($addr) = $src2.new",<br>
@@ -1912,7 +3257,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1) memh($addr) = $src2.new",<br>
@@ -1920,7 +3266,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1.new) memh($addr) = $src2.new",<br>
@@ -1928,7 +3275,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),<br>
"if ($src1) memh($src2+#$src3) = $src4.new",<br>
@@ -1936,7 +3284,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),<br>
"if ($src1.new) memh($src2+#$src3) = $src4.new",<br>
@@ -1944,7 +3293,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),<br>
"if (!$src1) memh($src2+#$src3) = $src4.new",<br>
@@ -1952,7 +3302,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rs+#u6:1)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_1Imm:$src3, IntRegs:$src4),<br>
"if (!$src1.new) memh($src2+#$src3) = $src4.new",<br>
@@ -1961,7 +3312,8 @@<br>
<br>
// if ([!]Pv[.new]) memh(Rs+Ru<<#u2)=Nt.new<br>
// if (Pv) memh(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1970,7 +3322,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1979,7 +3332,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memh(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1988,7 +3342,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STrih_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -1998,7 +3353,8 @@<br>
<br>
// if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new<br>
// if (Pv) memh(Rx++#s4:1)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),<br>
"if ($src1) memh($src3++#$offset) = $src2.new",<br>
@@ -2006,7 +3362,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memh(Rx++#s4:1)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),<br>
"if ($src1.new) memh($src3++#$offset) = $src2.new",<br>
@@ -2014,7 +3371,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memh(Rx++#s4:1)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),<br>
"if (!$src1) memh($src3++#$offset) = $src2.new",<br>
@@ -2022,7 +3380,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memh(Rx++#s4:1)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),<br>
"if (!$src1.new) memh($src3++#$offset) = $src2.new",<br>
@@ -2085,6 +3444,12 @@<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STw_GP_nv_V4 : NVInst_V4<(outs),<br>
+ (ins globaladdress:$global, IntRegs:$src),<br>
+ "memw(#$global) = $src.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
// Store new-value word conditionally.<br>
<br>
@@ -2092,7 +3457,8 @@<br>
<br>
// if ([!]Pv[.new]) memw(Rs+#u6:2)=Nt.new<br>
// if (Pv) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1) memw($addr) = $src2.new",<br>
@@ -2100,7 +3466,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if ($src1.new) memw($addr) = $src2.new",<br>
@@ -2108,7 +3475,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1) memw($addr) = $src2.new",<br>
@@ -2116,7 +3484,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, MEMri:$addr, IntRegs:$src2),<br>
"if (!$src1.new) memw($addr) = $src2.new",<br>
@@ -2124,7 +3493,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),<br>
"if ($src1) memw($src2+#$src3) = $src4.new",<br>
@@ -2132,7 +3502,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),<br>
"if ($src1.new) memw($src2+#$src3) = $src4.new",<br>
@@ -2140,7 +3511,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),<br>
"if (!$src1) memw($src2+#$src3) = $src4.new",<br>
@@ -2148,7 +3520,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (!Pv.new) memw(Rs+#u6:2)=Nt.new<br>
-let mayStore = 1, neverHasSideEffects = 1 in<br>
+let mayStore = 1, neverHasSideEffects = 1,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, u6_2Imm:$src3, IntRegs:$src4),<br>
"if (!$src1.new) memw($src2+#$src3) = $src4.new",<br>
@@ -2158,7 +3531,8 @@<br>
<br>
// if ([!]Pv[.new]) memw(Rs+Ru<<#u2)=Nt.new<br>
// if (Pv) memw(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_shl_cPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -2167,7 +3541,8 @@<br>
Requires<[HasV4T]>;<br>
<br>
// if (Pv.new) memw(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
def STriw_indexed_shl_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
IntRegs:$src5),<br>
@@ -2175,57 +3550,256 @@<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memw(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
-def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
- IntRegs:$src5),<br>
- "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",<br>
+// if (!Pv) memw(Rs+Ru<<#u2)=Nt.new<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
+def STriw_indexed_shl_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
+ IntRegs:$src5),<br>
+ "if (!$src1) memw($src2+$src3<<#$src4) = $src5.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new<br>
+let mayStore = 1, AddedComplexity = 10,<br>
+ isPredicated = 1 in<br>
+def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
+ IntRegs:$src5),<br>
+ "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new<br>
+// if (Pv) memw(Rx++#s4:2)=Nt.new<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
+def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
+ "if ($src1) memw($src3++#$offset) = $src2.new",<br>
+ [],"$src3 = $dst">,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv.new) memw(Rx++#s4:2)=Nt.new<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
+def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
+ "if ($src1.new) memw($src3++#$offset) = $src2.new",<br>
+ [],"$src3 = $dst">,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memw(Rx++#s4:2)=Nt.new<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
+def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
+ "if (!$src1) memw($src3++#$offset) = $src2.new",<br>
+ [],"$src3 = $dst">,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv.new) memw(Rx++#s4:2)=Nt.new<br>
+let mayStore = 1, hasCtrlDep = 1,<br>
+ isPredicated = 1 in<br>
+def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
+ "if (!$src1.new) memw($src3++#$offset) = $src2.new",<br>
+ [],"$src3 = $dst">,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+<br>
+// if (Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1) memb(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STb_GP_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1) memb(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STb_GP_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1.new) memb(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memb(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STb_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1.new) memb(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STh_GP_cPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1) memh(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STh_GP_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1) memh(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STh_GP_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1.new) memh(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memh(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STh_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1.new) memh(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STw_GP_cPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1) memw(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1) memw(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if ($src1.new) memw(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+// if (!Pv) memw(##global) = Rt<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, IntRegs:$src2),<br>
+ "if (!$src1.new) memw(##$global) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrib_GP_cPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1) memb(##$global+$offset) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrib_GP_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1) memb(##$global+$offset) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrib_GP_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1.new) memb(##$global+$offset) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrib_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1.new) memb(##$global+$offset) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrih_GP_cPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1) memh(##$global+$offset) = $src2.new",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv.new) memw(Rs+Ru<<#u2)=Nt.new<br>
-let mayStore = 1, AddedComplexity = 10 in<br>
-def STriw_indexed_shl_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,<br>
- IntRegs:$src5),<br>
- "if (!$src1.new) memw($src2+$src3<<#$src4) = $src5.new",<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrih_GP_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1) memh(##$global+$offset) = $src2.new",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new<br>
-// if (Pv) memw(Rx++#s4:2)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
-def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
- "if ($src1) memw($src3++#$offset) = $src2.new",<br>
- [],"$src3 = $dst">,<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrih_GP_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1.new) memh(##$global+$offset) = $src2.new",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (Pv.new) memw(Rx++#s4:2)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
-def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
- "if ($src1.new) memw($src3++#$offset) = $src2.new",<br>
- [],"$src3 = $dst">,<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STrih_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1.new) memh(##$global+$offset) = $src2.new",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv) memw(Rx++#s4:2)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
-def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
- "if (!$src1) memw($src3++#$offset) = $src2.new",<br>
- [],"$src3 = $dst">,<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STriw_GP_cPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1) memw(##$global+$offset) = $src2.new",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
-// if (!Pv.new) memw(Rx++#s4:2)=Nt.new<br>
-let mayStore = 1, hasCtrlDep = 1 in<br>
-def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),<br>
- (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),<br>
- "if (!$src1.new) memw($src3++#$offset) = $src2.new",<br>
- [],"$src3 = $dst">,<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STriw_GP_cNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1) memw(##$global+$offset) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STriw_GP_cdnPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if ($src1.new) memw(##$global+$offset) = $src2.new",<br>
+ []>,<br>
Requires<[HasV4T]>;<br>
<br>
+let mayStore = 1, neverHasSideEffects = 1 in<br>
+def STriw_GP_cdnNotPt_nv_V4 : NVInst_V4<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$global, u16Imm:$offset,<br>
+ IntRegs:$src2),<br>
+ "if (!$src1.new) memw(##$global+$offset) = $src2.new",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// NV/ST -<br>
@@ -2416,16 +3990,18 @@<br>
def ADDr_ADDri_V4 : MInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),<br>
"$dst = add($src1, add($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (add IntRegs:$src1, (add IntRegs:$src2, s6ImmPred:$src3)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (i32 IntRegs:$src1), (add (i32 IntRegs:$src2),<br>
+ s6ImmPred:$src3)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rd=add(Rs,sub(#s6,Ru))<br>
def ADDr_SUBri_V4 : MInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),<br>
"$dst = add($src1, sub(#$src2, $src3))",<br>
- [(set IntRegs:$dst,<br>
- (add IntRegs:$src1, (sub s6ImmPred:$src2, IntRegs:$src3)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (i32 IntRegs:$src1), (sub s6ImmPred:$src2,<br>
+ (i32 IntRegs:$src3))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Generates the same instruction as ADDr_SUBri_V4 but matches different<br>
@@ -2434,8 +4010,9 @@<br>
def ADDri_SUBr_V4 : MInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),<br>
"$dst = add($src1, sub(#$src2, $src3))",<br>
- [(set IntRegs:$dst,<br>
- (sub (add IntRegs:$src1, s6ImmPred:$src2), IntRegs:$src3))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (sub (add (i32 IntRegs:$src1), s6ImmPred:$src2),<br>
+ (i32 IntRegs:$src3)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
<br>
@@ -2451,16 +4028,16 @@<br>
def ANDd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2),<br>
"$dst = and($src1, ~$src2)",<br>
- [(set DoubleRegs:$dst, (and DoubleRegs:$src1,<br>
- (not DoubleRegs:$src2)))]>,<br>
+ [(set (i64 DoubleRegs:$dst), (and (i64 DoubleRegs:$src1),<br>
+ (not (i64 DoubleRegs:$src2))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rdd=or(Rtt,~Rss)<br>
def ORd_NOTd_V4 : MInst<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2),<br>
"$dst = or($src1, ~$src2)",<br>
- [(set DoubleRegs:$dst,<br>
- (or DoubleRegs:$src1, (not DoubleRegs:$src2)))]>,<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (or (i64 DoubleRegs:$src1), (not (i64 DoubleRegs:$src2))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
<br>
@@ -2469,8 +4046,9 @@<br>
def XORd_XORdd: MInst_acc<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),<br>
"$dst ^= xor($src2, $src3)",<br>
- [(set DoubleRegs:$dst,<br>
- (xor DoubleRegs:$src1, (xor DoubleRegs:$src2, DoubleRegs:$src3)))],<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (xor (i64 DoubleRegs:$src1), (xor (i64 DoubleRegs:$src2),<br>
+ (i64 DoubleRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2480,8 +4058,9 @@<br>
def ORr_ANDri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),<br>
"$dst = or($src1, and($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ s10ImmPred:$src3)))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2490,8 +4069,9 @@<br>
def ANDr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst &= and($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (and IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2499,8 +4079,9 @@<br>
def ORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst |= and($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (or IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2508,8 +4089,9 @@<br>
def XORr_ANDrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst ^= and($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (xor IntRegs:$src1, (and IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2518,8 +4100,9 @@<br>
def ANDr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst &= and($src2, ~$src3)",<br>
- [(set IntRegs:$dst,<br>
- (and IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ (not (i32 IntRegs:$src3)))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2527,8 +4110,9 @@<br>
def ORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst |= and($src2, ~$src3)",<br>
- [(set IntRegs:$dst,<br>
- (or IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ (not (i32 IntRegs:$src3)))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2536,8 +4120,9 @@<br>
def XORr_ANDr_NOTr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst ^= and($src2, ~$src3)",<br>
- [(set IntRegs:$dst,<br>
- (xor IntRegs:$src1, (and IntRegs:$src2, (not IntRegs:$src3))))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (xor (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ (not (i32 IntRegs:$src3)))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2546,8 +4131,9 @@<br>
def ANDr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst &= or($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (and IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2555,8 +4141,9 @@<br>
def ORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst |= or($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (or IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2564,8 +4151,9 @@<br>
def XORr_ORrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst ^= or($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (xor IntRegs:$src1, (or IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (xor (i32 IntRegs:$src1), (or (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2574,8 +4162,9 @@<br>
def ANDr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst &= xor($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2583,8 +4172,9 @@<br>
def ORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst |= xor($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2592,8 +4182,9 @@<br>
def XORr_XORrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, IntRegs:$src3),<br>
"$dst ^= xor($src2, $src3)",<br>
- [(set IntRegs:$dst,<br>
- (and IntRegs:$src1, (xor IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (i32 IntRegs:$src1), (xor (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2601,8 +4192,9 @@<br>
def ORr_ANDri2_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),<br>
"$dst |= and($src2, #$src3)",<br>
- [(set IntRegs:$dst,<br>
- (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ s10ImmPred:$src3)))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2610,8 +4202,9 @@<br>
def ORr_ORri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs: $src2, s10Imm:$src3),<br>
"$dst |= or($src2, #$src3)",<br>
- [(set IntRegs:$dst,<br>
- (or IntRegs:$src1, (and IntRegs:$src2, s10ImmPred:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (i32 IntRegs:$src1), (and (i32 IntRegs:$src2),<br>
+ s10ImmPred:$src3)))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2663,8 +4256,9 @@<br>
def ADDi_MPYri_V4 : MInst<(outs IntRegs:$dst),<br>
(ins u6Imm:$src1, IntRegs:$src2, u6Imm:$src3),<br>
"$dst = add(#$src1, mpyi($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (add (mul IntRegs:$src2, u6ImmPred:$src3), u6ImmPred:$src1))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (mul (i32 IntRegs:$src2), u6ImmPred:$src3),<br>
+ u6ImmPred:$src1))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rd=add(#u6,mpyi(Rs,Rt))<br>
@@ -2672,32 +4266,36 @@<br>
def ADDi_MPYrr_V4 : MInst<(outs IntRegs:$dst),<br>
(ins u6Imm:$src1, IntRegs:$src2, IntRegs:$src3),<br>
"$dst = add(#$src1, mpyi($src2, $src3))",<br>
- [(set IntRegs:$dst,<br>
- (add (mul IntRegs:$src2, IntRegs:$src3), u6ImmPred:$src1))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (mul (i32 IntRegs:$src2), (i32 IntRegs:$src3)),<br>
+ u6ImmPred:$src1))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rd=add(Ru,mpyi(#u6:2,Rs))<br>
def ADDr_MPYir_V4 : MInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
"$dst = add($src1, mpyi(#$src2, $src3))",<br>
- [(set IntRegs:$dst,<br>
- (add IntRegs:$src1, (mul IntRegs:$src3, u6_2ImmPred:$src2)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src3),<br>
+ u6_2ImmPred:$src2)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rd=add(Ru,mpyi(Rs,#u6))<br>
def ADDr_MPYri_V4 : MInst<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, u6Imm:$src3),<br>
"$dst = add($src1, mpyi($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (add IntRegs:$src1, (mul IntRegs:$src2, u6ImmPred:$src3)))]>,<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),<br>
+ u6ImmPred:$src3)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Rx=add(Ru,mpyi(Rx,Rs))<br>
def ADDr_MPYrr_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),<br>
"$dst = add($src1, mpyi($src2, $src3))",<br>
- [(set IntRegs:$dst,<br>
- (add IntRegs:$src1, (mul IntRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (i32 IntRegs:$src1), (mul (i32 IntRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2745,8 +4343,9 @@<br>
def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = add(#$src1, asl($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (add (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2754,8 +4353,9 @@<br>
def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = add(#$src1, lsr($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (add (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2763,8 +4363,9 @@<br>
def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = sub(#$src1, asl($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (sub (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2772,8 +4373,9 @@<br>
def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = sub(#$src1, lsr($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (sub (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2783,8 +4385,9 @@<br>
def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = and(#$src1, asl($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (and (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2792,26 +4395,31 @@<br>
def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = and(#$src1, lsr($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (and (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
//Rx=or(#u8,asl(Rx,#U5))<br>
+let AddedComplexity = 30 in<br>
def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = or(#$src1, asl($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (or (shl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
//Rx=or(#u8,lsr(Rx,#U5))<br>
+let AddedComplexity = 30 in<br>
def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst),<br>
(ins u8Imm:$src1, IntRegs:$src2, u5Imm:$src3),<br>
"$dst = or(#$src1, lsr($src2, #$src3))",<br>
- [(set IntRegs:$dst,<br>
- (or (srl IntRegs:$src2, u5ImmPred:$src3), u8ImmPred:$src1))],<br>
+ [(set (i32 IntRegs:$dst),<br>
+ (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3),<br>
+ u8ImmPred:$src1))],<br>
"$src2 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2820,7 +4428,8 @@<br>
//Rd=lsl(#s6,Rt)<br>
def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2),<br>
"$dst = lsl(#$src1, $src2)",<br>
- [(set IntRegs:$dst, (shl s6ImmPred:$src1, IntRegs:$src2))]>,<br>
+ [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1,<br>
+ (i32 IntRegs:$src2)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
<br>
@@ -2829,8 +4438,9 @@<br>
def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br>
"$dst ^= asl($src2, $src3)",<br>
- [(set DoubleRegs:$dst,<br>
- (xor DoubleRegs:$src1, (shl DoubleRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2838,8 +4448,9 @@<br>
def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br>
"$dst ^= asr($src2, $src3)",<br>
- [(set DoubleRegs:$dst,<br>
- (xor DoubleRegs:$src1, (sra DoubleRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2847,8 +4458,9 @@<br>
def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br>
"$dst ^= lsl($src2, $src3)",<br>
- [(set DoubleRegs:$dst,<br>
- (xor DoubleRegs:$src1, (shl DoubleRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1),<br>
+ (shl (i64 DoubleRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2856,8 +4468,9 @@<br>
def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst),<br>
(ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),<br>
"$dst ^= lsr($src2, $src3)",<br>
- [(set DoubleRegs:$dst,<br>
- (xor DoubleRegs:$src1, (srl DoubleRegs:$src2, IntRegs:$src3)))],<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2),<br>
+ (i32 IntRegs:$src3))))],<br>
"$src1 = $dst">,<br>
Requires<[HasV4T]>;<br>
<br>
@@ -2903,16 +4516,16 @@<br>
def MEMw_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, m6Imm:$addend),<br>
"Error; should not emit",<br>
- [(store (add (load (add IntRegs:$base, u6_2ImmPred:$offset)),<br>
-m6ImmPred:$addend),<br>
- (add IntRegs:$base, u6_2ImmPred:$offset))]>,<br>
+ [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),<br>
+ m6ImmPred:$addend),<br>
+ (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memw(Rs+#u6:2) += #U5<br>
let AddedComplexity = 30 in<br>
def MEMw_ADDi_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$addend),<br>
- "memw($base+#$offset) += $addend",<br>
+ "memw($base+#$offset) += #$addend",<br>
[]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
@@ -2920,7 +4533,7 @@<br>
let AddedComplexity = 30 in<br>
def MEMw_SUBi_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, u5Imm:$subend),<br>
- "memw($base+#$offset) -= $subend",<br>
+ "memw($base+#$offset) -= #$subend",<br>
[]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
@@ -2929,9 +4542,9 @@<br>
def MEMw_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$addend),<br>
"memw($base+#$offset) += $addend",<br>
- [(store (add (load (add IntRegs:$base, u6_2ImmPred:$offset)),<br>
-IntRegs:$addend),<br>
- (add IntRegs:$base, u6_2ImmPred:$offset))]>,<br>
+ [(store (add (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),<br>
+ (i32 IntRegs:$addend)),<br>
+ (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memw(Rs+#u6:2) -= Rt<br>
@@ -2939,19 +4552,19 @@<br>
def MEMw_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$subend),<br>
"memw($base+#$offset) -= $subend",<br>
- [(store (sub (load (add IntRegs:$base, u6_2ImmPred:$offset)),<br>
-IntRegs:$subend),<br>
- (add IntRegs:$base, u6_2ImmPred:$offset))]>,<br>
+ [(store (sub (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),<br>
+ (i32 IntRegs:$subend)),<br>
+ (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memw(Rs+#u6:2) &= Rt<br>
let AddedComplexity = 30 in<br>
def MEMw_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$andend),<br>
- "memw($base+#$offset) += $andend",<br>
- [(store (and (load (add IntRegs:$base, u6_2ImmPred:$offset)),<br>
-IntRegs:$andend),<br>
- (add IntRegs:$base, u6_2ImmPred:$offset))]>,<br>
+ "memw($base+#$offset) &= $andend",<br>
+ [(store (and (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),<br>
+ (i32 IntRegs:$andend)),<br>
+ (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memw(Rs+#u6:2) |= Rt<br>
@@ -2959,9 +4572,9 @@<br>
def MEMw_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_2Imm:$offset, IntRegs:$orend),<br>
"memw($base+#$offset) |= $orend",<br>
- [(store (or (load (add IntRegs:$base, u6_2ImmPred:$offset)),<br>
- IntRegs:$orend),<br>
- (add IntRegs:$base, u6_2ImmPred:$offset))]>,<br>
+ [(store (or (load (add (i32 IntRegs:$base), u6_2ImmPred:$offset)),<br>
+ (i32 IntRegs:$orend)),<br>
+ (add (i32 IntRegs:$base), u6_2ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// MEMw_ADDSUBi_V4:<br>
@@ -2996,7 +4609,7 @@<br>
def MEMw_ADDr_MEM_V4 : MEMInst_V4<(outs),<br>
(ins MEMri:$addr, IntRegs:$addend),<br>
"memw($addr) += $addend",<br>
- [(store (add (load ADDRriU6_2:$addr), IntRegs:$addend),<br>
+ [(store (add (load ADDRriU6_2:$addr), (i32 IntRegs:$addend)),<br>
ADDRriU6_2:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
@@ -3005,7 +4618,7 @@<br>
def MEMw_SUBr_MEM_V4 : MEMInst_V4<(outs),<br>
(ins MEMri:$addr, IntRegs:$subend),<br>
"memw($addr) -= $subend",<br>
- [(store (sub (load ADDRriU6_2:$addr), IntRegs:$subend),<br>
+ [(store (sub (load ADDRriU6_2:$addr), (i32 IntRegs:$subend)),<br>
ADDRriU6_2:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
@@ -3014,7 +4627,7 @@<br>
def MEMw_ANDr_MEM_V4 : MEMInst_V4<(outs),<br>
(ins MEMri:$addr, IntRegs:$andend),<br>
"memw($addr) &= $andend",<br>
- [(store (and (load ADDRriU6_2:$addr), IntRegs:$andend),<br>
+ [(store (and (load ADDRriU6_2:$addr), (i32 IntRegs:$andend)),<br>
ADDRriU6_2:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
@@ -3023,8 +4636,8 @@<br>
def MEMw_ORr_MEM_V4 : MEMInst_V4<(outs),<br>
(ins MEMri:$addr, IntRegs:$orend),<br>
"memw($addr) |= $orend",<br>
- [(store (or (load ADDRriU6_2:$addr), IntRegs:$orend),<br>
-ADDRriU6_2:$addr)]>,<br>
+ [(store (or (load ADDRriU6_2:$addr), (i32 IntRegs:$orend)),<br>
+ ADDRriU6_2:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
@@ -3060,10 +4673,10 @@<br>
def MEMh_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_1Imm:$offset, m6Imm:$addend),<br>
"Error; should not emit",<br>
- [(truncstorei16 (add (sextloadi16 (add IntRegs:$base,<br>
+ [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),<br>
u6_1ImmPred:$offset)),<br>
m6ImmPred:$addend),<br>
- (add IntRegs:$base, u6_1ImmPred:$offset))]>,<br>
+ (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) += #U5<br>
@@ -3087,10 +4700,10 @@<br>
def MEMh_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$addend),<br>
"memh($base+#$offset) += $addend",<br>
- [(truncstorei16 (add (sextloadi16 (add IntRegs:$base,<br>
+ [(truncstorei16 (add (sextloadi16 (add (i32 IntRegs:$base),<br>
u6_1ImmPred:$offset)),<br>
- IntRegs:$addend),<br>
- (add IntRegs:$base, u6_1ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$addend)),<br>
+ (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) -= Rt<br>
@@ -3098,10 +4711,10 @@<br>
def MEMh_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$subend),<br>
"memh($base+#$offset) -= $subend",<br>
- [(truncstorei16 (sub (sextloadi16 (add IntRegs:$base,<br>
+ [(truncstorei16 (sub (sextloadi16 (add (i32 IntRegs:$base),<br>
u6_1ImmPred:$offset)),<br>
- IntRegs:$subend),<br>
- (add IntRegs:$base, u6_1ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$subend)),<br>
+ (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) &= Rt<br>
@@ -3109,10 +4722,10 @@<br>
def MEMh_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$andend),<br>
"memh($base+#$offset) += $andend",<br>
- [(truncstorei16 (and (sextloadi16 (add IntRegs:$base,<br>
+ [(truncstorei16 (and (sextloadi16 (add (i32 IntRegs:$base),<br>
u6_1ImmPred:$offset)),<br>
- IntRegs:$andend),<br>
- (add IntRegs:$base, u6_1ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$andend)),<br>
+ (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) |= Rt<br>
@@ -3120,10 +4733,10 @@<br>
def MEMh_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_1Imm:$offset, IntRegs:$orend),<br>
"memh($base+#$offset) |= $orend",<br>
- [(truncstorei16 (or (sextloadi16 (add IntRegs:$base,<br>
+ [(truncstorei16 (or (sextloadi16 (add (i32 IntRegs:$base),<br>
u6_1ImmPred:$offset)),<br>
- IntRegs:$orend),<br>
- (add IntRegs:$base, u6_1ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$orend)),<br>
+ (add (i32 IntRegs:$base), u6_1ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// MEMh_ADDSUBi_V4:<br>
@@ -3159,7 +4772,7 @@<br>
(ins MEMri:$addr, IntRegs:$addend),<br>
"memh($addr) += $addend",<br>
[(truncstorei16 (add (sextloadi16 ADDRriU6_1:$addr),<br>
- IntRegs:$addend), ADDRriU6_1:$addr)]>,<br>
+ (i32 IntRegs:$addend)), ADDRriU6_1:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) -= Rt<br>
@@ -3168,7 +4781,7 @@<br>
(ins MEMri:$addr, IntRegs:$subend),<br>
"memh($addr) -= $subend",<br>
[(truncstorei16 (sub (sextloadi16 ADDRriU6_1:$addr),<br>
- IntRegs:$subend), ADDRriU6_1:$addr)]>,<br>
+ (i32 IntRegs:$subend)), ADDRriU6_1:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) &= Rt<br>
@@ -3177,7 +4790,7 @@<br>
(ins MEMri:$addr, IntRegs:$andend),<br>
"memh($addr) &= $andend",<br>
[(truncstorei16 (and (sextloadi16 ADDRriU6_1:$addr),<br>
- IntRegs:$andend), ADDRriU6_1:$addr)]>,<br>
+ (i32 IntRegs:$andend)), ADDRriU6_1:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memh(Rs+#u6:1) |= Rt<br>
@@ -3186,7 +4799,7 @@<br>
(ins MEMri:$addr, IntRegs:$orend),<br>
"memh($addr) |= $orend",<br>
[(truncstorei16 (or (sextloadi16 ADDRriU6_1:$addr),<br>
- IntRegs:$orend), ADDRriU6_1:$addr)]>,<br>
+ (i32 IntRegs:$orend)), ADDRriU6_1:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
<br>
@@ -3223,10 +4836,10 @@<br>
def MEMb_ADDSUBi_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_0Imm:$offset, m6Imm:$addend),<br>
"Error; should not emit",<br>
- [(truncstorei8 (add (sextloadi8 (add IntRegs:$base,<br>
+ [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),<br>
u6_0ImmPred:$offset)),<br>
m6ImmPred:$addend),<br>
- (add IntRegs:$base, u6_0ImmPred:$offset))]>,<br>
+ (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) += #U5<br>
@@ -3250,10 +4863,10 @@<br>
def MEMb_ADDr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$addend),<br>
"memb($base+#$offset) += $addend",<br>
- [(truncstorei8 (add (sextloadi8 (add IntRegs:$base,<br>
+ [(truncstorei8 (add (sextloadi8 (add (i32 IntRegs:$base),<br>
u6_0ImmPred:$offset)),<br>
- IntRegs:$addend),<br>
- (add IntRegs:$base, u6_0ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$addend)),<br>
+ (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) -= Rt<br>
@@ -3261,10 +4874,10 @@<br>
def MEMb_SUBr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$subend),<br>
"memb($base+#$offset) -= $subend",<br>
- [(truncstorei8 (sub (sextloadi8 (add IntRegs:$base,<br>
+ [(truncstorei8 (sub (sextloadi8 (add (i32 IntRegs:$base),<br>
u6_0ImmPred:$offset)),<br>
- IntRegs:$subend),<br>
- (add IntRegs:$base, u6_0ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$subend)),<br>
+ (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) &= Rt<br>
@@ -3272,10 +4885,10 @@<br>
def MEMb_ANDr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$andend),<br>
"memb($base+#$offset) += $andend",<br>
- [(truncstorei8 (and (sextloadi8 (add IntRegs:$base,<br>
+ [(truncstorei8 (and (sextloadi8 (add (i32 IntRegs:$base),<br>
u6_0ImmPred:$offset)),<br>
- IntRegs:$andend),<br>
- (add IntRegs:$base, u6_0ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$andend)),<br>
+ (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) |= Rt<br>
@@ -3283,10 +4896,10 @@<br>
def MEMb_ORr_indexed_MEM_V4 : MEMInst_V4<(outs),<br>
(ins IntRegs:$base, u6_0Imm:$offset, IntRegs:$orend),<br>
"memb($base+#$offset) |= $orend",<br>
- [(truncstorei8 (or (sextloadi8 (add IntRegs:$base,<br>
+ [(truncstorei8 (or (sextloadi8 (add (i32 IntRegs:$base),<br>
u6_0ImmPred:$offset)),<br>
- IntRegs:$orend),<br>
- (add IntRegs:$base, u6_0ImmPred:$offset))]>,<br>
+ (i32 IntRegs:$orend)),<br>
+ (add (i32 IntRegs:$base), u6_0ImmPred:$offset))]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// MEMb_ADDSUBi_V4:<br>
@@ -3322,7 +4935,7 @@<br>
(ins MEMri:$addr, IntRegs:$addend),<br>
"memb($addr) += $addend",<br>
[(truncstorei8 (add (sextloadi8 ADDRriU6_0:$addr),<br>
- IntRegs:$addend), ADDRriU6_0:$addr)]>,<br>
+ (i32 IntRegs:$addend)), ADDRriU6_0:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) -= Rt<br>
@@ -3331,7 +4944,7 @@<br>
(ins MEMri:$addr, IntRegs:$subend),<br>
"memb($addr) -= $subend",<br>
[(truncstorei8 (sub (sextloadi8 ADDRriU6_0:$addr),<br>
- IntRegs:$subend), ADDRriU6_0:$addr)]>,<br>
+ (i32 IntRegs:$subend)), ADDRriU6_0:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) &= Rt<br>
@@ -3340,7 +4953,7 @@<br>
(ins MEMri:$addr, IntRegs:$andend),<br>
"memb($addr) &= $andend",<br>
[(truncstorei8 (and (sextloadi8 ADDRriU6_0:$addr),<br>
- IntRegs:$andend), ADDRriU6_0:$addr)]>,<br>
+ (i32 IntRegs:$andend)), ADDRriU6_0:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
// memb(Rs+#u6:0) |= Rt<br>
@@ -3349,7 +4962,7 @@<br>
(ins MEMri:$addr, IntRegs:$orend),<br>
"memb($addr) |= $orend",<br>
[(truncstorei8 (or (sextloadi8 ADDRriU6_0:$addr),<br>
- IntRegs:$orend), ADDRriU6_0:$addr)]>,<br>
+ (i32 IntRegs:$orend)), ADDRriU6_0:$addr)]>,<br>
Requires<[HasV4T, UseMEMOP]>;<br>
<br>
<br>
@@ -3364,13 +4977,16 @@<br>
// The implemented patterns are: EQ/GT/GTU.<br>
// Missing patterns are: GE/GEU/LT/LTU/LE/LEU.<br>
<br>
+// Following instruction is not being extended as it results into the<br>
+// incorrect code for negative numbers.<br>
// Pd=cmpb.eq(Rs,#u8)<br>
+<br>
let isCompare = 1 in<br>
def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, u8Imm:$src2),<br>
"$dst = cmpb.eq($src1, #$src2)",<br>
- [(set PredRegs:$dst, (seteq (and IntRegs:$src1, 255),<br>
- u8ImmPred:$src2))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (seteq (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Pd=cmpb.eq(Rs,Rt)<br>
@@ -3378,10 +4994,9 @@<br>
def CMPbEQrr_ubub_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = cmpb.eq($src1, $src2)",<br>
- [(set PredRegs:$dst, (seteq (and (xor IntRegs:$src1,<br>
- IntRegs:$src2),<br>
- 255),<br>
- 0))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (seteq (and (xor (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)), 255), 0))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Pd=cmpb.eq(Rs,Rt)<br>
@@ -3389,26 +5004,31 @@<br>
def CMPbEQrr_sbsb_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = cmpb.eq($src1, $src2)",<br>
- [(set PredRegs:$dst, (seteq (shl IntRegs:$src1, (i32 24)),<br>
- (shl IntRegs:$src2, (i32 24))))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (seteq (shl (i32 IntRegs:$src1), (i32 24)),<br>
+ (shl (i32 IntRegs:$src2), (i32 24))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
+/* Incorrect Pattern -- immediate should be right shifted before being<br>
+used in the <a href="http://cmpb.gt" target="_blank">cmpb.gt</a> instruction.<br>
// Pd=<a href="http://cmpb.gt" target="_blank">cmpb.gt</a>(Rs,#s8)<br>
let isCompare = 1 in<br>
def CMPbGTri_V4 : MInst<(outs PredRegs:$dst),<br>
- (ins IntRegs:$src1, s32Imm:$src2),<br>
+ (ins IntRegs:$src1, s8Imm:$src2),<br>
"$dst = <a href="http://cmpb.gt" target="_blank">cmpb.gt</a>($src1, #$src2)",<br>
- [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 24)),<br>
- s32_24ImmPred:$src2))]>,<br>
+ [(set (i1 PredRegs:$dst), (setgt (shl (i32 IntRegs:$src1), (i32 24)),<br>
+ s8ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
+*/<br>
<br>
// Pd=<a href="http://cmpb.gt" target="_blank">cmpb.gt</a>(Rs,Rt)<br>
let isCompare = 1 in<br>
def CMPbGTrr_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = <a href="http://cmpb.gt" target="_blank">cmpb.gt</a>($src1, $src2)",<br>
- [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 24)),<br>
- (shl IntRegs:$src2, (i32 24))))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (setgt (shl (i32 IntRegs:$src1), (i32 24)),<br>
+ (shl (i32 IntRegs:$src2), (i32 24))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Pd=cmpb.gtu(Rs,#u7)<br>
@@ -3416,8 +5036,8 @@<br>
def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, u7Imm:$src2),<br>
"$dst = cmpb.gtu($src1, #$src2)",<br>
- [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 255),<br>
- u7ImmPred:$src2))]>,<br>
+ [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),<br>
+ u7ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Pd=cmpb.gtu(Rs,Rt)<br>
@@ -3425,18 +5045,21 @@<br>
def CMPbGTUrr_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = cmpb.gtu($src1, $src2)",<br>
- [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 255),<br>
- (and IntRegs:$src2, 255)))]>,<br>
+ [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 255),<br>
+ (and (i32 IntRegs:$src2), 255)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
+// Following instruction is not being extended as it results into the incorrect<br>
+// code for negative numbers.<br>
+<br>
// Signed half compare(.eq) ri.<br>
// Pd=cmph.eq(Rs,#s8)<br>
let isCompare = 1 in<br>
def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),<br>
- (ins IntRegs:$src1, u16Imm:$src2),<br>
+ (ins IntRegs:$src1, s8Imm:$src2),<br>
"$dst = cmph.eq($src1, #$src2)",<br>
- [(set PredRegs:$dst, (seteq (and IntRegs:$src1, 65535),<br>
- u16_s8ImmPred:$src2))]>,<br>
+ [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),<br>
+ s8ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Signed half compare(.eq) rr.<br>
@@ -3449,10 +5072,9 @@<br>
def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = cmph.eq($src1, $src2)",<br>
- [(set PredRegs:$dst, (seteq (and (xor IntRegs:$src1,<br>
- IntRegs:$src2),<br>
- 65535),<br>
- 0))]>,<br>
+ [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),<br>
+ (i32 IntRegs:$src2)),<br>
+ 65535), 0))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Signed half compare(.eq) rr.<br>
@@ -3465,19 +5087,25 @@<br>
def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = cmph.eq($src1, $src2)",<br>
- [(set PredRegs:$dst, (seteq (shl IntRegs:$src1, (i32 16)),<br>
- (shl IntRegs:$src2, (i32 16))))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (seteq (shl (i32 IntRegs:$src1), (i32 16)),<br>
+ (shl (i32 IntRegs:$src2), (i32 16))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
+/* Incorrect Pattern -- immediate should be right shifted before being<br>
+used in the <a href="http://cmph.gt" target="_blank">cmph.gt</a> instruction.<br>
// Signed half compare(.gt) ri.<br>
// Pd=<a href="http://cmph.gt" target="_blank">cmph.gt</a>(Rs,#s8)<br>
+<br>
let isCompare = 1 in<br>
def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),<br>
- (ins IntRegs:$src1, s32Imm:$src2),<br>
+ (ins IntRegs:$src1, s8Imm:$src2),<br>
"$dst = <a href="http://cmph.gt" target="_blank">cmph.gt</a>($src1, #$src2)",<br>
- [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 16)),<br>
- s32_16s8ImmPred:$src2))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (setgt (shl (i32 IntRegs:$src1), (i32 16)),<br>
+ s8ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
+*/<br>
<br>
// Signed half compare(.gt) rr.<br>
// Pd=<a href="http://cmph.gt" target="_blank">cmph.gt</a>(Rs,Rt)<br>
@@ -3485,8 +5113,9 @@<br>
def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = <a href="http://cmph.gt" target="_blank">cmph.gt</a>($src1, $src2)",<br>
- [(set PredRegs:$dst, (setgt (shl IntRegs:$src1, (i32 16)),<br>
- (shl IntRegs:$src2, (i32 16))))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (setgt (shl (i32 IntRegs:$src1), (i32 16)),<br>
+ (shl (i32 IntRegs:$src2), (i32 16))))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Unsigned half compare rr (.gtu).<br>
@@ -3495,8 +5124,9 @@<br>
def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, IntRegs:$src2),<br>
"$dst = cmph.gtu($src1, $src2)",<br>
- [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 65535),<br>
- (and IntRegs:$src2, 65535)))]>,<br>
+ [(set (i1 PredRegs:$dst),<br>
+ (setugt (and (i32 IntRegs:$src1), 65535),<br>
+ (and (i32 IntRegs:$src2), 65535)))]>,<br>
Requires<[HasV4T]>;<br>
<br>
// Unsigned half compare ri (.gtu).<br>
@@ -3505,8 +5135,8 @@<br>
def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),<br>
(ins IntRegs:$src1, u7Imm:$src2),<br>
"$dst = cmph.gtu($src1, #$src2)",<br>
- [(set PredRegs:$dst, (setugt (and IntRegs:$src1, 65535),<br>
- u7ImmPred:$src2))]>,<br>
+ [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),<br>
+ u7ImmPred:$src2))]>,<br>
Requires<[HasV4T]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
@@ -3523,9 +5153,37 @@<br>
Requires<[HasV4T]>;<br>
}<br>
<br>
+// Restore registers and dealloc return function call.<br>
+let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,<br>
+ Defs = [R29, R30, R31, PC] in {<br>
+ def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs), (ins calltarget:$dst, variable_ops),<br>
+ "jump $dst // Restore_and_dealloc_return",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+// Restore registers and dealloc frame before a tail call.<br>
+let isCall = 1, isBarrier = 1,<br>
+ Defs = [R29, R30, R31, PC] in {<br>
+ def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs), (ins calltarget:$dst, variable_ops),<br>
+ "call $dst // Restore_and_dealloc_before_tailcall",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+// Save registers function call.<br>
+let isCall = 1, isBarrier = 1,<br>
+ Uses = [R29, R31] in {<br>
+ def SAVE_REGISTERS_CALL_V4 : JInst<(outs), (ins calltarget:$dst, variable_ops),<br>
+ "call $dst // Save_calle_saved_registers",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
// if (Ps) dealloc_return<br>
let isReturn = 1, isTerminator = 1,<br>
- Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {<br>
+ Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,<br>
+ isPredicated = 1 in {<br>
def DEALLOC_RET_cPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1, i32imm:$amt1),<br>
"if ($src1) dealloc_return",<br>
[]>,<br>
@@ -3534,7 +5192,8 @@<br>
<br>
// if (!Ps) dealloc_return<br>
let isReturn = 1, isTerminator = 1,<br>
- Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {<br>
+ Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,<br>
+ isPredicated = 1 in {<br>
def DEALLOC_RET_cNotPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,<br>
i32imm:$amt1),<br>
"if (!$src1) dealloc_return",<br>
@@ -3544,7 +5203,8 @@<br>
<br>
// if (Ps.new) dealloc_return:nt<br>
let isReturn = 1, isTerminator = 1,<br>
- Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {<br>
+ Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,<br>
+ isPredicated = 1 in {<br>
def DEALLOC_RET_cdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,<br>
i32imm:$amt1),<br>
"if ($src1.new) dealloc_return:nt",<br>
@@ -3554,7 +5214,8 @@<br>
<br>
// if (!Ps.new) dealloc_return:nt<br>
let isReturn = 1, isTerminator = 1,<br>
- Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {<br>
+ Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,<br>
+ isPredicated = 1 in {<br>
def DEALLOC_RET_cNotdnPnt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,<br>
i32imm:$amt1),<br>
"if (!$src1.new) dealloc_return:nt",<br>
@@ -3564,7 +5225,8 @@<br>
<br>
// if (Ps.new) dealloc_return:t<br>
let isReturn = 1, isTerminator = 1,<br>
- Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {<br>
+ Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,<br>
+ isPredicated = 1 in {<br>
def DEALLOC_RET_cdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,<br>
i32imm:$amt1),<br>
"if ($src1.new) dealloc_return:t",<br>
@@ -3574,10 +5236,511 @@<br>
<br>
// if (!Ps.new) dealloc_return:nt<br>
let isReturn = 1, isTerminator = 1,<br>
- Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1 in {<br>
+ Defs = [R29, R30, R31, PC], Uses = [R29, R31], neverHasSideEffects = 1,<br>
+ isPredicated = 1 in {<br>
def DEALLOC_RET_cNotdnPt_V4 : NVInst_V4<(outs), (ins PredRegs:$src1,<br>
i32imm:$amt1),<br>
"if (!$src1.new) dealloc_return:t",<br>
[]>,<br>
Requires<[HasV4T]>;<br>
}<br>
+<br>
+<br>
+// Load/Store with absolute addressing mode<br>
+// memw(#u6)=Rt<br>
+<br>
+multiclass ST_abs<string OpcStr> {<br>
+ let isPredicable = 1 in<br>
+ def _abs_V4 : STInst<(outs),<br>
+ (ins globaladdress:$absaddr, IntRegs:$src),<br>
+ !strconcat(OpcStr, "(##$absaddr) = $src"),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if ($src1)", !strconcat(OpcStr, "(##$absaddr) = $src2")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if (!$src1)", !strconcat(OpcStr, "(##$absaddr) = $src2")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if ($src1.new)", !strconcat(OpcStr, "(##$absaddr) = $src2")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if (!$src1.new)", !strconcat(OpcStr, "(##$absaddr) = $src2")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ def _abs_nv_V4 : STInst<(outs),<br>
+ (ins globaladdress:$absaddr, IntRegs:$src),<br>
+ !strconcat(OpcStr, "(##$absaddr) = $src.new"),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if ($src1)", !strconcat(OpcStr, "(##$absaddr) = $src2.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cNotPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if (!$src1)", !strconcat(OpcStr, "(##$absaddr) = $src2.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if ($src1.new)", !strconcat(OpcStr, "(##$absaddr) = $src2.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnNotPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, IntRegs:$src2),<br>
+ !strconcat("if (!$src1.new)", !strconcat(OpcStr, "(##$absaddr) = $src2.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+let AddedComplexity = 30, isPredicable = 1 in<br>
+def STrid_abs_V4 : STInst<(outs),<br>
+ (ins globaladdress:$absaddr, DoubleRegs:$src),<br>
+ "memd(##$absaddr) = $src",<br>
+ [(store (i64 DoubleRegs:$src), (HexagonCONST32 tglobaladdr:$absaddr))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def STrid_abs_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),<br>
+ "if ($src1) memd(##$absaddr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def STrid_abs_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),<br>
+ "if (!$src1) memd(##$absaddr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def STrid_abs_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),<br>
+ "if ($src1.new) memd(##$absaddr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def STrid_abs_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr, DoubleRegs:$src2),<br>
+ "if (!$src1.new) memd(##$absaddr) = $src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+defm STrib : ST_abs<"memb">;<br>
+defm STrih : ST_abs<"memh">;<br>
+defm STriw : ST_abs<"memw">;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(truncstorei8 (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),<br>
+ (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(truncstorei16 (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),<br>
+ (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),<br>
+ (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;<br>
+<br>
+<br>
+multiclass LD_abs<string OpcStr> {<br>
+ let isPredicable = 1 in<br>
+ def _abs_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins globaladdress:$absaddr),<br>
+ !strconcat("$dst = ", !strconcat(OpcStr, "(##$absaddr)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ !strconcat("if ($src1) $dst = ", !strconcat(OpcStr, "(##$absaddr)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ !strconcat("if (!$src1) $dst = ", !strconcat(OpcStr, "(##$absaddr)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ !strconcat("if ($src1.new) $dst = ", !strconcat(OpcStr, "(##$absaddr)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ !strconcat("if (!$src1.new) $dst = ", !strconcat(OpcStr, "(##$absaddr)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+let AddedComplexity = 30 in<br>
+def LDrid_abs_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins globaladdress:$absaddr),<br>
+ "$dst = memd(##$absaddr)",<br>
+ [(set (i64 DoubleRegs:$dst), (load (HexagonCONST32 tglobaladdr:$absaddr)))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def LDrid_abs_cPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ "if ($src1) $dst = memd(##$absaddr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def LDrid_abs_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ "if (!$src1) $dst = memd(##$absaddr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def LDrid_abs_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ "if ($src1.new) $dst = memd(##$absaddr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 30, isPredicated = 1 in<br>
+def LDrid_abs_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$absaddr),<br>
+ "if (!$src1.new) $dst = memd(##$absaddr)",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+defm LDrib : LD_abs<"memb">;<br>
+defm LDriub : LD_abs<"memub">;<br>
+defm LDrih : LD_abs<"memh">;<br>
+defm LDriuh : LD_abs<"memuh">;<br>
+defm LDriw : LD_abs<"memw">;<br>
+<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),<br>
+ (LDriw_abs_V4 tglobaladdr: $absaddr)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),<br>
+ (LDrib_abs_V4 tglobaladdr:$absaddr)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),<br>
+ (LDriub_abs_V4 tglobaladdr:$absaddr)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),<br>
+ (LDrih_abs_V4 tglobaladdr:$absaddr)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),<br>
+ (LDriuh_abs_V4 tglobaladdr:$absaddr)>;<br>
+<br>
+// Transfer global address into a register<br>
+let AddedComplexity=50, isMoveImm = 1, isReMaterializable = 1 in<br>
+def TFRI_V4 : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$src1),<br>
+ "$dst = ##$src1",<br>
+ [(set IntRegs:$dst, (HexagonCONST32 tglobaladdr:$src1))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$src2),<br>
+ "if($src1) $dst = ##$src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$src2),<br>
+ "if(!$src1) $dst = ##$src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$src2),<br>
+ "if($src1.new) $dst = ##$src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity=50, neverHasSideEffects = 1, isPredicated = 1 in<br>
+def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, globaladdress:$src2),<br>
+ "if(!$src1.new) $dst = ##$src2",<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 50, Predicates = [HasV4T] in<br>
+def : Pat<(HexagonCONST32_GP tglobaladdr:$src1),<br>
+ (TFRI_V4 tglobaladdr:$src1)>;<br>
+<br>
+<br>
+// Load - Indirect with long offset: These instructions take global address<br>
+// as an operand<br>
+let AddedComplexity = 10 in<br>
+def LDrid_ind_lo_V4 : LDInst<(outs DoubleRegs:$dst),<br>
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),<br>
+ "$dst=memd($src1<<#$src2+##$offset)",<br>
+ [(set (i64 DoubleRegs:$dst),<br>
+ (load (add (shl IntRegs:$src1, u2ImmPred:$src2),<br>
+ (HexagonCONST32 tglobaladdr:$offset))))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 10 in<br>
+multiclass LD_indirect_lo<string OpcStr, PatFrag OpNode> {<br>
+ def _lo_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$offset),<br>
+ !strconcat("$dst = ", !strconcat(OpcStr, "($src1<<#$src2+##$offset)")),<br>
+ [(set IntRegs:$dst,<br>
+ (i32 (OpNode (add (shl IntRegs:$src1, u2ImmPred:$src2),<br>
+ (HexagonCONST32 tglobaladdr:$offset)))))]>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+defm LDrib_ind : LD_indirect_lo<"memb", sextloadi8>;<br>
+defm LDriub_ind : LD_indirect_lo<"memub", zextloadi8>;<br>
+defm LDrih_ind : LD_indirect_lo<"memh", sextloadi16>;<br>
+defm LDriuh_ind : LD_indirect_lo<"memuh", zextloadi16>;<br>
+defm LDriw_ind : LD_indirect_lo<"memw", load>;<br>
+<br>
+// Store - Indirect with long offset: These instructions take global address<br>
+// as an operand<br>
+let AddedComplexity = 10 in<br>
+def STrid_ind_lo_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,<br>
+ DoubleRegs:$src4),<br>
+ "memd($src1<<#$src2+#$src3) = $src4",<br>
+ [(store (i64 DoubleRegs:$src4),<br>
+ (add (shl IntRegs:$src1, u2ImmPred:$src2),<br>
+ (HexagonCONST32 tglobaladdr:$src3)))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+let AddedComplexity = 10 in<br>
+multiclass ST_indirect_lo<string OpcStr, PatFrag OpNode> {<br>
+ def _lo_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u2Imm:$src2, globaladdress:$src3,<br>
+ IntRegs:$src4),<br>
+ !strconcat(OpcStr, "($src1<<#$src2+##$src3) = $src4"),<br>
+ [(OpNode (i32 IntRegs:$src4),<br>
+ (add (shl IntRegs:$src1, u2ImmPred:$src2),<br>
+ (HexagonCONST32 tglobaladdr:$src3)))]>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+defm STrib_ind : ST_indirect_lo<"memb", truncstorei8>;<br>
+defm STrih_ind : ST_indirect_lo<"memh", truncstorei16>;<br>
+defm STriw_ind : ST_indirect_lo<"memw", store>;<br>
+<br>
+// Store - absolute addressing mode: These instruction take constant<br>
+// value as the extended operand<br>
+multiclass ST_absimm<string OpcStr> {<br>
+ let isPredicable = 1 in<br>
+ def _abs_V4 : STInst<(outs),<br>
+ (ins u6Imm:$src1, IntRegs:$src2),<br>
+ !strconcat(OpcStr, "(#$src1) = $src2"),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if ($src1.new)", !strconcat(OpcStr, "(#$src2) = $src3")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnNotPt_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if (!$src1.new)", !strconcat(OpcStr, "(#$src2) = $src3")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ def _abs_nv_V4 : STInst<(outs),<br>
+ (ins u6Imm:$src1, IntRegs:$src2),<br>
+ !strconcat(OpcStr, "(#$src1) = $src2.new"),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if ($src1)", !strconcat(OpcStr, "(#$src2) = $src3.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cNotPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if (!$src1)", !strconcat(OpcStr, "(#$src2) = $src3.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if ($src1.new)", !strconcat(OpcStr, "(#$src2) = $src3.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnNotPt_nv_V4 : STInst<(outs),<br>
+ (ins PredRegs:$src1, u6Imm:$src2, IntRegs:$src3),<br>
+ !strconcat("if (!$src1.new)", !strconcat(OpcStr, "(#$src2) = $src3.new")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+defm STrib_imm : ST_absimm<"memb">;<br>
+defm STrih_imm : ST_absimm<"memh">;<br>
+defm STriw_imm : ST_absimm<"memw">;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(truncstorei8 (i32 IntRegs:$src1), u6ImmPred:$src2),<br>
+ (STrib_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(truncstorei16 (i32 IntRegs:$src1), u6ImmPred:$src2),<br>
+ (STrih_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(store (i32 IntRegs:$src1), u6ImmPred:$src2),<br>
+ (STriw_imm_abs_V4 u6ImmPred:$src2, IntRegs: $src1)>;<br>
+<br>
+<br>
+// Load - absolute addressing mode: These instruction take constant<br>
+// value as the extended operand<br>
+<br>
+multiclass LD_absimm<string OpcStr> {<br>
+ let isPredicable = 1 in<br>
+ def _abs_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins u6Imm:$src),<br>
+ !strconcat("$dst = ", !strconcat(OpcStr, "(#$src)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, u6Imm:$src2),<br>
+ !strconcat("if ($src1) $dst = ", !strconcat(OpcStr, "(#$src2)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, u6Imm:$src2),<br>
+ !strconcat("if (!$src1) $dst = ", !strconcat(OpcStr, "(#$src2)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, u6Imm:$src2),<br>
+ !strconcat("if ($src1.new) $dst = ", !strconcat(OpcStr, "(#$src2)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+ let isPredicated = 1 in<br>
+ def _abs_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst),<br>
+ (ins PredRegs:$src1, u6Imm:$src2),<br>
+ !strconcat("if (!$src1.new) $dst = ", !strconcat(OpcStr, "(#$src2)")),<br>
+ []>,<br>
+ Requires<[HasV4T]>;<br>
+}<br>
+<br>
+defm LDrib_imm : LD_absimm<"memb">;<br>
+defm LDriub_imm : LD_absimm<"memub">;<br>
+defm LDrih_imm : LD_absimm<"memh">;<br>
+defm LDriuh_imm : LD_absimm<"memuh">;<br>
+defm LDriw_imm : LD_absimm<"memw">;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity = 30 in<br>
+def : Pat<(i32 (load u6ImmPred:$src)),<br>
+ (LDriw_imm_abs_V4 u6ImmPred:$src)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (sextloadi8 u6ImmPred:$src)),<br>
+ (LDrib_imm_abs_V4 u6ImmPred:$src)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (zextloadi8 u6ImmPred:$src)),<br>
+ (LDriub_imm_abs_V4 u6ImmPred:$src)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (sextloadi16 u6ImmPred:$src)),<br>
+ (LDrih_imm_abs_V4 u6ImmPred:$src)>;<br>
+<br>
+let Predicates = [HasV4T], AddedComplexity=30 in<br>
+def : Pat<(i32 (zextloadi16 u6ImmPred:$src)),<br>
+ (LDriuh_imm_abs_V4 u6ImmPred:$src)>;<br>
+<br>
+<br>
+// Indexed store double word - global address.<br>
+// memw(Rs+#u6:2)=#S8<br>
+let AddedComplexity = 10 in<br>
+def STriw_offset_ext_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u6_2Imm:$src2, globaladdress:$src3),<br>
+ "memw($src1+#$src2) = ##$src3",<br>
+ [(store (HexagonCONST32 tglobaladdr:$src3),<br>
+ (add IntRegs:$src1, u6_2ImmPred:$src2))]>,<br>
+ Requires<[HasV4T]>;<br>
+<br>
+<br>
+// Indexed store double word - global address.<br>
+// memw(Rs+#u6:2)=#S8<br>
+let AddedComplexity = 10 in<br>
+def STrih_offset_ext_V4 : STInst<(outs),<br>
+ (ins IntRegs:$src1, u6_1Imm:$src2, globaladdress:$src3),<br>
+ "memh($src1+#$src2) = ##$src3",<br>
+ [(truncstorei16 (HexagonCONST32 tglobaladdr:$src3),<br>
+ (add IntRegs:$src1, u6_1ImmPred:$src2))]>,<br>
+ Requires<[HasV4T]>;<br>
<br>
Added: llvm/trunk/lib/Target/Hexagon/HexagonMCInst.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInst.h?rev=154616&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInst.h?rev=154616&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonMCInst.h (added)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonMCInst.h Thu Apr 12 16:06:38 2012<br>
@@ -0,0 +1,41 @@<br>
+//===- HexagonMCInst.h - Hexagon sub-class of MCInst ----------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This class extends MCInst to allow some VLIW annotation.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef HEXAGONMCINST_H<br>
+#define HEXAGONMCINST_H<br>
+<br>
+#include "llvm/MC/MCInst.h"<br>
+#include "llvm/CodeGen/MachineInstr.h"<br>
+<br>
+namespace llvm {<br>
+ class HexagonMCInst: public MCInst {<br>
+ // Packet start and end markers<br>
+ unsigned startPacket: 1, endPacket: 1;<br>
+ const MachineInstr *MachineI;<br>
+ public:<br>
+ explicit HexagonMCInst(): MCInst(),<br>
+ startPacket(0), endPacket(0) {}<br>
+<br>
+ const MachineInstr* getMI() const { return MachineI; };<br>
+<br>
+ void setMI(const MachineInstr *MI) { MachineI = MI; };<br>
+<br>
+ bool isStartPacket() const { return (startPacket); };<br>
+ bool isEndPacket() const { return (endPacket); };<br>
+<br>
+ void setStartPacket(bool yes) { startPacket = yes; };<br>
+ void setEndPacket(bool yes) { endPacket = yes; };<br>
+ };<br>
+}<br>
+<br>
+#endif<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td Thu Apr 12 16:06:38 2012<br>
@@ -13,7 +13,6 @@<br>
def MUNIT : FuncUnit;<br>
def SUNIT : FuncUnit;<br>
<br>
-<br>
// Itinerary classes<br>
def ALU32 : InstrItinClass;<br>
def ALU64 : InstrItinClass;<br>
@@ -24,23 +23,25 @@<br>
def M : InstrItinClass;<br>
def ST : InstrItinClass;<br>
def S : InstrItinClass;<br>
+def SYS : InstrItinClass;<br>
+def MARKER : InstrItinClass;<br>
def PSEUDO : InstrItinClass;<br>
<br>
-<br>
def HexagonItineraries :<br>
- ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [<br>
- InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,<br>
- InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,<br>
- InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,<br>
- InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,<br>
- InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,<br>
- InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,<br>
- InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,<br>
- InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,<br>
- InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,<br>
- InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]><br>
-]>;<br>
-<br>
+ ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [<br>
+ InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,<br>
+ InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,<br>
+ InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,<br>
+ InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,<br>
+ InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,<br>
+ InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,<br>
+ InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,<br>
+ InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,<br>
+ InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,<br>
+ InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,<br>
+ InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,<br>
+ InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]><br>
+ ]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// V4 Machine Info +<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td Thu Apr 12 16:06:38 2012<br>
@@ -23,7 +23,6 @@<br>
// | SLOT3 | XTYPE ALU32 J CR |<br>
// |===========|==================================================|<br>
<br>
-<br>
// Functional Units.<br>
def SLOT0 : FuncUnit;<br>
def SLOT1 : FuncUnit;<br>
@@ -34,22 +33,26 @@<br>
def NV_V4 : InstrItinClass;<br>
def MEM_V4 : InstrItinClass;<br>
// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.<br>
+def PREFIX : InstrItinClass;<br>
<br>
-def HexagonItinerariesV4 : ProcessorItineraries<<br>
- [SLOT0, SLOT1, SLOT2, SLOT3], [], [<br>
- InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,<br>
- InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,<br>
- InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,<br>
- InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>,<br>
- InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>,<br>
- InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
- InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,<br>
- InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,<br>
- InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,<br>
- InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
- InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
- InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]><br>
-]>;<br>
+def HexagonItinerariesV4 :<br>
+ ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3], [], [<br>
+ InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,<br>
+ InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
+ InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,<br>
+ InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
+ InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,<br>
+ InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,<br>
+ InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
+ InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,<br>
+ InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>,<br>
+ InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>,<br>
+ InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>,<br>
+ InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>,<br>
+ InstrItinData<MARKER , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,<br>
+ InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,<br>
+ InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]><br>
+ ]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// Hexagon V4 Resource Definitions -<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Thu Apr 12 16:06:38 2012<br>
@@ -138,5 +138,8 @@<br>
// Split up TFRcondsets into conditional transfers.<br>
PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));<br>
<br>
+ // Create Packets.<br>
+ PM.add(createHexagonPacketizer());<br>
+<br>
return false;<br>
}<br>
<br>
Added: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=154616&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=154616&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (added)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Thu Apr 12 16:06:38 2012<br>
@@ -0,0 +1,3654 @@<br>
+//===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This implements a simple VLIW packetizer using DFA. The packetizer works on<br>
+// machine basic blocks. For each instruction I in BB, the packetizer consults<br>
+// the DFA to see if machine resources are available to execute I. If so, the<br>
+// packetizer checks if I depends on any instruction J in the current packet.<br>
+// If no dependency is found, I is added to current packet and machine resource<br>
+// is marked as taken. If any dependency is found, a target API call is made to<br>
+// prune the dependence.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+#define DEBUG_TYPE "packets"<br>
+#include "llvm/CodeGen/DFAPacketizer.h"<br>
+#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/CodeGen/MachineDominators.h"<br>
+#include "llvm/CodeGen/MachineFunctionPass.h"<br>
+#include "llvm/CodeGen/MachineLoopInfo.h"<br>
+#include "llvm/CodeGen/ScheduleDAG.h"<br>
+#include "llvm/CodeGen/ScheduleDAGInstrs.h"<br>
+#include "llvm/CodeGen/LatencyPriorityQueue.h"<br>
+#include "llvm/CodeGen/SchedulerRegistry.h"<br>
+#include "llvm/CodeGen/MachineFrameInfo.h"<br>
+#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
+#include "llvm/CodeGen/MachineRegisterInfo.h"<br>
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"<br>
+#include "llvm/CodeGen/ScheduleHazardRecognizer.h"<br>
+#include "llvm/Target/TargetMachine.h"<br>
+#include "llvm/Target/TargetInstrInfo.h"<br>
+#include "llvm/Target/TargetRegisterInfo.h"<br>
+#include "llvm/ADT/DenseMap.h"<br>
+#include "llvm/ADT/Statistic.h"<br>
+#include "llvm/Support/MathExtras.h"<br>
+#include "llvm/MC/MCInstrItineraries.h"<br>
+#include "llvm/Support/Compiler.h"<br>
+#include "llvm/Support/CommandLine.h"<br>
+#include "llvm/Support/Debug.h"<br>
+#include "Hexagon.h"<br>
+#include "HexagonTargetMachine.h"<br>
+#include "HexagonRegisterInfo.h"<br>
+#include "HexagonSubtarget.h"<br>
+#include "HexagonMachineFunctionInfo.h"<br>
+<br>
+#include <map><br>
+<br>
+using namespace llvm;<br>
+<br>
+namespace {<br>
+ class HexagonPacketizer : public MachineFunctionPass {<br>
+<br>
+ public:<br>
+ static char ID;<br>
+ HexagonPacketizer() : MachineFunctionPass(ID) {}<br>
+<br>
+ void getAnalysisUsage(AnalysisUsage &AU) const {<br>
+ AU.setPreservesCFG();<br>
+ AU.addRequired<MachineDominatorTree>();<br>
+ AU.addPreserved<MachineDominatorTree>();<br>
+ AU.addRequired<MachineLoopInfo>();<br>
+ AU.addPreserved<MachineLoopInfo>();<br>
+ MachineFunctionPass::getAnalysisUsage(AU);<br>
+ }<br>
+<br>
+ const char *getPassName() const {<br>
+ return "Hexagon Packetizer";<br>
+ }<br>
+<br>
+ bool runOnMachineFunction(MachineFunction &Fn);<br>
+ };<br>
+ char HexagonPacketizer::ID = 0;<br>
+<br>
+ class HexagonPacketizerList : public VLIWPacketizerList {<br>
+<br>
+ private:<br>
+<br>
+ // Has the instruction been promoted to a dot-new instruction.<br>
+ bool PromotedToDotNew;<br>
+<br>
+ // Has the instruction been glued to allocframe.<br>
+ bool GlueAllocframeStore;<br>
+<br>
+ // Has the feeder instruction been glued to new value jump.<br>
+ bool GlueToNewValueJump;<br>
+<br>
+ // Check if there is a dependence between some instruction already in this<br>
+ // packet and this instruction.<br>
+ bool Dependence;<br>
+<br>
+ // Only check for dependence if there are resources available to<br>
+ // schedule this instruction.<br>
+ bool FoundSequentialDependence;<br>
+<br>
+ public:<br>
+ // Ctor.<br>
+ HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,<br>
+ MachineDominatorTree &MDT);<br>
+<br>
+ // initPacketizerState - initialize some internal flags.<br>
+ void initPacketizerState(void);<br>
+<br>
+ // ignorePseudoInstruction - Ignore bundling of pseudo instructions.<br>
+ bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);<br>
+<br>
+ // isSoloInstruction - return true if instruction MI can not be packetized<br>
+ // with any other instruction, which means that MI itself is a packet.<br>
+ bool isSoloInstruction(MachineInstr *MI);<br>
+<br>
+ // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ<br>
+ // together.<br>
+ bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);<br>
+<br>
+ // isLegalToPruneDependencies - Is it legal to prune dependece between SUI<br>
+ // and SUJ.<br>
+ bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);<br>
+<br>
+ MachineBasicBlock::iterator addToPacket(MachineInstr *MI);<br>
+ private:<br>
+ bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);<br>
+ bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,<br>
+ MachineBasicBlock::iterator &MII,<br>
+ const TargetRegisterClass* RC);<br>
+ bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,<br>
+ unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit,<br>
+ MachineBasicBlock::iterator &MII,<br>
+ const TargetRegisterClass* RC);<br>
+ bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,<br>
+ unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit,<br>
+ MachineBasicBlock::iterator &MII);<br>
+ bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,<br>
+ unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit);<br>
+ bool DemoteToDotOld(MachineInstr* MI);<br>
+ bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit);<br>
+ bool RestrictingDepExistInPacket(MachineInstr*,<br>
+ unsigned, std::map <MachineInstr*, SUnit*>);<br>
+ bool isNewifiable(MachineInstr* MI);<br>
+ bool isCondInst(MachineInstr* MI);<br>
+ bool IsNewifyStore (MachineInstr* MI);<br>
+ bool tryAllocateResourcesForConstExt(MachineInstr* MI);<br>
+ bool canReserveResourcesForConstExt(MachineInstr *MI);<br>
+ void reserveResourcesForConstExt(MachineInstr* MI);<br>
+ bool isNewValueInst(MachineInstr* MI);<br>
+ bool isDotNewInst(MachineInstr* MI);<br>
+ };<br>
+}<br>
+<br>
+// HexagonPacketizerList Ctor.<br>
+HexagonPacketizerList::HexagonPacketizerList(<br>
+ MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)<br>
+ : VLIWPacketizerList(MF, MLI, MDT, true){<br>
+}<br>
+<br>
+bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {<br>
+ const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();<br>
+ MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();<br>
+ MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();<br>
+<br>
+ // Instantiate the packetizer.<br>
+ HexagonPacketizerList Packetizer(Fn, MLI, MDT);<br>
+<br>
+ // DFA state table should not be empty.<br>
+ assert(Packetizer.getResourceTracker() && "Empty DFA table!");<br>
+<br>
+ //<br>
+ // Loop over all basic blocks and remove KILL pseudo-instructions<br>
+ // These instructions confuse the dependence analysis. Consider:<br>
+ // D0 = ... (Insn 0)<br>
+ // R0 = KILL R0, D0 (Insn 1)<br>
+ // R0 = ... (Insn 2)<br>
+ // Here, Insn 1 will result in the dependence graph not emitting an output<br>
+ // dependence between Insn 0 and Insn 2. This can lead to incorrect<br>
+ // packetization<br>
+ //<br>
+ for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();<br>
+ MBB != MBBe; ++MBB) {<br>
+ MachineBasicBlock::iterator End = MBB->end();<br>
+ MachineBasicBlock::iterator MI = MBB->begin();<br>
+ while (MI != End) {<br>
+ if (MI->isKill()) {<br>
+ MachineBasicBlock::iterator DeleteMI = MI;<br>
+ ++MI;<br>
+ MBB->erase(DeleteMI);<br>
+ End = MBB->end();<br>
+ continue;<br>
+ }<br>
+ ++MI;<br>
+ }<br>
+ }<br>
+<br>
+ // Loop over all of the basic blocks.<br>
+ for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();<br>
+ MBB != MBBe; ++MBB) {<br>
+ // Find scheduling regions and schedule / packetize each region.<br>
+ unsigned RemainingCount = MBB->size();<br>
+ for(MachineBasicBlock::iterator RegionEnd = MBB->end();<br>
+ RegionEnd != MBB->begin();) {<br>
+ // The next region starts above the previous region. Look backward in the<br>
+ // instruction stream until we find the nearest boundary.<br>
+ MachineBasicBlock::iterator I = RegionEnd;<br>
+ for(;I != MBB->begin(); --I, --RemainingCount) {<br>
+ if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))<br>
+ break;<br>
+ }<br>
+ I = MBB->begin();<br>
+<br>
+ // Skip empty scheduling regions.<br>
+ if (I == RegionEnd) {<br>
+ RegionEnd = llvm::prior(RegionEnd);<br>
+ --RemainingCount;<br>
+ continue;<br>
+ }<br>
+ // Skip regions with one instruction.<br>
+ if (I == llvm::prior(RegionEnd)) {<br>
+ RegionEnd = llvm::prior(RegionEnd);<br>
+ continue;<br>
+ }<br>
+<br>
+ Packetizer.PacketizeMIs(MBB, I, RegionEnd);<br>
+ RegionEnd = I;<br>
+ }<br>
+ }<br>
+<br>
+ return true;<br>
+}<br>
+<br>
+<br>
+static bool IsIndirectCall(MachineInstr* MI) {<br>
+ return ((MI->getOpcode() == Hexagon::CALLR) ||<br>
+ (MI->getOpcode() == Hexagon::CALLRv3));<br>
+}<br>
+<br>
+// Reserve resources for constant extender. Trigure an assertion if<br>
+// reservation fail.<br>
+void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(<br>
+ QII->get(Hexagon::IMMEXT), MI->getDebugLoc());<br>
+<br>
+ if (ResourceTracker->canReserveResources(PseudoMI)) {<br>
+ ResourceTracker->reserveResources(PseudoMI);<br>
+ MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);<br>
+ } else {<br>
+ MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);<br>
+ assert(0 && "can not reserve resources for constant extender.");<br>
+ }<br>
+ return;<br>
+}<br>
+<br>
+bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ assert(QII->isExtended(MI) &&<br>
+ "Should only be called for constant extended instructions");<br>
+ MachineFunction *MF = MI->getParent()->getParent();<br>
+ MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),<br>
+ MI->getDebugLoc());<br>
+ bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);<br>
+ MF->DeleteMachineInstr(PseudoMI);<br>
+ return CanReserve;<br>
+}<br>
+<br>
+// Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return<br>
+// true, otherwise, return false.<br>
+bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(<br>
+ QII->get(Hexagon::IMMEXT), MI->getDebugLoc());<br>
+<br>
+ if (ResourceTracker->canReserveResources(PseudoMI)) {<br>
+ ResourceTracker->reserveResources(PseudoMI);<br>
+ MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);<br>
+ return true;<br>
+ } else {<br>
+ MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);<br>
+ return false;<br>
+ }<br>
+}<br>
+<br>
+<br>
+bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,<br>
+ SDep::Kind DepType,<br>
+ unsigned DepReg) {<br>
+<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();<br>
+<br>
+ // Check for lr dependence<br>
+ if (DepReg == QRI->getRARegister()) {<br>
+ return true;<br>
+ }<br>
+<br>
+ if (QII->isDeallocRet(MI)) {<br>
+ if (DepReg == QRI->getFrameRegister() ||<br>
+ DepReg == QRI->getStackRegister())<br>
+ return true;<br>
+ }<br>
+<br>
+ // Check if this is a predicate dependence<br>
+ const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);<br>
+ if (RC == Hexagon::PredRegsRegisterClass) {<br>
+ return true;<br>
+ }<br>
+<br>
+ //<br>
+ // Lastly check for an operand used in an indirect call<br>
+ // If we had an attribute for checking if an instruction is an indirect call,<br>
+ // then we could have avoided this relatively brittle implementation of<br>
+ // IsIndirectCall()<br>
+ //<br>
+ // Assumes that the first operand of the CALLr is the function address<br>
+ //<br>
+ if (IsIndirectCall(MI) && (DepType == SDep::Data)) {<br>
+ MachineOperand MO = MI->getOperand(0);<br>
+ if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {<br>
+ return true;<br>
+ }<br>
+ }<br>
+<br>
+ return false;<br>
+}<br>
+<br>
+static bool IsRegDependence(const SDep::Kind DepType) {<br>
+ return (DepType == SDep::Data || DepType == SDep::Anti ||<br>
+ DepType == SDep::Output);<br>
+}<br>
+<br>
+static bool IsDirectJump(MachineInstr* MI) {<br>
+ return (MI->getOpcode() == Hexagon::JMP);<br>
+}<br>
+<br>
+static bool IsSchedBarrier(MachineInstr* MI) {<br>
+ switch (MI->getOpcode()) {<br>
+ case Hexagon::BARRIER:<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+static bool IsControlFlow(MachineInstr* MI) {<br>
+ return (MI->getDesc().isTerminator() || MI->getDesc().isCall());<br>
+}<br>
+<br>
+bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ if (QII->isNewValueJump(MI))<br>
+ return true;<br>
+<br>
+ if (QII->isNewValueStore(MI))<br>
+ return true;<br>
+<br>
+ return false;<br>
+}<br>
+<br>
+// Function returns true if an instruction can be promoted to the new-value<br>
+// store. It will always return false for v2 and v3.<br>
+// It lists all the conditional and unconditional stores that can be promoted<br>
+// to the new-value stores.<br>
+<br>
+bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {<br>
+ const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();<br>
+ switch (MI->getOpcode())<br>
+ {<br>
+ // store byte<br>
+ case Hexagon::STrib:<br>
+ case Hexagon::STrib_indexed:<br>
+ case Hexagon::STrib_indexed_shl_V4:<br>
+ case Hexagon::STrib_shl_V4:<br>
+ case Hexagon::STrib_GP_V4:<br>
+ case Hexagon::STb_GP_V4:<br>
+ case Hexagon::POST_STbri:<br>
+ case Hexagon::STrib_cPt:<br>
+ case Hexagon::STrib_cdnPt_V4:<br>
+ case Hexagon::STrib_cNotPt:<br>
+ case Hexagon::STrib_cdnNotPt_V4:<br>
+ case Hexagon::STrib_indexed_cPt:<br>
+ case Hexagon::STrib_indexed_cdnPt_V4:<br>
+ case Hexagon::STrib_indexed_cNotPt:<br>
+ case Hexagon::STrib_indexed_cdnNotPt_V4:<br>
+ case Hexagon::STrib_indexed_shl_cPt_V4:<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_V4:<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_V4:<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_V4:<br>
+ case Hexagon::POST_STbri_cPt:<br>
+ case Hexagon::POST_STbri_cdnPt_V4:<br>
+ case Hexagon::POST_STbri_cNotPt:<br>
+ case Hexagon::POST_STbri_cdnNotPt_V4:<br>
+ case Hexagon::STb_GP_cPt_V4:<br>
+ case Hexagon::STb_GP_cNotPt_V4:<br>
+ case Hexagon::STb_GP_cdnPt_V4:<br>
+ case Hexagon::STb_GP_cdnNotPt_V4:<br>
+ case Hexagon::STrib_GP_cPt_V4:<br>
+ case Hexagon::STrib_GP_cNotPt_V4:<br>
+ case Hexagon::STrib_GP_cdnPt_V4:<br>
+ case Hexagon::STrib_GP_cdnNotPt_V4:<br>
+<br>
+ // store halfword<br>
+ case Hexagon::STrih:<br>
+ case Hexagon::STrih_indexed:<br>
+ case Hexagon::STrih_indexed_shl_V4:<br>
+ case Hexagon::STrih_shl_V4:<br>
+ case Hexagon::STrih_GP_V4:<br>
+ case Hexagon::STh_GP_V4:<br>
+ case Hexagon::POST_SThri:<br>
+ case Hexagon::STrih_cPt:<br>
+ case Hexagon::STrih_cdnPt_V4:<br>
+ case Hexagon::STrih_cNotPt:<br>
+ case Hexagon::STrih_cdnNotPt_V4:<br>
+ case Hexagon::STrih_indexed_cPt:<br>
+ case Hexagon::STrih_indexed_cdnPt_V4:<br>
+ case Hexagon::STrih_indexed_cNotPt:<br>
+ case Hexagon::STrih_indexed_cdnNotPt_V4:<br>
+ case Hexagon::STrih_indexed_shl_cPt_V4:<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_V4:<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_V4:<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_V4:<br>
+ case Hexagon::POST_SThri_cPt:<br>
+ case Hexagon::POST_SThri_cdnPt_V4:<br>
+ case Hexagon::POST_SThri_cNotPt:<br>
+ case Hexagon::POST_SThri_cdnNotPt_V4:<br>
+ case Hexagon::STh_GP_cPt_V4:<br>
+ case Hexagon::STh_GP_cNotPt_V4:<br>
+ case Hexagon::STh_GP_cdnPt_V4:<br>
+ case Hexagon::STh_GP_cdnNotPt_V4:<br>
+ case Hexagon::STrih_GP_cPt_V4:<br>
+ case Hexagon::STrih_GP_cNotPt_V4:<br>
+ case Hexagon::STrih_GP_cdnPt_V4:<br>
+ case Hexagon::STrih_GP_cdnNotPt_V4:<br>
+<br>
+ // store word<br>
+ case Hexagon::STriw:<br>
+ case Hexagon::STriw_indexed:<br>
+ case Hexagon::STriw_indexed_shl_V4:<br>
+ case Hexagon::STriw_shl_V4:<br>
+ case Hexagon::STriw_GP_V4:<br>
+ case Hexagon::STw_GP_V4:<br>
+ case Hexagon::POST_STwri:<br>
+ case Hexagon::STriw_cPt:<br>
+ case Hexagon::STriw_cdnPt_V4:<br>
+ case Hexagon::STriw_cNotPt:<br>
+ case Hexagon::STriw_cdnNotPt_V4:<br>
+ case Hexagon::STriw_indexed_cPt:<br>
+ case Hexagon::STriw_indexed_cdnPt_V4:<br>
+ case Hexagon::STriw_indexed_cNotPt:<br>
+ case Hexagon::STriw_indexed_cdnNotPt_V4:<br>
+ case Hexagon::STriw_indexed_shl_cPt_V4:<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_V4:<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_V4:<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_V4:<br>
+ case Hexagon::POST_STwri_cPt:<br>
+ case Hexagon::POST_STwri_cdnPt_V4:<br>
+ case Hexagon::POST_STwri_cNotPt:<br>
+ case Hexagon::POST_STwri_cdnNotPt_V4:<br>
+ case Hexagon::STw_GP_cPt_V4:<br>
+ case Hexagon::STw_GP_cNotPt_V4:<br>
+ case Hexagon::STw_GP_cdnPt_V4:<br>
+ case Hexagon::STw_GP_cdnNotPt_V4:<br>
+ case Hexagon::STriw_GP_cPt_V4:<br>
+ case Hexagon::STriw_GP_cNotPt_V4:<br>
+ case Hexagon::STriw_GP_cdnPt_V4:<br>
+ case Hexagon::STriw_GP_cdnNotPt_V4:<br>
+ return QRI->Subtarget.hasV4TOps();<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+static bool IsLoopN(MachineInstr *MI) {<br>
+ return (MI->getOpcode() == Hexagon::LOOP0_i ||<br>
+ MI->getOpcode() == Hexagon::LOOP0_r);<br>
+}<br>
+<br>
+/// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a<br>
+/// callee-saved register.<br>
+static bool DoesModifyCalleeSavedReg(MachineInstr *MI,<br>
+ const TargetRegisterInfo *TRI) {<br>
+ for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {<br>
+ unsigned CalleeSavedReg = *CSR;<br>
+ if (MI->modifiesRegister(CalleeSavedReg, TRI))<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+// Return the new value instruction for a given store.<br>
+static int GetDotNewOp(const int opc) {<br>
+ switch (opc) {<br>
+<br>
+ // store new value byte<br>
+ case Hexagon::STrib:<br>
+ return Hexagon::STrib_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed:<br>
+ return Hexagon::STrib_indexed_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_V4:<br>
+ return Hexagon::STrib_indexed_shl_nv_V4;<br>
+<br>
+ case Hexagon::STrib_shl_V4:<br>
+ return Hexagon::STrib_shl_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_V4:<br>
+ return Hexagon::STrib_GP_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_V4:<br>
+ return Hexagon::STb_GP_nv_V4;<br>
+<br>
+ case Hexagon::POST_STbri:<br>
+ return Hexagon::POST_STbri_nv_V4;<br>
+<br>
+ case Hexagon::STrib_cPt:<br>
+ return Hexagon::STrib_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_cdnPt_V4:<br>
+ return Hexagon::STrib_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_cNotPt:<br>
+ return Hexagon::STrib_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_cdnNotPt_V4:<br>
+ return Hexagon::STrib_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cPt:<br>
+ return Hexagon::STrib_indexed_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cdnPt_V4:<br>
+ return Hexagon::STrib_indexed_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cNotPt:<br>
+ return Hexagon::STrib_indexed_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cdnNotPt_V4:<br>
+ return Hexagon::STrib_indexed_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cPt_V4:<br>
+ return Hexagon::STrib_indexed_shl_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_V4:<br>
+ return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_V4:<br>
+ return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_V4:<br>
+ return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cPt:<br>
+ return Hexagon::POST_STbri_cPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cdnPt_V4:<br>
+ return Hexagon::POST_STbri_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cNotPt:<br>
+ return Hexagon::POST_STbri_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cdnNotPt_V4:<br>
+ return Hexagon::POST_STbri_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_cPt_V4:<br>
+ return Hexagon::STb_GP_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_cNotPt_V4:<br>
+ return Hexagon::STb_GP_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_cdnPt_V4:<br>
+ return Hexagon::STb_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_cdnNotPt_V4:<br>
+ return Hexagon::STb_GP_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cPt_V4:<br>
+ return Hexagon::STrib_GP_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cNotPt_V4:<br>
+ return Hexagon::STrib_GP_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cdnPt_V4:<br>
+ return Hexagon::STrib_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cdnNotPt_V4:<br>
+ return Hexagon::STrib_GP_cdnNotPt_nv_V4;<br>
+<br>
+ // store new value halfword<br>
+ case Hexagon::STrih:<br>
+ return Hexagon::STrih_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed:<br>
+ return Hexagon::STrih_indexed_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_V4:<br>
+ return Hexagon::STrih_indexed_shl_nv_V4;<br>
+<br>
+ case Hexagon::STrih_shl_V4:<br>
+ return Hexagon::STrih_shl_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_V4:<br>
+ return Hexagon::STrih_GP_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_V4:<br>
+ return Hexagon::STh_GP_nv_V4;<br>
+<br>
+ case Hexagon::POST_SThri:<br>
+ return Hexagon::POST_SThri_nv_V4;<br>
+<br>
+ case Hexagon::STrih_cPt:<br>
+ return Hexagon::STrih_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_cdnPt_V4:<br>
+ return Hexagon::STrih_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_cNotPt:<br>
+ return Hexagon::STrih_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_cdnNotPt_V4:<br>
+ return Hexagon::STrih_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cPt:<br>
+ return Hexagon::STrih_indexed_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cdnPt_V4:<br>
+ return Hexagon::STrih_indexed_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cNotPt:<br>
+ return Hexagon::STrih_indexed_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cdnNotPt_V4:<br>
+ return Hexagon::STrih_indexed_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cPt_V4:<br>
+ return Hexagon::STrih_indexed_shl_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_V4:<br>
+ return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_V4:<br>
+ return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_V4:<br>
+ return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cPt:<br>
+ return Hexagon::POST_SThri_cPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cdnPt_V4:<br>
+ return Hexagon::POST_SThri_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cNotPt:<br>
+ return Hexagon::POST_SThri_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cdnNotPt_V4:<br>
+ return Hexagon::POST_SThri_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_cPt_V4:<br>
+ return Hexagon::STh_GP_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_cNotPt_V4:<br>
+ return Hexagon::STh_GP_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_cdnPt_V4:<br>
+ return Hexagon::STh_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_cdnNotPt_V4:<br>
+ return Hexagon::STh_GP_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cPt_V4:<br>
+ return Hexagon::STrih_GP_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cNotPt_V4:<br>
+ return Hexagon::STrih_GP_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cdnPt_V4:<br>
+ return Hexagon::STrih_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cdnNotPt_V4:<br>
+ return Hexagon::STrih_GP_cdnNotPt_nv_V4;<br>
+<br>
+ // store new value word<br>
+ case Hexagon::STriw:<br>
+ return Hexagon::STriw_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed:<br>
+ return Hexagon::STriw_indexed_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_V4:<br>
+ return Hexagon::STriw_indexed_shl_nv_V4;<br>
+<br>
+ case Hexagon::STriw_shl_V4:<br>
+ return Hexagon::STriw_shl_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_V4:<br>
+ return Hexagon::STriw_GP_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_V4:<br>
+ return Hexagon::STw_GP_nv_V4;<br>
+<br>
+ case Hexagon::POST_STwri:<br>
+ return Hexagon::POST_STwri_nv_V4;<br>
+<br>
+ case Hexagon::STriw_cPt:<br>
+ return Hexagon::STriw_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_cdnPt_V4:<br>
+ return Hexagon::STriw_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_cNotPt:<br>
+ return Hexagon::STriw_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_cdnNotPt_V4:<br>
+ return Hexagon::STriw_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cPt:<br>
+ return Hexagon::STriw_indexed_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cdnPt_V4:<br>
+ return Hexagon::STriw_indexed_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cNotPt:<br>
+ return Hexagon::STriw_indexed_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cdnNotPt_V4:<br>
+ return Hexagon::STriw_indexed_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cPt_V4:<br>
+ return Hexagon::STriw_indexed_shl_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_V4:<br>
+ return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_V4:<br>
+ return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_V4:<br>
+ return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cPt:<br>
+ return Hexagon::POST_STwri_cPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cdnPt_V4:<br>
+ return Hexagon::POST_STwri_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cNotPt:<br>
+ return Hexagon::POST_STwri_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cdnNotPt_V4:<br>
+ return Hexagon::POST_STwri_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_cPt_V4:<br>
+ return Hexagon::STw_GP_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_cNotPt_V4:<br>
+ return Hexagon::STw_GP_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_cdnPt_V4:<br>
+ return Hexagon::STw_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_cdnNotPt_V4:<br>
+ return Hexagon::STw_GP_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cPt_V4:<br>
+ return Hexagon::STriw_GP_cPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cNotPt_V4:<br>
+ return Hexagon::STriw_GP_cNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cdnPt_V4:<br>
+ return Hexagon::STriw_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cdnNotPt_V4:<br>
+ return Hexagon::STriw_GP_cdnNotPt_nv_V4;<br>
+<br>
+ default:<br>
+ assert(0 && "Unknown .new type");<br>
+ }<br>
+ return 0;<br>
+}<br>
+<br>
+// Return .new predicate version for an instruction<br>
+static int GetDotNewPredOp(const int opc) {<br>
+ switch (opc) {<br>
+ // Conditional stores<br>
+ // Store byte conditionally<br>
+ case Hexagon::STrib_cPt :<br>
+ return Hexagon::STrib_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrib_cNotPt :<br>
+ return Hexagon::STrib_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cPt :<br>
+ return Hexagon::STrib_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cNotPt :<br>
+ return Hexagon::STrib_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrib_imm_cPt_V4 :<br>
+ return Hexagon::STrib_imm_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrib_imm_cNotPt_V4 :<br>
+ return Hexagon::STrib_imm_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cPt :<br>
+ return Hexagon::POST_STbri_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cNotPt :<br>
+ return Hexagon::POST_STbri_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cPt_V4 :<br>
+ return Hexagon::STrib_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::STrib_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STb_GP_cPt_V4 :<br>
+ return Hexagon::STb_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STb_GP_cNotPt_V4 :<br>
+ return Hexagon::STb_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cPt_V4 :<br>
+ return Hexagon::STrib_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cNotPt_V4 :<br>
+ return Hexagon::STrib_GP_cdnNotPt_V4;<br>
+<br>
+ // Store doubleword conditionally<br>
+ case Hexagon::STrid_cPt :<br>
+ return Hexagon::STrid_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrid_cNotPt :<br>
+ return Hexagon::STrid_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrid_indexed_cPt :<br>
+ return Hexagon::STrid_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrid_indexed_cNotPt :<br>
+ return Hexagon::STrid_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrid_indexed_shl_cPt_V4 :<br>
+ return Hexagon::STrid_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrid_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::STrid_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::POST_STdri_cPt :<br>
+ return Hexagon::POST_STdri_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_STdri_cNotPt :<br>
+ return Hexagon::POST_STdri_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STd_GP_cPt_V4 :<br>
+ return Hexagon::STd_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STd_GP_cNotPt_V4 :<br>
+ return Hexagon::STd_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrid_GP_cPt_V4 :<br>
+ return Hexagon::STrid_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrid_GP_cNotPt_V4 :<br>
+ return Hexagon::STrid_GP_cdnNotPt_V4;<br>
+<br>
+ // Store halfword conditionally<br>
+ case Hexagon::STrih_cPt :<br>
+ return Hexagon::STrih_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrih_cNotPt :<br>
+ return Hexagon::STrih_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cPt :<br>
+ return Hexagon::STrih_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cNotPt :<br>
+ return Hexagon::STrih_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrih_imm_cPt_V4 :<br>
+ return Hexagon::STrih_imm_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrih_imm_cNotPt_V4 :<br>
+ return Hexagon::STrih_imm_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cPt_V4 :<br>
+ return Hexagon::STrih_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::STrih_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cPt :<br>
+ return Hexagon::POST_SThri_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cNotPt :<br>
+ return Hexagon::POST_SThri_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STh_GP_cPt_V4 :<br>
+ return Hexagon::STh_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STh_GP_cNotPt_V4 :<br>
+ return Hexagon::STh_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cPt_V4 :<br>
+ return Hexagon::STrih_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cNotPt_V4 :<br>
+ return Hexagon::STrih_GP_cdnNotPt_V4;<br>
+<br>
+ // Store word conditionally<br>
+ case Hexagon::STriw_cPt :<br>
+ return Hexagon::STriw_cdnPt_V4;<br>
+<br>
+ case Hexagon::STriw_cNotPt :<br>
+ return Hexagon::STriw_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cPt :<br>
+ return Hexagon::STriw_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cNotPt :<br>
+ return Hexagon::STriw_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STriw_imm_cPt_V4 :<br>
+ return Hexagon::STriw_imm_cdnPt_V4;<br>
+<br>
+ case Hexagon::STriw_imm_cNotPt_V4 :<br>
+ return Hexagon::STriw_imm_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cPt_V4 :<br>
+ return Hexagon::STriw_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::STriw_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cPt :<br>
+ return Hexagon::POST_STwri_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cNotPt :<br>
+ return Hexagon::POST_STwri_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STw_GP_cPt_V4 :<br>
+ return Hexagon::STw_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STw_GP_cNotPt_V4 :<br>
+ return Hexagon::STw_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cPt_V4 :<br>
+ return Hexagon::STriw_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cNotPt_V4 :<br>
+ return Hexagon::STriw_GP_cdnNotPt_V4;<br>
+<br>
+ // Condtional Jumps<br>
+ case Hexagon::JMP_c:<br>
+ return Hexagon::JMP_cdnPt;<br>
+<br>
+ case Hexagon::JMP_cNot:<br>
+ return Hexagon::JMP_cdnNotPt;<br>
+<br>
+ case Hexagon::JMPR_cPt:<br>
+ return Hexagon::JMPR_cdnPt_V3;<br>
+<br>
+ case Hexagon::JMPR_cNotPt:<br>
+ return Hexagon::JMPR_cdnNotPt_V3;<br>
+<br>
+ // Conditional Transfers<br>
+ case Hexagon::TFR_cPt:<br>
+ return Hexagon::TFR_cdnPt;<br>
+<br>
+ case Hexagon::TFR_cNotPt:<br>
+ return Hexagon::TFR_cdnNotPt;<br>
+<br>
+ case Hexagon::TFRI_cPt:<br>
+ return Hexagon::TFRI_cdnPt;<br>
+<br>
+ case Hexagon::TFRI_cNotPt:<br>
+ return Hexagon::TFRI_cdnNotPt;<br>
+<br>
+ // Load double word<br>
+ case Hexagon::LDrid_cPt :<br>
+ return Hexagon::LDrid_cdnPt;<br>
+<br>
+ case Hexagon::LDrid_cNotPt :<br>
+ return Hexagon::LDrid_cdnNotPt;<br>
+<br>
+ case Hexagon::LDrid_indexed_cPt :<br>
+ return Hexagon::LDrid_indexed_cdnPt;<br>
+<br>
+ case Hexagon::LDrid_indexed_cNotPt :<br>
+ return Hexagon::LDrid_indexed_cdnNotPt;<br>
+<br>
+ case Hexagon::POST_LDrid_cPt :<br>
+ return Hexagon::POST_LDrid_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_LDrid_cNotPt :<br>
+ return Hexagon::POST_LDrid_cdnNotPt_V4;<br>
+<br>
+ // Load word<br>
+ case Hexagon::LDriw_cPt :<br>
+ return Hexagon::LDriw_cdnPt;<br>
+<br>
+ case Hexagon::LDriw_cNotPt :<br>
+ return Hexagon::LDriw_cdnNotPt;<br>
+<br>
+ case Hexagon::LDriw_indexed_cPt :<br>
+ return Hexagon::LDriw_indexed_cdnPt;<br>
+<br>
+ case Hexagon::LDriw_indexed_cNotPt :<br>
+ return Hexagon::LDriw_indexed_cdnNotPt;<br>
+<br>
+ case Hexagon::POST_LDriw_cPt :<br>
+ return Hexagon::POST_LDriw_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_LDriw_cNotPt :<br>
+ return Hexagon::POST_LDriw_cdnNotPt_V4;<br>
+<br>
+ // Load halfword<br>
+ case Hexagon::LDrih_cPt :<br>
+ return Hexagon::LDrih_cdnPt;<br>
+<br>
+ case Hexagon::LDrih_cNotPt :<br>
+ return Hexagon::LDrih_cdnNotPt;<br>
+<br>
+ case Hexagon::LDrih_indexed_cPt :<br>
+ return Hexagon::LDrih_indexed_cdnPt;<br>
+<br>
+ case Hexagon::LDrih_indexed_cNotPt :<br>
+ return Hexagon::LDrih_indexed_cdnNotPt;<br>
+<br>
+ case Hexagon::POST_LDrih_cPt :<br>
+ return Hexagon::POST_LDrih_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_LDrih_cNotPt :<br>
+ return Hexagon::POST_LDrih_cdnNotPt_V4;<br>
+<br>
+ // Load byte<br>
+ case Hexagon::LDrib_cPt :<br>
+ return Hexagon::LDrib_cdnPt;<br>
+<br>
+ case Hexagon::LDrib_cNotPt :<br>
+ return Hexagon::LDrib_cdnNotPt;<br>
+<br>
+ case Hexagon::LDrib_indexed_cPt :<br>
+ return Hexagon::LDrib_indexed_cdnPt;<br>
+<br>
+ case Hexagon::LDrib_indexed_cNotPt :<br>
+ return Hexagon::LDrib_indexed_cdnNotPt;<br>
+<br>
+ case Hexagon::POST_LDrib_cPt :<br>
+ return Hexagon::POST_LDrib_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_LDrib_cNotPt :<br>
+ return Hexagon::POST_LDrib_cdnNotPt_V4;<br>
+<br>
+ // Load unsigned halfword<br>
+ case Hexagon::LDriuh_cPt :<br>
+ return Hexagon::LDriuh_cdnPt;<br>
+<br>
+ case Hexagon::LDriuh_cNotPt :<br>
+ return Hexagon::LDriuh_cdnNotPt;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cPt :<br>
+ return Hexagon::LDriuh_indexed_cdnPt;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cNotPt :<br>
+ return Hexagon::LDriuh_indexed_cdnNotPt;<br>
+<br>
+ case Hexagon::POST_LDriuh_cPt :<br>
+ return Hexagon::POST_LDriuh_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_LDriuh_cNotPt :<br>
+ return Hexagon::POST_LDriuh_cdnNotPt_V4;<br>
+<br>
+ // Load unsigned byte<br>
+ case Hexagon::LDriub_cPt :<br>
+ return Hexagon::LDriub_cdnPt;<br>
+<br>
+ case Hexagon::LDriub_cNotPt :<br>
+ return Hexagon::LDriub_cdnNotPt;<br>
+<br>
+ case Hexagon::LDriub_indexed_cPt :<br>
+ return Hexagon::LDriub_indexed_cdnPt;<br>
+<br>
+ case Hexagon::LDriub_indexed_cNotPt :<br>
+ return Hexagon::LDriub_indexed_cdnNotPt;<br>
+<br>
+ case Hexagon::POST_LDriub_cPt :<br>
+ return Hexagon::POST_LDriub_cdnPt_V4;<br>
+<br>
+ case Hexagon::POST_LDriub_cNotPt :<br>
+ return Hexagon::POST_LDriub_cdnNotPt_V4;<br>
+<br>
+ // V4 indexed+scaled load<br>
+<br>
+ case Hexagon::LDrid_indexed_cPt_V4 :<br>
+ return Hexagon::LDrid_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrid_indexed_cNotPt_V4 :<br>
+ return Hexagon::LDrid_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrid_indexed_shl_cPt_V4 :<br>
+ return Hexagon::LDrid_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrid_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_cPt_V4 :<br>
+ return Hexagon::LDrib_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_cNotPt_V4 :<br>
+ return Hexagon::LDrib_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_shl_cPt_V4 :<br>
+ return Hexagon::LDrib_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_cPt_V4 :<br>
+ return Hexagon::LDriub_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_cNotPt_V4 :<br>
+ return Hexagon::LDriub_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_shl_cPt_V4 :<br>
+ return Hexagon::LDriub_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_cPt_V4 :<br>
+ return Hexagon::LDrih_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_cNotPt_V4 :<br>
+ return Hexagon::LDrih_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_shl_cPt_V4 :<br>
+ return Hexagon::LDrih_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cNotPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_shl_cPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_cPt_V4 :<br>
+ return Hexagon::LDriw_indexed_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_cNotPt_V4 :<br>
+ return Hexagon::LDriw_indexed_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_shl_cPt_V4 :<br>
+ return Hexagon::LDriw_indexed_shl_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_shl_cNotPt_V4 :<br>
+ return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;<br>
+<br>
+ // V4 global address load<br>
+<br>
+ case Hexagon::LDd_GP_cPt_V4:<br>
+ return Hexagon::LDd_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDd_GP_cNotPt_V4:<br>
+ return Hexagon::LDd_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDb_GP_cPt_V4:<br>
+ return Hexagon::LDb_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDb_GP_cNotPt_V4:<br>
+ return Hexagon::LDb_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDub_GP_cPt_V4:<br>
+ return Hexagon::LDub_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDub_GP_cNotPt_V4:<br>
+ return Hexagon::LDub_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDh_GP_cPt_V4:<br>
+ return Hexagon::LDh_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDh_GP_cNotPt_V4:<br>
+ return Hexagon::LDh_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDuh_GP_cPt_V4:<br>
+ return Hexagon::LDuh_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDuh_GP_cNotPt_V4:<br>
+ return Hexagon::LDuh_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDw_GP_cPt_V4:<br>
+ return Hexagon::LDw_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDw_GP_cNotPt_V4:<br>
+ return Hexagon::LDw_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrid_GP_cPt_V4:<br>
+ return Hexagon::LDrid_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrid_GP_cNotPt_V4:<br>
+ return Hexagon::LDrid_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrib_GP_cPt_V4:<br>
+ return Hexagon::LDrib_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrib_GP_cNotPt_V4:<br>
+ return Hexagon::LDrib_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriub_GP_cPt_V4:<br>
+ return Hexagon::LDriub_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriub_GP_cNotPt_V4:<br>
+ return Hexagon::LDriub_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDrih_GP_cPt_V4:<br>
+ return Hexagon::LDrih_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDrih_GP_cNotPt_V4:<br>
+ return Hexagon::LDrih_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_GP_cPt_V4:<br>
+ return Hexagon::LDriuh_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_GP_cNotPt_V4:<br>
+ return Hexagon::LDriuh_GP_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::LDriw_GP_cPt_V4:<br>
+ return Hexagon::LDriw_GP_cdnPt_V4;<br>
+<br>
+ case Hexagon::LDriw_GP_cNotPt_V4:<br>
+ return Hexagon::LDriw_GP_cdnNotPt_V4;<br>
+<br>
+ // Conditional store new-value byte<br>
+ case Hexagon::STrib_cPt_nv_V4 :<br>
+ return Hexagon::STrib_cdnPt_nv_V4;<br>
+ case Hexagon::STrib_cNotPt_nv_V4 :<br>
+ return Hexagon::STrib_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_cPt_nv_V4 :<br>
+ return Hexagon::STrib_indexed_cdnPt_nv_V4;<br>
+ case Hexagon::STrib_indexed_cNotPt_nv_V4 :<br>
+ return Hexagon::STrib_indexed_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cPt_nv_V4 :<br>
+ return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :<br>
+ return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cPt_nv_V4 :<br>
+ return Hexagon::POST_STbri_cdnPt_nv_V4;<br>
+ case Hexagon::POST_STbri_cNotPt_nv_V4 :<br>
+ return Hexagon::POST_STbri_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_cPt_nv_V4 :<br>
+ return Hexagon::STb_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STb_GP_cNotPt_nv_V4 :<br>
+ return Hexagon::STb_GP_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cPt_nv_V4 :<br>
+ return Hexagon::STrib_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cNotPt_nv_V4 :<br>
+ return Hexagon::STrib_GP_cdnNotPt_nv_V4;<br>
+<br>
+ // Conditional store new-value halfword<br>
+ case Hexagon::STrih_cPt_nv_V4 :<br>
+ return Hexagon::STrih_cdnPt_nv_V4;<br>
+ case Hexagon::STrih_cNotPt_nv_V4 :<br>
+ return Hexagon::STrih_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_cPt_nv_V4 :<br>
+ return Hexagon::STrih_indexed_cdnPt_nv_V4;<br>
+ case Hexagon::STrih_indexed_cNotPt_nv_V4 :<br>
+ return Hexagon::STrih_indexed_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cPt_nv_V4 :<br>
+ return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :<br>
+ return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cPt_nv_V4 :<br>
+ return Hexagon::POST_SThri_cdnPt_nv_V4;<br>
+ case Hexagon::POST_SThri_cNotPt_nv_V4 :<br>
+ return Hexagon::POST_SThri_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_cPt_nv_V4 :<br>
+ return Hexagon::STh_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STh_GP_cNotPt_nv_V4 :<br>
+ return Hexagon::STh_GP_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cPt_nv_V4 :<br>
+ return Hexagon::STrih_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cNotPt_nv_V4 :<br>
+ return Hexagon::STrih_GP_cdnNotPt_nv_V4;<br>
+<br>
+ // Conditional store new-value word<br>
+ case Hexagon::STriw_cPt_nv_V4 :<br>
+ return Hexagon::STriw_cdnPt_nv_V4;<br>
+ case Hexagon::STriw_cNotPt_nv_V4 :<br>
+ return Hexagon::STriw_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_cPt_nv_V4 :<br>
+ return Hexagon::STriw_indexed_cdnPt_nv_V4;<br>
+ case Hexagon::STriw_indexed_cNotPt_nv_V4 :<br>
+ return Hexagon::STriw_indexed_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cPt_nv_V4 :<br>
+ return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :<br>
+ return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cPt_nv_V4 :<br>
+ return Hexagon::POST_STwri_cdnPt_nv_V4;<br>
+ case Hexagon::POST_STwri_cNotPt_nv_V4:<br>
+ return Hexagon::POST_STwri_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_cPt_nv_V4 :<br>
+ return Hexagon::STw_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STw_GP_cNotPt_nv_V4 :<br>
+ return Hexagon::STw_GP_cdnNotPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cPt_nv_V4 :<br>
+ return Hexagon::STriw_GP_cdnPt_nv_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cNotPt_nv_V4 :<br>
+ return Hexagon::STriw_GP_cdnNotPt_nv_V4;<br>
+<br>
+ // Conditional add<br>
+ case Hexagon::ADD_ri_cPt :<br>
+ return Hexagon::ADD_ri_cdnPt;<br>
+ case Hexagon::ADD_ri_cNotPt :<br>
+ return Hexagon::ADD_ri_cdnNotPt;<br>
+<br>
+ case Hexagon::ADD_rr_cPt :<br>
+ return Hexagon::ADD_rr_cdnPt;<br>
+ case Hexagon::ADD_rr_cNotPt :<br>
+ return Hexagon::ADD_rr_cdnNotPt;<br>
+<br>
+ // Conditional logical Operations<br>
+ case Hexagon::XOR_rr_cPt :<br>
+ return Hexagon::XOR_rr_cdnPt;<br>
+ case Hexagon::XOR_rr_cNotPt :<br>
+ return Hexagon::XOR_rr_cdnNotPt;<br>
+<br>
+ case Hexagon::AND_rr_cPt :<br>
+ return Hexagon::AND_rr_cdnPt;<br>
+ case Hexagon::AND_rr_cNotPt :<br>
+ return Hexagon::AND_rr_cdnNotPt;<br>
+<br>
+ case Hexagon::OR_rr_cPt :<br>
+ return Hexagon::OR_rr_cdnPt;<br>
+ case Hexagon::OR_rr_cNotPt :<br>
+ return Hexagon::OR_rr_cdnNotPt;<br>
+<br>
+ // Conditional Subtract<br>
+ case Hexagon::SUB_rr_cPt :<br>
+ return Hexagon::SUB_rr_cdnPt;<br>
+ case Hexagon::SUB_rr_cNotPt :<br>
+ return Hexagon::SUB_rr_cdnNotPt;<br>
+<br>
+ // Conditional combine<br>
+ case Hexagon::COMBINE_rr_cPt :<br>
+ return Hexagon::COMBINE_rr_cdnPt;<br>
+ case Hexagon::COMBINE_rr_cNotPt :<br>
+ return Hexagon::COMBINE_rr_cdnNotPt;<br>
+<br>
+ case Hexagon::ASLH_cPt_V4 :<br>
+ return Hexagon::ASLH_cdnPt_V4;<br>
+ case Hexagon::ASLH_cNotPt_V4 :<br>
+ return Hexagon::ASLH_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::ASRH_cPt_V4 :<br>
+ return Hexagon::ASRH_cdnPt_V4;<br>
+ case Hexagon::ASRH_cNotPt_V4 :<br>
+ return Hexagon::ASRH_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::SXTB_cPt_V4 :<br>
+ return Hexagon::SXTB_cdnPt_V4;<br>
+ case Hexagon::SXTB_cNotPt_V4 :<br>
+ return Hexagon::SXTB_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::SXTH_cPt_V4 :<br>
+ return Hexagon::SXTH_cdnPt_V4;<br>
+ case Hexagon::SXTH_cNotPt_V4 :<br>
+ return Hexagon::SXTH_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::ZXTB_cPt_V4 :<br>
+ return Hexagon::ZXTB_cdnPt_V4;<br>
+ case Hexagon::ZXTB_cNotPt_V4 :<br>
+ return Hexagon::ZXTB_cdnNotPt_V4;<br>
+<br>
+ case Hexagon::ZXTH_cPt_V4 :<br>
+ return Hexagon::ZXTH_cdnPt_V4;<br>
+ case Hexagon::ZXTH_cNotPt_V4 :<br>
+ return Hexagon::ZXTH_cdnNotPt_V4;<br>
+<br>
+<br>
+ default:<br>
+ assert(0 && "Unknown .new type");<br>
+ }<br>
+ return 0;<br>
+}<br>
+<br>
+// Returns true if an instruction can be promoted to .new predicate<br>
+// or new-value store.<br>
+bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {<br>
+ if ( isCondInst(MI) || IsNewifyStore(MI))<br>
+ return true;<br>
+ else<br>
+ return false;<br>
+}<br>
+<br>
+bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ const MCInstrDesc& TID = MI->getDesc();<br>
+ // bug 5670: until that is fixed,<br>
+ // this portion is disabled.<br>
+ if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||<br>
+ || QII->isConditionalTransfer(MI)<br>
+ || QII->isConditionalALU32(MI)<br>
+ || QII->isConditionalLoad(MI)<br>
+ || QII->isConditionalStore(MI)) {<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+<br>
+// Promote an instructiont to its .new form.<br>
+// At this time, we have already made a call to CanPromoteToDotNew<br>
+// and made sure that it can *indeed* be promoted.<br>
+bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,<br>
+ SDep::Kind DepType, MachineBasicBlock::iterator &MII,<br>
+ const TargetRegisterClass* RC) {<br>
+<br>
+ assert (DepType == SDep::Data);<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+<br>
+ int NewOpcode;<br>
+ if (RC == Hexagon::PredRegsRegisterClass)<br>
+ NewOpcode = GetDotNewPredOp(MI->getOpcode());<br>
+ else<br>
+ NewOpcode = GetDotNewOp(MI->getOpcode());<br>
+ MI->setDesc(QII->get(NewOpcode));<br>
+<br>
+ return true;<br>
+}<br>
+<br>
+// Returns the most basic instruction for the .new predicated instructions and<br>
+// new-value stores.<br>
+// For example, all of the following instructions will be converted back to the<br>
+// same instruction:<br>
+// 1) if (p0.new) memw(R0+#0) = R1.new ---><br>
+// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1<br>
+// 3) if (p0.new) memw(R0+#0) = R1 ---><br>
+//<br>
+// To understand the translation of instruction 1 to its original form, consider<br>
+// a packet with 3 instructions.<br>
+// { p0 = cmp.eq(R0,R1)<br>
+// if (p0.new) R2 = add(R3, R4)<br>
+// R5 = add (R3, R1)<br>
+// }<br>
+// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet<br>
+//<br>
+// This instruction can be part of the previous packet only if both p0 and R2<br>
+// are promoted to .new values. This promotion happens in steps, first<br>
+// predicate register is promoted to .new and in the next iteration R2 is<br>
+// promoted. Therefore, in case of dependence check failure (due to R5) during<br>
+// next iteration, it should be converted back to its most basic form.<br>
+<br>
+static int GetDotOldOp(const int opc) {<br>
+ switch (opc) {<br>
+ case Hexagon::TFR_cdnPt:<br>
+ return Hexagon::TFR_cPt;<br>
+<br>
+ case Hexagon::TFR_cdnNotPt:<br>
+ return Hexagon::TFR_cNotPt;<br>
+<br>
+ case Hexagon::TFRI_cdnPt:<br>
+ return Hexagon::TFRI_cPt;<br>
+<br>
+ case Hexagon::TFRI_cdnNotPt:<br>
+ return Hexagon::TFRI_cNotPt;<br>
+<br>
+ case Hexagon::JMP_cdnPt:<br>
+ return Hexagon::JMP_c;<br>
+<br>
+ case Hexagon::JMP_cdnNotPt:<br>
+ return Hexagon::JMP_cNot;<br>
+<br>
+ case Hexagon::JMPR_cdnPt_V3:<br>
+ return Hexagon::JMPR_cPt;<br>
+<br>
+ case Hexagon::JMPR_cdnNotPt_V3:<br>
+ return Hexagon::JMPR_cNotPt;<br>
+<br>
+ // Load double word<br>
+<br>
+ case Hexagon::LDrid_cdnPt :<br>
+ return Hexagon::LDrid_cPt;<br>
+<br>
+ case Hexagon::LDrid_cdnNotPt :<br>
+ return Hexagon::LDrid_cNotPt;<br>
+<br>
+ case Hexagon::LDrid_indexed_cdnPt :<br>
+ return Hexagon::LDrid_indexed_cPt;<br>
+<br>
+ case Hexagon::LDrid_indexed_cdnNotPt :<br>
+ return Hexagon::LDrid_indexed_cNotPt;<br>
+<br>
+ case Hexagon::POST_LDrid_cdnPt_V4 :<br>
+ return Hexagon::POST_LDrid_cPt;<br>
+<br>
+ case Hexagon::POST_LDrid_cdnNotPt_V4 :<br>
+ return Hexagon::POST_LDrid_cNotPt;<br>
+<br>
+ // Load word<br>
+<br>
+ case Hexagon::LDriw_cdnPt :<br>
+ return Hexagon::LDriw_cPt;<br>
+<br>
+ case Hexagon::LDriw_cdnNotPt :<br>
+ return Hexagon::LDriw_cNotPt;<br>
+<br>
+ case Hexagon::LDriw_indexed_cdnPt :<br>
+ return Hexagon::LDriw_indexed_cPt;<br>
+<br>
+ case Hexagon::LDriw_indexed_cdnNotPt :<br>
+ return Hexagon::LDriw_indexed_cNotPt;<br>
+<br>
+ case Hexagon::POST_LDriw_cdnPt_V4 :<br>
+ return Hexagon::POST_LDriw_cPt;<br>
+<br>
+ case Hexagon::POST_LDriw_cdnNotPt_V4 :<br>
+ return Hexagon::POST_LDriw_cNotPt;<br>
+<br>
+ // Load half<br>
+<br>
+ case Hexagon::LDrih_cdnPt :<br>
+ return Hexagon::LDrih_cPt;<br>
+<br>
+ case Hexagon::LDrih_cdnNotPt :<br>
+ return Hexagon::LDrih_cNotPt;<br>
+<br>
+ case Hexagon::LDrih_indexed_cdnPt :<br>
+ return Hexagon::LDrih_indexed_cPt;<br>
+<br>
+ case Hexagon::LDrih_indexed_cdnNotPt :<br>
+ return Hexagon::LDrih_indexed_cNotPt;<br>
+<br>
+ case Hexagon::POST_LDrih_cdnPt_V4 :<br>
+ return Hexagon::POST_LDrih_cPt;<br>
+<br>
+ case Hexagon::POST_LDrih_cdnNotPt_V4 :<br>
+ return Hexagon::POST_LDrih_cNotPt;<br>
+<br>
+ // Load byte<br>
+<br>
+ case Hexagon::LDrib_cdnPt :<br>
+ return Hexagon::LDrib_cPt;<br>
+<br>
+ case Hexagon::LDrib_cdnNotPt :<br>
+ return Hexagon::LDrib_cNotPt;<br>
+<br>
+ case Hexagon::LDrib_indexed_cdnPt :<br>
+ return Hexagon::LDrib_indexed_cPt;<br>
+<br>
+ case Hexagon::LDrib_indexed_cdnNotPt :<br>
+ return Hexagon::LDrib_indexed_cNotPt;<br>
+<br>
+ case Hexagon::POST_LDrib_cdnPt_V4 :<br>
+ return Hexagon::POST_LDrib_cPt;<br>
+<br>
+ case Hexagon::POST_LDrib_cdnNotPt_V4 :<br>
+ return Hexagon::POST_LDrib_cNotPt;<br>
+<br>
+ // Load unsigned half<br>
+<br>
+ case Hexagon::LDriuh_cdnPt :<br>
+ return Hexagon::LDriuh_cPt;<br>
+<br>
+ case Hexagon::LDriuh_cdnNotPt :<br>
+ return Hexagon::LDriuh_cNotPt;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cdnPt :<br>
+ return Hexagon::LDriuh_indexed_cPt;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cdnNotPt :<br>
+ return Hexagon::LDriuh_indexed_cNotPt;<br>
+<br>
+ case Hexagon::POST_LDriuh_cdnPt_V4 :<br>
+ return Hexagon::POST_LDriuh_cPt;<br>
+<br>
+ case Hexagon::POST_LDriuh_cdnNotPt_V4 :<br>
+ return Hexagon::POST_LDriuh_cNotPt;<br>
+<br>
+ // Load unsigned byte<br>
+ case Hexagon::LDriub_cdnPt :<br>
+ return Hexagon::LDriub_cPt;<br>
+<br>
+ case Hexagon::LDriub_cdnNotPt :<br>
+ return Hexagon::LDriub_cNotPt;<br>
+<br>
+ case Hexagon::LDriub_indexed_cdnPt :<br>
+ return Hexagon::LDriub_indexed_cPt;<br>
+<br>
+ case Hexagon::LDriub_indexed_cdnNotPt :<br>
+ return Hexagon::LDriub_indexed_cNotPt;<br>
+<br>
+ case Hexagon::POST_LDriub_cdnPt_V4 :<br>
+ return Hexagon::POST_LDriub_cPt;<br>
+<br>
+ case Hexagon::POST_LDriub_cdnNotPt_V4 :<br>
+ return Hexagon::POST_LDriub_cNotPt;<br>
+<br>
+ // V4 indexed+scaled Load<br>
+<br>
+ case Hexagon::LDrid_indexed_cdnPt_V4 :<br>
+ return Hexagon::LDrid_indexed_cPt_V4;<br>
+<br>
+ case Hexagon::LDrid_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::LDrid_indexed_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrid_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::LDrid_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::LDrid_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_cdnPt_V4 :<br>
+ return Hexagon::LDrib_indexed_cPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::LDrib_indexed_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::LDrib_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::LDrib_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_cdnPt_V4 :<br>
+ return Hexagon::LDriub_indexed_cPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::LDriub_indexed_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::LDriub_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::LDriub_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_cdnPt_V4 :<br>
+ return Hexagon::LDrih_indexed_cPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::LDrih_indexed_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::LDrih_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::LDrih_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cdnPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_cPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::LDriuh_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_cdnPt_V4 :<br>
+ return Hexagon::LDriw_indexed_cPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::LDriw_indexed_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::LDriw_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::LDriw_indexed_shl_cNotPt_V4;<br>
+<br>
+ // V4 global address load<br>
+<br>
+ case Hexagon::LDd_GP_cdnPt_V4:<br>
+ return Hexagon::LDd_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDd_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDd_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDb_GP_cdnPt_V4:<br>
+ return Hexagon::LDb_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDb_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDb_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDub_GP_cdnPt_V4:<br>
+ return Hexagon::LDub_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDub_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDub_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDh_GP_cdnPt_V4:<br>
+ return Hexagon::LDh_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDh_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDh_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDuh_GP_cdnPt_V4:<br>
+ return Hexagon::LDuh_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDuh_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDuh_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDw_GP_cdnPt_V4:<br>
+ return Hexagon::LDw_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDw_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDw_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrid_GP_cdnPt_V4:<br>
+ return Hexagon::LDrid_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDrid_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDrid_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrib_GP_cdnPt_V4:<br>
+ return Hexagon::LDrib_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDrib_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDrib_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriub_GP_cdnPt_V4:<br>
+ return Hexagon::LDriub_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDriub_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDriub_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDrih_GP_cdnPt_V4:<br>
+ return Hexagon::LDrih_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDrih_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDrih_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_GP_cdnPt_V4:<br>
+ return Hexagon::LDriuh_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDriuh_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDriuh_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::LDriw_GP_cdnPt_V4:<br>
+ return Hexagon::LDriw_GP_cPt_V4;<br>
+<br>
+ case Hexagon::LDriw_GP_cdnNotPt_V4:<br>
+ return Hexagon::LDriw_GP_cNotPt_V4;<br>
+<br>
+ // Conditional add<br>
+<br>
+ case Hexagon::ADD_ri_cdnPt :<br>
+ return Hexagon::ADD_ri_cPt;<br>
+ case Hexagon::ADD_ri_cdnNotPt :<br>
+ return Hexagon::ADD_ri_cNotPt;<br>
+<br>
+ case Hexagon::ADD_rr_cdnPt :<br>
+ return Hexagon::ADD_rr_cPt;<br>
+ case Hexagon::ADD_rr_cdnNotPt:<br>
+ return Hexagon::ADD_rr_cNotPt;<br>
+<br>
+ // Conditional logical Operations<br>
+<br>
+ case Hexagon::XOR_rr_cdnPt :<br>
+ return Hexagon::XOR_rr_cPt;<br>
+ case Hexagon::XOR_rr_cdnNotPt :<br>
+ return Hexagon::XOR_rr_cNotPt;<br>
+<br>
+ case Hexagon::AND_rr_cdnPt :<br>
+ return Hexagon::AND_rr_cPt;<br>
+ case Hexagon::AND_rr_cdnNotPt :<br>
+ return Hexagon::AND_rr_cNotPt;<br>
+<br>
+ case Hexagon::OR_rr_cdnPt :<br>
+ return Hexagon::OR_rr_cPt;<br>
+ case Hexagon::OR_rr_cdnNotPt :<br>
+ return Hexagon::OR_rr_cNotPt;<br>
+<br>
+ // Conditional Subtract<br>
+<br>
+ case Hexagon::SUB_rr_cdnPt :<br>
+ return Hexagon::SUB_rr_cPt;<br>
+ case Hexagon::SUB_rr_cdnNotPt :<br>
+ return Hexagon::SUB_rr_cNotPt;<br>
+<br>
+ // Conditional combine<br>
+<br>
+ case Hexagon::COMBINE_rr_cdnPt :<br>
+ return Hexagon::COMBINE_rr_cPt;<br>
+ case Hexagon::COMBINE_rr_cdnNotPt :<br>
+ return Hexagon::COMBINE_rr_cNotPt;<br>
+<br>
+// Conditional shift operations<br>
+<br>
+ case Hexagon::ASLH_cdnPt_V4 :<br>
+ return Hexagon::ASLH_cPt_V4;<br>
+ case Hexagon::ASLH_cdnNotPt_V4 :<br>
+ return Hexagon::ASLH_cNotPt_V4;<br>
+<br>
+ case Hexagon::ASRH_cdnPt_V4 :<br>
+ return Hexagon::ASRH_cPt_V4;<br>
+ case Hexagon::ASRH_cdnNotPt_V4 :<br>
+ return Hexagon::ASRH_cNotPt_V4;<br>
+<br>
+ case Hexagon::SXTB_cdnPt_V4 :<br>
+ return Hexagon::SXTB_cPt_V4;<br>
+ case Hexagon::SXTB_cdnNotPt_V4 :<br>
+ return Hexagon::SXTB_cNotPt_V4;<br>
+<br>
+ case Hexagon::SXTH_cdnPt_V4 :<br>
+ return Hexagon::SXTH_cPt_V4;<br>
+ case Hexagon::SXTH_cdnNotPt_V4 :<br>
+ return Hexagon::SXTH_cNotPt_V4;<br>
+<br>
+ case Hexagon::ZXTB_cdnPt_V4 :<br>
+ return Hexagon::ZXTB_cPt_V4;<br>
+ case Hexagon::ZXTB_cdnNotPt_V4 :<br>
+ return Hexagon::ZXTB_cNotPt_V4;<br>
+<br>
+ case Hexagon::ZXTH_cdnPt_V4 :<br>
+ return Hexagon::ZXTH_cPt_V4;<br>
+ case Hexagon::ZXTH_cdnNotPt_V4 :<br>
+ return Hexagon::ZXTH_cNotPt_V4;<br>
+<br>
+ // Store byte<br>
+<br>
+ case Hexagon::STrib_imm_cdnPt_V4 :<br>
+ return Hexagon::STrib_imm_cPt_V4;<br>
+<br>
+ case Hexagon::STrib_imm_cdnNotPt_V4 :<br>
+ return Hexagon::STrib_imm_cNotPt_V4;<br>
+<br>
+ case Hexagon::STrib_cdnPt_nv_V4 :<br>
+ case Hexagon::STrib_cPt_nv_V4 :<br>
+ case Hexagon::STrib_cdnPt_V4 :<br>
+ return Hexagon::STrib_cPt;<br>
+<br>
+ case Hexagon::STrib_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STrib_cNotPt_nv_V4 :<br>
+ case Hexagon::STrib_cdnNotPt_V4 :<br>
+ return Hexagon::STrib_cNotPt;<br>
+<br>
+ case Hexagon::STrib_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrib_indexed_cPt_nv_V4 :<br>
+ case Hexagon::STrib_indexed_cdnPt_nv_V4 :<br>
+ return Hexagon::STrib_indexed_cPt;<br>
+<br>
+ case Hexagon::STrib_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_cNotPt_nv_V4 :<br>
+ case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :<br>
+ return Hexagon::STrib_indexed_cNotPt;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_cPt_nv_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::STrib_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::STrib_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::POST_STbri_cdnPt_nv_V4 :<br>
+ case Hexagon::POST_STbri_cPt_nv_V4 :<br>
+ case Hexagon::POST_STbri_cdnPt_V4 :<br>
+ return Hexagon::POST_STbri_cPt;<br>
+<br>
+ case Hexagon::POST_STbri_cdnNotPt_nv_V4 :<br>
+ case Hexagon::POST_STbri_cNotPt_nv_V4:<br>
+ case Hexagon::POST_STbri_cdnNotPt_V4 :<br>
+ return Hexagon::POST_STbri_cNotPt;<br>
+<br>
+ case Hexagon::STb_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STb_GP_cdnPt_V4:<br>
+ case Hexagon::STb_GP_cPt_nv_V4:<br>
+ return Hexagon::STb_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STb_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STb_GP_cdnNotPt_V4:<br>
+ case Hexagon::STb_GP_cNotPt_nv_V4:<br>
+ return Hexagon::STb_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STrib_GP_cdnPt_V4:<br>
+ case Hexagon::STrib_GP_cPt_nv_V4:<br>
+ return Hexagon::STrib_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STrib_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrib_GP_cdnNotPt_V4:<br>
+ case Hexagon::STrib_GP_cNotPt_nv_V4:<br>
+ return Hexagon::STrib_GP_cNotPt_V4;<br>
+<br>
+ // Store new-value byte - unconditional<br>
+ case Hexagon::STrib_nv_V4:<br>
+ return Hexagon::STrib;<br>
+<br>
+ case Hexagon::STrib_indexed_nv_V4:<br>
+ return Hexagon::STrib_indexed;<br>
+<br>
+ case Hexagon::STrib_indexed_shl_nv_V4:<br>
+ return Hexagon::STrib_indexed_shl_V4;<br>
+<br>
+ case Hexagon::STrib_shl_nv_V4:<br>
+ return Hexagon::STrib_shl_V4;<br>
+<br>
+ case Hexagon::STrib_GP_nv_V4:<br>
+ return Hexagon::STrib_GP_V4;<br>
+<br>
+ case Hexagon::STb_GP_nv_V4:<br>
+ return Hexagon::STb_GP_V4;<br>
+<br>
+ case Hexagon::POST_STbri_nv_V4:<br>
+ return Hexagon::POST_STbri;<br>
+<br>
+ // Store halfword<br>
+ case Hexagon::STrih_imm_cdnPt_V4 :<br>
+ return Hexagon::STrih_imm_cPt_V4;<br>
+<br>
+ case Hexagon::STrih_imm_cdnNotPt_V4 :<br>
+ return Hexagon::STrih_imm_cNotPt_V4;<br>
+<br>
+ case Hexagon::STrih_cdnPt_nv_V4 :<br>
+ case Hexagon::STrih_cPt_nv_V4 :<br>
+ case Hexagon::STrih_cdnPt_V4 :<br>
+ return Hexagon::STrih_cPt;<br>
+<br>
+ case Hexagon::STrih_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STrih_cNotPt_nv_V4 :<br>
+ case Hexagon::STrih_cdnNotPt_V4 :<br>
+ return Hexagon::STrih_cNotPt;<br>
+<br>
+ case Hexagon::STrih_indexed_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_cPt_nv_V4 :<br>
+ case Hexagon::STrih_indexed_cdnPt_V4 :<br>
+ return Hexagon::STrih_indexed_cPt;<br>
+<br>
+ case Hexagon::STrih_indexed_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_indexed_cNotPt_nv_V4 :<br>
+ case Hexagon::STrih_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::STrih_indexed_cNotPt;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cPt_nv_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::STrih_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::STrih_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::POST_SThri_cdnPt_nv_V4 :<br>
+ case Hexagon::POST_SThri_cPt_nv_V4 :<br>
+ case Hexagon::POST_SThri_cdnPt_V4 :<br>
+ return Hexagon::POST_SThri_cPt;<br>
+<br>
+ case Hexagon::POST_SThri_cdnNotPt_nv_V4 :<br>
+ case Hexagon::POST_SThri_cNotPt_nv_V4 :<br>
+ case Hexagon::POST_SThri_cdnNotPt_V4 :<br>
+ return Hexagon::POST_SThri_cNotPt;<br>
+<br>
+ case Hexagon::STh_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STh_GP_cdnPt_V4:<br>
+ case Hexagon::STh_GP_cPt_nv_V4:<br>
+ return Hexagon::STh_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STh_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STh_GP_cdnNotPt_V4:<br>
+ case Hexagon::STh_GP_cNotPt_nv_V4:<br>
+ return Hexagon::STh_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STrih_GP_cdnPt_V4:<br>
+ case Hexagon::STrih_GP_cPt_nv_V4:<br>
+ return Hexagon::STrih_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STrih_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STrih_GP_cdnNotPt_V4:<br>
+ case Hexagon::STrih_GP_cNotPt_nv_V4:<br>
+ return Hexagon::STrih_GP_cNotPt_V4;<br>
+<br>
+ // Store new-value halfword - unconditional<br>
+<br>
+ case Hexagon::STrih_nv_V4:<br>
+ return Hexagon::STrih;<br>
+<br>
+ case Hexagon::STrih_indexed_nv_V4:<br>
+ return Hexagon::STrih_indexed;<br>
+<br>
+ case Hexagon::STrih_indexed_shl_nv_V4:<br>
+ return Hexagon::STrih_indexed_shl_V4;<br>
+<br>
+ case Hexagon::STrih_shl_nv_V4:<br>
+ return Hexagon::STrih_shl_V4;<br>
+<br>
+ case Hexagon::STrih_GP_nv_V4:<br>
+ return Hexagon::STrih_GP_V4;<br>
+<br>
+ case Hexagon::STh_GP_nv_V4:<br>
+ return Hexagon::STh_GP_V4;<br>
+<br>
+ case Hexagon::POST_SThri_nv_V4:<br>
+ return Hexagon::POST_SThri;<br>
+<br>
+ // Store word<br>
+<br>
+ case Hexagon::STriw_imm_cdnPt_V4 :<br>
+ return Hexagon::STriw_imm_cPt_V4;<br>
+<br>
+ case Hexagon::STriw_imm_cdnNotPt_V4 :<br>
+ return Hexagon::STriw_imm_cNotPt_V4;<br>
+<br>
+ case Hexagon::STriw_cdnPt_nv_V4 :<br>
+ case Hexagon::STriw_cPt_nv_V4 :<br>
+ case Hexagon::STriw_cdnPt_V4 :<br>
+ return Hexagon::STriw_cPt;<br>
+<br>
+ case Hexagon::STriw_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STriw_cNotPt_nv_V4 :<br>
+ case Hexagon::STriw_cdnNotPt_V4 :<br>
+ return Hexagon::STriw_cNotPt;<br>
+<br>
+ case Hexagon::STriw_indexed_cdnPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_cPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_cdnPt_V4 :<br>
+ return Hexagon::STriw_indexed_cPt;<br>
+<br>
+ case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_cNotPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::STriw_indexed_cNotPt;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::STriw_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::STriw_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::POST_STwri_cdnPt_nv_V4 :<br>
+ case Hexagon::POST_STwri_cPt_nv_V4 :<br>
+ case Hexagon::POST_STwri_cdnPt_V4 :<br>
+ return Hexagon::POST_STwri_cPt;<br>
+<br>
+ case Hexagon::POST_STwri_cdnNotPt_nv_V4 :<br>
+ case Hexagon::POST_STwri_cNotPt_nv_V4 :<br>
+ case Hexagon::POST_STwri_cdnNotPt_V4 :<br>
+ return Hexagon::POST_STwri_cNotPt;<br>
+<br>
+ case Hexagon::STw_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STw_GP_cdnPt_V4:<br>
+ case Hexagon::STw_GP_cPt_nv_V4:<br>
+ return Hexagon::STw_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STw_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STw_GP_cdnNotPt_V4:<br>
+ case Hexagon::STw_GP_cNotPt_nv_V4:<br>
+ return Hexagon::STw_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cdnPt_nv_V4:<br>
+ case Hexagon::STriw_GP_cdnPt_V4:<br>
+ case Hexagon::STriw_GP_cPt_nv_V4:<br>
+ return Hexagon::STriw_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STriw_GP_cdnNotPt_nv_V4:<br>
+ case Hexagon::STriw_GP_cdnNotPt_V4:<br>
+ case Hexagon::STriw_GP_cNotPt_nv_V4:<br>
+ return Hexagon::STriw_GP_cNotPt_V4;<br>
+<br>
+ // Store new-value word - unconditional<br>
+<br>
+ case Hexagon::STriw_nv_V4:<br>
+ return Hexagon::STriw;<br>
+<br>
+ case Hexagon::STriw_indexed_nv_V4:<br>
+ return Hexagon::STriw_indexed;<br>
+<br>
+ case Hexagon::STriw_indexed_shl_nv_V4:<br>
+ return Hexagon::STriw_indexed_shl_V4;<br>
+<br>
+ case Hexagon::STriw_shl_nv_V4:<br>
+ return Hexagon::STriw_shl_V4;<br>
+<br>
+ case Hexagon::STriw_GP_nv_V4:<br>
+ return Hexagon::STriw_GP_V4;<br>
+<br>
+ case Hexagon::STw_GP_nv_V4:<br>
+ return Hexagon::STw_GP_V4;<br>
+<br>
+ case Hexagon::POST_STwri_nv_V4:<br>
+ return Hexagon::POST_STwri;<br>
+<br>
+ // Store doubleword<br>
+<br>
+ case Hexagon::STrid_cdnPt_V4 :<br>
+ return Hexagon::STrid_cPt;<br>
+<br>
+ case Hexagon::STrid_cdnNotPt_V4 :<br>
+ return Hexagon::STrid_cNotPt;<br>
+<br>
+ case Hexagon::STrid_indexed_cdnPt_V4 :<br>
+ return Hexagon::STrid_indexed_cPt;<br>
+<br>
+ case Hexagon::STrid_indexed_cdnNotPt_V4 :<br>
+ return Hexagon::STrid_indexed_cNotPt;<br>
+<br>
+ case Hexagon::STrid_indexed_shl_cdnPt_V4 :<br>
+ return Hexagon::STrid_indexed_shl_cPt_V4;<br>
+<br>
+ case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :<br>
+ return Hexagon::STrid_indexed_shl_cNotPt_V4;<br>
+<br>
+ case Hexagon::POST_STdri_cdnPt_V4 :<br>
+ return Hexagon::POST_STdri_cPt;<br>
+<br>
+ case Hexagon::POST_STdri_cdnNotPt_V4 :<br>
+ return Hexagon::POST_STdri_cNotPt;<br>
+<br>
+ case Hexagon::STd_GP_cdnPt_V4 :<br>
+ return Hexagon::STd_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STd_GP_cdnNotPt_V4 :<br>
+ return Hexagon::STd_GP_cNotPt_V4;<br>
+<br>
+ case Hexagon::STrid_GP_cdnPt_V4 :<br>
+ return Hexagon::STrid_GP_cPt_V4;<br>
+<br>
+ case Hexagon::STrid_GP_cdnNotPt_V4 :<br>
+ return Hexagon::STrid_GP_cNotPt_V4;<br>
+<br>
+ default:<br>
+ assert(0 && "Unknown .old type");<br>
+ }<br>
+ return 0;<br>
+}<br>
+<br>
+bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ int NewOpcode = GetDotOldOp(MI->getOpcode());<br>
+ MI->setDesc(QII->get(NewOpcode));<br>
+ return true;<br>
+}<br>
+<br>
+// Returns true if an instruction is predicated on p0 and false if it's<br>
+// predicated on !p0.<br>
+<br>
+static bool GetPredicateSense(MachineInstr* MI,<br>
+ const HexagonInstrInfo *QII) {<br>
+<br>
+ switch (MI->getOpcode()) {<br>
+ case Hexagon::TFR_cPt:<br>
+ case Hexagon::TFR_cdnPt:<br>
+ case Hexagon::TFRI_cPt:<br>
+ case Hexagon::TFRI_cdnPt:<br>
+ case Hexagon::STrib_cPt :<br>
+ case Hexagon::STrib_cdnPt_V4 :<br>
+ case Hexagon::STrib_indexed_cPt :<br>
+ case Hexagon::STrib_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::POST_STbri_cPt :<br>
+ case Hexagon::POST_STbri_cdnPt_V4 :<br>
+ case Hexagon::STrih_cPt :<br>
+ case Hexagon::STrih_cdnPt_V4 :<br>
+ case Hexagon::STrih_indexed_cPt :<br>
+ case Hexagon::STrih_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::POST_SThri_cPt :<br>
+ case Hexagon::POST_SThri_cdnPt_V4 :<br>
+ case Hexagon::STriw_cPt :<br>
+ case Hexagon::STriw_cdnPt_V4 :<br>
+ case Hexagon::STriw_indexed_cPt :<br>
+ case Hexagon::STriw_indexed_cdnPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::POST_STwri_cPt :<br>
+ case Hexagon::POST_STwri_cdnPt_V4 :<br>
+ case Hexagon::STrib_imm_cPt_V4 :<br>
+ case Hexagon::STrib_imm_cdnPt_V4 :<br>
+ case Hexagon::STrid_cPt :<br>
+ case Hexagon::STrid_cdnPt_V4 :<br>
+ case Hexagon::STrid_indexed_cPt :<br>
+ case Hexagon::STrid_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrid_indexed_shl_cPt_V4 :<br>
+ case Hexagon::STrid_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::POST_STdri_cPt :<br>
+ case Hexagon::POST_STdri_cdnPt_V4 :<br>
+ case Hexagon::STrih_imm_cPt_V4 :<br>
+ case Hexagon::STrih_imm_cdnPt_V4 :<br>
+ case Hexagon::STriw_imm_cPt_V4 :<br>
+ case Hexagon::STriw_imm_cdnPt_V4 :<br>
+ case Hexagon::JMP_cdnPt :<br>
+ case Hexagon::LDrid_cPt :<br>
+ case Hexagon::LDrid_cdnPt :<br>
+ case Hexagon::LDrid_indexed_cPt :<br>
+ case Hexagon::LDrid_indexed_cdnPt :<br>
+ case Hexagon::POST_LDrid_cPt :<br>
+ case Hexagon::POST_LDrid_cdnPt_V4 :<br>
+ case Hexagon::LDriw_cPt :<br>
+ case Hexagon::LDriw_cdnPt :<br>
+ case Hexagon::LDriw_indexed_cPt :<br>
+ case Hexagon::LDriw_indexed_cdnPt :<br>
+ case Hexagon::POST_LDriw_cPt :<br>
+ case Hexagon::POST_LDriw_cdnPt_V4 :<br>
+ case Hexagon::LDrih_cPt :<br>
+ case Hexagon::LDrih_cdnPt :<br>
+ case Hexagon::LDrih_indexed_cPt :<br>
+ case Hexagon::LDrih_indexed_cdnPt :<br>
+ case Hexagon::POST_LDrih_cPt :<br>
+ case Hexagon::POST_LDrih_cdnPt_V4 :<br>
+ case Hexagon::LDrib_cPt :<br>
+ case Hexagon::LDrib_cdnPt :<br>
+ case Hexagon::LDrib_indexed_cPt :<br>
+ case Hexagon::LDrib_indexed_cdnPt :<br>
+ case Hexagon::POST_LDrib_cPt :<br>
+ case Hexagon::POST_LDrib_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_cPt :<br>
+ case Hexagon::LDriuh_cdnPt :<br>
+ case Hexagon::LDriuh_indexed_cPt :<br>
+ case Hexagon::LDriuh_indexed_cdnPt :<br>
+ case Hexagon::POST_LDriuh_cPt :<br>
+ case Hexagon::POST_LDriuh_cdnPt_V4 :<br>
+ case Hexagon::LDriub_cPt :<br>
+ case Hexagon::LDriub_cdnPt :<br>
+ case Hexagon::LDriub_indexed_cPt :<br>
+ case Hexagon::LDriub_indexed_cdnPt :<br>
+ case Hexagon::POST_LDriub_cPt :<br>
+ case Hexagon::POST_LDriub_cdnPt_V4 :<br>
+ case Hexagon::LDrid_indexed_cPt_V4 :<br>
+ case Hexagon::LDrid_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDrid_indexed_shl_cPt_V4 :<br>
+ case Hexagon::LDrid_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDrib_indexed_cPt_V4 :<br>
+ case Hexagon::LDrib_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDrib_indexed_shl_cPt_V4 :<br>
+ case Hexagon::LDrib_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDriub_indexed_cPt_V4 :<br>
+ case Hexagon::LDriub_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDriub_indexed_shl_cPt_V4 :<br>
+ case Hexagon::LDriub_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDrih_indexed_cPt_V4 :<br>
+ case Hexagon::LDrih_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDrih_indexed_shl_cPt_V4 :<br>
+ case Hexagon::LDrih_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_cPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_shl_cPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDriw_indexed_cPt_V4 :<br>
+ case Hexagon::LDriw_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDriw_indexed_shl_cPt_V4 :<br>
+ case Hexagon::LDriw_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::ADD_ri_cPt :<br>
+ case Hexagon::ADD_ri_cdnPt :<br>
+ case Hexagon::ADD_rr_cPt :<br>
+ case Hexagon::ADD_rr_cdnPt :<br>
+ case Hexagon::XOR_rr_cPt :<br>
+ case Hexagon::XOR_rr_cdnPt :<br>
+ case Hexagon::AND_rr_cPt :<br>
+ case Hexagon::AND_rr_cdnPt :<br>
+ case Hexagon::OR_rr_cPt :<br>
+ case Hexagon::OR_rr_cdnPt :<br>
+ case Hexagon::SUB_rr_cPt :<br>
+ case Hexagon::SUB_rr_cdnPt :<br>
+ case Hexagon::COMBINE_rr_cPt :<br>
+ case Hexagon::COMBINE_rr_cdnPt :<br>
+ case Hexagon::ASLH_cPt_V4 :<br>
+ case Hexagon::ASLH_cdnPt_V4 :<br>
+ case Hexagon::ASRH_cPt_V4 :<br>
+ case Hexagon::ASRH_cdnPt_V4 :<br>
+ case Hexagon::SXTB_cPt_V4 :<br>
+ case Hexagon::SXTB_cdnPt_V4 :<br>
+ case Hexagon::SXTH_cPt_V4 :<br>
+ case Hexagon::SXTH_cdnPt_V4 :<br>
+ case Hexagon::ZXTB_cPt_V4 :<br>
+ case Hexagon::ZXTB_cdnPt_V4 :<br>
+ case Hexagon::ZXTH_cPt_V4 :<br>
+ case Hexagon::ZXTH_cdnPt_V4 :<br>
+ case Hexagon::LDrid_GP_cPt_V4 :<br>
+ case Hexagon::LDrib_GP_cPt_V4 :<br>
+ case Hexagon::LDriub_GP_cPt_V4 :<br>
+ case Hexagon::LDrih_GP_cPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cPt_V4 :<br>
+ case Hexagon::LDriw_GP_cPt_V4 :<br>
+ case Hexagon::LDd_GP_cPt_V4 :<br>
+ case Hexagon::LDb_GP_cPt_V4 :<br>
+ case Hexagon::LDub_GP_cPt_V4 :<br>
+ case Hexagon::LDh_GP_cPt_V4 :<br>
+ case Hexagon::LDuh_GP_cPt_V4 :<br>
+ case Hexagon::LDw_GP_cPt_V4 :<br>
+ case Hexagon::STrid_GP_cPt_V4 :<br>
+ case Hexagon::STrib_GP_cPt_V4 :<br>
+ case Hexagon::STrih_GP_cPt_V4 :<br>
+ case Hexagon::STriw_GP_cPt_V4 :<br>
+ case Hexagon::STd_GP_cPt_V4 :<br>
+ case Hexagon::STb_GP_cPt_V4 :<br>
+ case Hexagon::STh_GP_cPt_V4 :<br>
+ case Hexagon::STw_GP_cPt_V4 :<br>
+ case Hexagon::LDrid_GP_cdnPt_V4 :<br>
+ case Hexagon::LDrib_GP_cdnPt_V4 :<br>
+ case Hexagon::LDriub_GP_cdnPt_V4 :<br>
+ case Hexagon::LDrih_GP_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cdnPt_V4 :<br>
+ case Hexagon::LDriw_GP_cdnPt_V4 :<br>
+ case Hexagon::LDd_GP_cdnPt_V4 :<br>
+ case Hexagon::LDb_GP_cdnPt_V4 :<br>
+ case Hexagon::LDub_GP_cdnPt_V4 :<br>
+ case Hexagon::LDh_GP_cdnPt_V4 :<br>
+ case Hexagon::LDuh_GP_cdnPt_V4 :<br>
+ case Hexagon::LDw_GP_cdnPt_V4 :<br>
+ case Hexagon::STrid_GP_cdnPt_V4 :<br>
+ case Hexagon::STrib_GP_cdnPt_V4 :<br>
+ case Hexagon::STrih_GP_cdnPt_V4 :<br>
+ case Hexagon::STriw_GP_cdnPt_V4 :<br>
+ case Hexagon::STd_GP_cdnPt_V4 :<br>
+ case Hexagon::STb_GP_cdnPt_V4 :<br>
+ case Hexagon::STh_GP_cdnPt_V4 :<br>
+ case Hexagon::STw_GP_cdnPt_V4 :<br>
+ return true;<br>
+<br>
+ case Hexagon::TFR_cNotPt:<br>
+ case Hexagon::TFR_cdnNotPt:<br>
+ case Hexagon::TFRI_cNotPt:<br>
+ case Hexagon::TFRI_cdnNotPt:<br>
+ case Hexagon::STrib_cNotPt :<br>
+ case Hexagon::STrib_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_cNotPt :<br>
+ case Hexagon::STrib_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_STbri_cNotPt :<br>
+ case Hexagon::POST_STbri_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_cNotPt :<br>
+ case Hexagon::STrih_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_indexed_cNotPt :<br>
+ case Hexagon::STrih_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_SThri_cNotPt :<br>
+ case Hexagon::POST_SThri_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_cNotPt :<br>
+ case Hexagon::STriw_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_indexed_cNotPt :<br>
+ case Hexagon::STriw_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_STwri_cNotPt :<br>
+ case Hexagon::POST_STwri_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_imm_cNotPt_V4 :<br>
+ case Hexagon::STrib_imm_cdnNotPt_V4 :<br>
+ case Hexagon::STrid_cNotPt :<br>
+ case Hexagon::STrid_cdnNotPt_V4 :<br>
+ case Hexagon::STrid_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STrid_indexed_cNotPt :<br>
+ case Hexagon::STrid_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_STdri_cNotPt :<br>
+ case Hexagon::POST_STdri_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_imm_cNotPt_V4 :<br>
+ case Hexagon::STrih_imm_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_imm_cNotPt_V4 :<br>
+ case Hexagon::STriw_imm_cdnNotPt_V4 :<br>
+ case Hexagon::JMP_cdnNotPt :<br>
+ case Hexagon::LDrid_cNotPt :<br>
+ case Hexagon::LDrid_cdnNotPt :<br>
+ case Hexagon::LDrid_indexed_cNotPt :<br>
+ case Hexagon::LDrid_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDrid_cNotPt :<br>
+ case Hexagon::POST_LDrid_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_cNotPt :<br>
+ case Hexagon::LDriw_cdnNotPt :<br>
+ case Hexagon::LDriw_indexed_cNotPt :<br>
+ case Hexagon::LDriw_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDriw_cNotPt :<br>
+ case Hexagon::POST_LDriw_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_cNotPt :<br>
+ case Hexagon::LDrih_cdnNotPt :<br>
+ case Hexagon::LDrih_indexed_cNotPt :<br>
+ case Hexagon::LDrih_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDrih_cNotPt :<br>
+ case Hexagon::POST_LDrih_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_cNotPt :<br>
+ case Hexagon::LDrib_cdnNotPt :<br>
+ case Hexagon::LDrib_indexed_cNotPt :<br>
+ case Hexagon::LDrib_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDrib_cNotPt :<br>
+ case Hexagon::POST_LDrib_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_cNotPt :<br>
+ case Hexagon::LDriuh_cdnNotPt :<br>
+ case Hexagon::LDriuh_indexed_cNotPt :<br>
+ case Hexagon::LDriuh_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDriuh_cNotPt :<br>
+ case Hexagon::POST_LDriuh_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_cNotPt :<br>
+ case Hexagon::LDriub_cdnNotPt :<br>
+ case Hexagon::LDriub_indexed_cNotPt :<br>
+ case Hexagon::LDriub_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDriub_cNotPt :<br>
+ case Hexagon::POST_LDriub_cdnNotPt_V4 :<br>
+ case Hexagon::LDrid_indexed_cNotPt_V4 :<br>
+ case Hexagon::LDrid_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDrid_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_indexed_cNotPt_V4 :<br>
+ case Hexagon::LDrib_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_indexed_cNotPt_V4 :<br>
+ case Hexagon::LDriub_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_indexed_cNotPt_V4 :<br>
+ case Hexagon::LDrih_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_cNotPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_indexed_cNotPt_V4 :<br>
+ case Hexagon::LDriw_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_indexed_shl_cNotPt_V4 :<br>
+ case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::ADD_ri_cNotPt :<br>
+ case Hexagon::ADD_ri_cdnNotPt :<br>
+ case Hexagon::ADD_rr_cNotPt :<br>
+ case Hexagon::ADD_rr_cdnNotPt :<br>
+ case Hexagon::XOR_rr_cNotPt :<br>
+ case Hexagon::XOR_rr_cdnNotPt :<br>
+ case Hexagon::AND_rr_cNotPt :<br>
+ case Hexagon::AND_rr_cdnNotPt :<br>
+ case Hexagon::OR_rr_cNotPt :<br>
+ case Hexagon::OR_rr_cdnNotPt :<br>
+ case Hexagon::SUB_rr_cNotPt :<br>
+ case Hexagon::SUB_rr_cdnNotPt :<br>
+ case Hexagon::COMBINE_rr_cNotPt :<br>
+ case Hexagon::COMBINE_rr_cdnNotPt :<br>
+ case Hexagon::ASLH_cNotPt_V4 :<br>
+ case Hexagon::ASLH_cdnNotPt_V4 :<br>
+ case Hexagon::ASRH_cNotPt_V4 :<br>
+ case Hexagon::ASRH_cdnNotPt_V4 :<br>
+ case Hexagon::SXTB_cNotPt_V4 :<br>
+ case Hexagon::SXTB_cdnNotPt_V4 :<br>
+ case Hexagon::SXTH_cNotPt_V4 :<br>
+ case Hexagon::SXTH_cdnNotPt_V4 :<br>
+ case Hexagon::ZXTB_cNotPt_V4 :<br>
+ case Hexagon::ZXTB_cdnNotPt_V4 :<br>
+ case Hexagon::ZXTH_cNotPt_V4 :<br>
+ case Hexagon::ZXTH_cdnNotPt_V4 :<br>
+<br>
+ case Hexagon::LDrid_GP_cNotPt_V4 :<br>
+ case Hexagon::LDrib_GP_cNotPt_V4 :<br>
+ case Hexagon::LDriub_GP_cNotPt_V4 :<br>
+ case Hexagon::LDrih_GP_cNotPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cNotPt_V4 :<br>
+ case Hexagon::LDriw_GP_cNotPt_V4 :<br>
+ case Hexagon::LDd_GP_cNotPt_V4 :<br>
+ case Hexagon::LDb_GP_cNotPt_V4 :<br>
+ case Hexagon::LDub_GP_cNotPt_V4 :<br>
+ case Hexagon::LDh_GP_cNotPt_V4 :<br>
+ case Hexagon::LDuh_GP_cNotPt_V4 :<br>
+ case Hexagon::LDw_GP_cNotPt_V4 :<br>
+ case Hexagon::STrid_GP_cNotPt_V4 :<br>
+ case Hexagon::STrib_GP_cNotPt_V4 :<br>
+ case Hexagon::STrih_GP_cNotPt_V4 :<br>
+ case Hexagon::STriw_GP_cNotPt_V4 :<br>
+ case Hexagon::STd_GP_cNotPt_V4 :<br>
+ case Hexagon::STb_GP_cNotPt_V4 :<br>
+ case Hexagon::STh_GP_cNotPt_V4 :<br>
+ case Hexagon::STw_GP_cNotPt_V4 :<br>
+ case Hexagon::LDrid_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDd_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDb_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDub_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDuh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::LDw_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STrid_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STd_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STb_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STh_GP_cdnNotPt_V4 :<br>
+ case Hexagon::STw_GP_cdnNotPt_V4 :<br>
+ return false;<br>
+<br>
+ default:<br>
+ assert (false && "Unknown predicate sense of the instruction");<br>
+ }<br>
+ // return *some value* to avoid compiler warning<br>
+ return false;<br>
+}<br>
+<br>
+bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {<br>
+ if (isNewValueInst(MI))<br>
+ return true;<br>
+<br>
+ switch (MI->getOpcode()) {<br>
+ case Hexagon::TFR_cdnNotPt:<br>
+ case Hexagon::TFR_cdnPt:<br>
+ case Hexagon::TFRI_cdnNotPt:<br>
+ case Hexagon::TFRI_cdnPt:<br>
+ case Hexagon::LDrid_cdnPt :<br>
+ case Hexagon::LDrid_cdnNotPt :<br>
+ case Hexagon::LDrid_indexed_cdnPt :<br>
+ case Hexagon::LDrid_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDrid_cdnPt_V4 :<br>
+ case Hexagon::POST_LDrid_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_cdnPt :<br>
+ case Hexagon::LDriw_cdnNotPt :<br>
+ case Hexagon::LDriw_indexed_cdnPt :<br>
+ case Hexagon::LDriw_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDriw_cdnPt_V4 :<br>
+ case Hexagon::POST_LDriw_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_cdnPt :<br>
+ case Hexagon::LDrih_cdnNotPt :<br>
+ case Hexagon::LDrih_indexed_cdnPt :<br>
+ case Hexagon::LDrih_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDrih_cdnPt_V4 :<br>
+ case Hexagon::POST_LDrih_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_cdnPt :<br>
+ case Hexagon::LDrib_cdnNotPt :<br>
+ case Hexagon::LDrib_indexed_cdnPt :<br>
+ case Hexagon::LDrib_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDrib_cdnPt_V4 :<br>
+ case Hexagon::POST_LDrib_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_cdnPt :<br>
+ case Hexagon::LDriuh_cdnNotPt :<br>
+ case Hexagon::LDriuh_indexed_cdnPt :<br>
+ case Hexagon::LDriuh_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDriuh_cdnPt_V4 :<br>
+ case Hexagon::POST_LDriuh_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_cdnPt :<br>
+ case Hexagon::LDriub_cdnNotPt :<br>
+ case Hexagon::LDriub_indexed_cdnPt :<br>
+ case Hexagon::LDriub_indexed_cdnNotPt :<br>
+ case Hexagon::POST_LDriub_cdnPt_V4 :<br>
+ case Hexagon::POST_LDriub_cdnNotPt_V4 :<br>
+<br>
+ case Hexagon::LDrid_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDrid_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDrid_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDrib_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDrib_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDriub_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDriub_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDrih_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDrih_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_indexed_cdnPt_V4 :<br>
+ case Hexagon::LDriw_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::LDriw_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :<br>
+<br>
+// Coditional add<br>
+ case Hexagon::ADD_ri_cdnPt:<br>
+ case Hexagon::ADD_ri_cdnNotPt:<br>
+ case Hexagon::ADD_rr_cdnPt:<br>
+ case Hexagon::ADD_rr_cdnNotPt:<br>
+<br>
+ // Conditional logical operations<br>
+ case Hexagon::XOR_rr_cdnPt :<br>
+ case Hexagon::XOR_rr_cdnNotPt :<br>
+ case Hexagon::AND_rr_cdnPt :<br>
+ case Hexagon::AND_rr_cdnNotPt :<br>
+ case Hexagon::OR_rr_cdnPt :<br>
+ case Hexagon::OR_rr_cdnNotPt :<br>
+<br>
+ // Conditonal subtract<br>
+ case Hexagon::SUB_rr_cdnPt :<br>
+ case Hexagon::SUB_rr_cdnNotPt :<br>
+<br>
+ // Conditional combine<br>
+ case Hexagon::COMBINE_rr_cdnPt :<br>
+ case Hexagon::COMBINE_rr_cdnNotPt :<br>
+<br>
+ // Conditional shift operations<br>
+ case Hexagon::ASLH_cdnPt_V4:<br>
+ case Hexagon::ASLH_cdnNotPt_V4:<br>
+ case Hexagon::ASRH_cdnPt_V4:<br>
+ case Hexagon::ASRH_cdnNotPt_V4:<br>
+ case Hexagon::SXTB_cdnPt_V4:<br>
+ case Hexagon::SXTB_cdnNotPt_V4:<br>
+ case Hexagon::SXTH_cdnPt_V4:<br>
+ case Hexagon::SXTH_cdnNotPt_V4:<br>
+ case Hexagon::ZXTB_cdnPt_V4:<br>
+ case Hexagon::ZXTB_cdnNotPt_V4:<br>
+ case Hexagon::ZXTH_cdnPt_V4:<br>
+ case Hexagon::ZXTH_cdnNotPt_V4:<br>
+<br>
+ // Conditional stores<br>
+ case Hexagon::STrib_imm_cdnPt_V4 :<br>
+ case Hexagon::STrib_imm_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_cdnPt_V4 :<br>
+ case Hexagon::STrib_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrib_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::POST_STbri_cdnPt_V4 :<br>
+ case Hexagon::POST_STbri_cdnNotPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :<br>
+<br>
+ // Store doubleword conditionally<br>
+ case Hexagon::STrid_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrid_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STrid_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_STdri_cdnPt_V4 :<br>
+ case Hexagon::POST_STdri_cdnNotPt_V4 :<br>
+<br>
+ // Store halfword conditionally<br>
+ case Hexagon::STrih_cdnPt_V4 :<br>
+ case Hexagon::STrih_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_indexed_cdnPt_V4 :<br>
+ case Hexagon::STrih_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_imm_cdnPt_V4 :<br>
+ case Hexagon::STrih_imm_cdnNotPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_SThri_cdnPt_V4 :<br>
+ case Hexagon::POST_SThri_cdnNotPt_V4 :<br>
+<br>
+ // Store word conditionally<br>
+ case Hexagon::STriw_cdnPt_V4 :<br>
+ case Hexagon::STriw_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_indexed_cdnPt_V4 :<br>
+ case Hexagon::STriw_indexed_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_imm_cdnPt_V4 :<br>
+ case Hexagon::STriw_imm_cdnNotPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cdnPt_V4 :<br>
+ case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :<br>
+ case Hexagon::POST_STwri_cdnPt_V4 :<br>
+ case Hexagon::POST_STwri_cdnNotPt_V4 :<br>
+<br>
+ case Hexagon::LDd_GP_cdnPt_V4:<br>
+ case Hexagon::LDd_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDb_GP_cdnPt_V4:<br>
+ case Hexagon::LDb_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDub_GP_cdnPt_V4:<br>
+ case Hexagon::LDub_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDh_GP_cdnPt_V4:<br>
+ case Hexagon::LDh_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDuh_GP_cdnPt_V4:<br>
+ case Hexagon::LDuh_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDw_GP_cdnPt_V4:<br>
+ case Hexagon::LDw_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDrid_GP_cdnPt_V4:<br>
+ case Hexagon::LDrid_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDrib_GP_cdnPt_V4:<br>
+ case Hexagon::LDrib_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDriub_GP_cdnPt_V4:<br>
+ case Hexagon::LDriub_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDrih_GP_cdnPt_V4:<br>
+ case Hexagon::LDrih_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDriuh_GP_cdnPt_V4:<br>
+ case Hexagon::LDriuh_GP_cdnNotPt_V4:<br>
+ case Hexagon::LDriw_GP_cdnPt_V4:<br>
+ case Hexagon::LDriw_GP_cdnNotPt_V4:<br>
+<br>
+ case Hexagon::STrid_GP_cdnPt_V4:<br>
+ case Hexagon::STrid_GP_cdnNotPt_V4:<br>
+ case Hexagon::STrib_GP_cdnPt_V4:<br>
+ case Hexagon::STrib_GP_cdnNotPt_V4:<br>
+ case Hexagon::STrih_GP_cdnPt_V4:<br>
+ case Hexagon::STrih_GP_cdnNotPt_V4:<br>
+ case Hexagon::STriw_GP_cdnPt_V4:<br>
+ case Hexagon::STriw_GP_cdnNotPt_V4:<br>
+ case Hexagon::STd_GP_cdnPt_V4:<br>
+ case Hexagon::STd_GP_cdnNotPt_V4:<br>
+ case Hexagon::STb_GP_cdnPt_V4:<br>
+ case Hexagon::STb_GP_cdnNotPt_V4:<br>
+ case Hexagon::STh_GP_cdnPt_V4:<br>
+ case Hexagon::STh_GP_cdnNotPt_V4:<br>
+ case Hexagon::STw_GP_cdnPt_V4:<br>
+ case Hexagon::STw_GP_cdnNotPt_V4:<br>
+<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,<br>
+ const HexagonInstrInfo *QII) {<br>
+ assert(QII->isPostIncrement(MI) && "Not a post increment operation.");<br>
+#ifndef NDEBUG<br>
+ // Post Increment means duplicates. Use dense map to find duplicates in the<br>
+ // list. Caution: Densemap initializes with the minimum of 64 buckets,<br>
+ // whereas there are at most 5 operands in the post increment.<br>
+ DenseMap<unsigned, unsigned> DefRegsSet;<br>
+ for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)<br>
+ if (MI->getOperand(opNum).isReg() &&<br>
+ MI->getOperand(opNum).isDef()) {<br>
+ DefRegsSet[MI->getOperand(opNum).getReg()] = 1;<br>
+ }<br>
+<br>
+ for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)<br>
+ if (MI->getOperand(opNum).isReg() &&<br>
+ MI->getOperand(opNum).isUse()) {<br>
+ if (DefRegsSet[MI->getOperand(opNum).getReg()]) {<br>
+ return MI->getOperand(opNum);<br>
+ }<br>
+ }<br>
+#else<br>
+ if (MI->getDesc().mayLoad()) {<br>
+ // The 2nd operand is always the post increment operand in load.<br>
+ assert(MI->getOperand(1).isReg() &&<br>
+ "Post increment operand has be to a register.");<br>
+ return (MI->getOperand(1));<br>
+ }<br>
+ if (MI->getDesc().mayStore()) {<br>
+ // The 1st operand is always the post increment operand in store.<br>
+ assert(MI->getOperand(0).isReg() &&<br>
+ "Post increment operand has be to a register.");<br>
+ return (MI->getOperand(0));<br>
+ }<br>
+#endif<br>
+ // we should never come here.<br>
+ assert(0 && "mayLoad or mayStore not set for Post Increment operation");<br>
+<br>
+ // return *some value* to avoid compiler warning<br>
+ return MI->getOperand(0);<br>
+}<br>
+<br>
+// get the value being stored<br>
+static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {<br>
+ // value being stored is always the last operand.<br>
+ return (MI->getOperand(MI->getNumOperands()-1));<br>
+}<br>
+<br>
+// can be new value store?<br>
+// Following restrictions are to be respected in convert a store into<br>
+// a new value store.<br>
+// 1. If an instruction uses auto-increment, its address register cannot<br>
+// be a new-value register. Arch Spec 5.4.2.1<br>
+// 2. If an instruction uses absolute-set addressing mode,<br>
+// its address register cannot be a new-value register.<br>
+// Arch Spec 5.4.2.1.TODO: This is not enabled as<br>
+// as absolute-set address mode patters are not implemented.<br>
+// 3. If an instruction produces a 64-bit result, its registers cannot be used<br>
+// as new-value registers. Arch Spec 5.4.2.2.<br>
+// 4. If the instruction that sets a new-value register is conditional, then<br>
+// the instruction that uses the new-value register must also be conditional,<br>
+// and both must always have their predicates evaluate identically.<br>
+// Arch Spec 5.4.2.3.<br>
+// 5. There is an implied restriction of a packet can not have another store,<br>
+// if there is a new value store in the packet. Corollary, if there is<br>
+// already a store in a packet, there can not be a new value store.<br>
+// Arch Spec: 3.4.4.2<br>
+bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,<br>
+ MachineInstr *PacketMI, unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit)<br>
+{<br>
+ // Make sure we are looking at the store<br>
+ if (!IsNewifyStore(MI))<br>
+ return false;<br>
+<br>
+ // Make sure there is dependency and can be new value'ed<br>
+ if (GetStoreValueOperand(MI).isReg() &&<br>
+ GetStoreValueOperand(MI).getReg() != DepReg)<br>
+ return false;<br>
+<br>
+ const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();<br>
+ const MCInstrDesc& MCID = PacketMI->getDesc();<br>
+ // first operand is always the result<br>
+<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI);<br>
+<br>
+ // if there is already an store in the packet, no can do new value store<br>
+ // Arch Spec 3.4.4.2.<br>
+ for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),<br>
+ VE = CurrentPacketMIs.end();<br>
+ (VI != VE); ++VI) {<br>
+ SUnit* PacketSU = MIToSUnit[*VI];<br>
+ if (PacketSU->getInstr()->getDesc().mayStore() ||<br>
+ // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,<br>
+ // then we don't need this<br>
+ PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||<br>
+ PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)<br>
+ return false;<br>
+ }<br>
+<br>
+ if (PacketRC == Hexagon::DoubleRegsRegisterClass) {<br>
+ // new value store constraint: double regs can not feed into new value store<br>
+ // arch spec section: 5.4.2.2<br>
+ return false;<br>
+ }<br>
+<br>
+ // Make sure it's NOT the post increment register that we are going to<br>
+ // new value.<br>
+ if (QII->isPostIncrement(MI) &&<br>
+ MI->getDesc().mayStore() &&<br>
+ GetPostIncrementOperand(MI, QII).getReg() == DepReg) {<br>
+ return false;<br>
+ }<br>
+<br>
+ if (QII->isPostIncrement(PacketMI) &&<br>
+ PacketMI->getDesc().mayLoad() &&<br>
+ GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {<br>
+ // if source is post_inc, or absolute-set addressing,<br>
+ // it can not feed into new value store<br>
+ // r3 = memw(r2++#4)<br>
+ // memw(r30 + #-1404) = r2.new -> can not be new value store<br>
+ // arch spec section: 5.4.2.1<br>
+ return false;<br>
+ }<br>
+<br>
+ // If the source that feeds the store is predicated, new value store must also be<br>
+ // also predicated.<br>
+ if (QII->isPredicated(PacketMI)) {<br>
+ if (!QII->isPredicated(MI))<br>
+ return false;<br>
+<br>
+ // Check to make sure that they both will have their predicates<br>
+ // evaluate identically<br>
+ unsigned predRegNumSrc;<br>
+ unsigned predRegNumDst;<br>
+ const TargetRegisterClass* predRegClass;<br>
+<br>
+ // Get predicate register used in the source instruction<br>
+ for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {<br>
+ if ( PacketMI->getOperand(opNum).isReg())<br>
+ predRegNumSrc = PacketMI->getOperand(opNum).getReg();<br>
+ predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);<br>
+ if (predRegClass == Hexagon::PredRegsRegisterClass) {<br>
+ break;<br>
+ }<br>
+ }<br>
+ assert ((predRegClass == Hexagon::PredRegsRegisterClass ) &&<br>
+ ("predicate register not found in a predicated PacketMI instruction"));<br>
+<br>
+ // Get predicate register used in new-value store instruction<br>
+ for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {<br>
+ if ( MI->getOperand(opNum).isReg())<br>
+ predRegNumDst = MI->getOperand(opNum).getReg();<br>
+ predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);<br>
+ if (predRegClass == Hexagon::PredRegsRegisterClass) {<br>
+ break;<br>
+ }<br>
+ }<br>
+ assert ((predRegClass == Hexagon::PredRegsRegisterClass ) &&<br>
+ ("predicate register not found in a predicated MI instruction"));<br>
+<br>
+ // New-value register producer and user (store) need to satisfy these<br>
+ // constraints:<br>
+ // 1) Both instructions should be predicated on the same register.<br>
+ // 2) If producer of the new-value register is .new predicated then store<br>
+ // should also be .new predicated and if producer is not .new predicated<br>
+ // then store should not be .new predicated.<br>
+ // 3) Both new-value register producer and user should have same predicate<br>
+ // sense, i.e, either both should be negated or both should be none negated.<br>
+<br>
+ if (( predRegNumDst != predRegNumSrc) ||<br>
+ isDotNewInst(PacketMI) != isDotNewInst(MI) ||<br>
+ GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {<br>
+ return false;<br>
+ }<br>
+ }<br>
+<br>
+ // Make sure that other than the new-value register no other store instruction<br>
+ // register has been modified in the same packet. Predicate registers can be<br>
+ // modified by they should not be modified between the producer and the store<br>
+ // instruction as it will make them both conditional on different values.<br>
+ // We already know this to be true for all the instructions before and<br>
+ // including PacketMI. Howerver, we need to perform the check for the<br>
+ // remaining instructions in the packet.<br>
+<br>
+ std::vector<MachineInstr*>::iterator VI;<br>
+ std::vector<MachineInstr*>::iterator VE;<br>
+ unsigned StartCheck = 0;<br>
+<br>
+ for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();<br>
+ (VI != VE); ++VI) {<br>
+ SUnit* TempSU = MIToSUnit[*VI];<br>
+ MachineInstr* TempMI = TempSU->getInstr();<br>
+<br>
+ // Following condition is true for all the instructions until PacketMI is<br>
+ // reached (StartCheck is set to 0 before the for loop).<br>
+ // StartCheck flag is 1 for all the instructions after PacketMI.<br>
+ if (TempMI != PacketMI && !StartCheck) // start processing only after<br>
+ continue; // encountering PacketMI<br>
+<br>
+ StartCheck = 1;<br>
+ if (TempMI == PacketMI) // We don't want to check PacketMI for dependence<br>
+ continue;<br>
+<br>
+ for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {<br>
+ if (MI->getOperand(opNum).isReg() &&<br>
+ TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), QRI))<br>
+ return false;<br>
+ }<br>
+ }<br>
+<br>
+ // Make sure that for non POST_INC stores:<br>
+ // 1. The only use of reg is DepReg and no other registers.<br>
+ // This handles V4 base+index registers.<br>
+ // The following store can not be dot new.<br>
+ // Eg. r0 = add(r0, #3)a<br>
+ // memw(r1+r0<<#2) = r0<br>
+ if (!QII->isPostIncrement(MI) &&<br>
+ GetStoreValueOperand(MI).isReg() &&<br>
+ GetStoreValueOperand(MI).getReg() == DepReg) {<br>
+ for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {<br>
+ if (MI->getOperand(opNum).isReg() &&<br>
+ MI->getOperand(opNum).getReg() == DepReg) {<br>
+ return false;<br>
+ }<br>
+ }<br>
+ // 2. If data definition is because of implicit definition of the register,<br>
+ // do not newify the store. Eg.<br>
+ // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def><br>
+ // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]<br>
+ for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {<br>
+ if (PacketMI->getOperand(opNum).isReg() &&<br>
+ PacketMI->getOperand(opNum).getReg() == DepReg &&<br>
+ PacketMI->getOperand(opNum).isDef() &&<br>
+ PacketMI->getOperand(opNum).isImplicit()) {<br>
+ return false;<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ // Can be dot new store.<br>
+ return true;<br>
+}<br>
+<br>
+// can this MI to promoted to either<br>
+// new value store or new value jump<br>
+bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,<br>
+ SUnit *PacketSU, unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit,<br>
+ MachineBasicBlock::iterator &MII)<br>
+{<br>
+<br>
+ const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();<br>
+ if (!QRI->Subtarget.hasV4TOps() ||<br>
+ !IsNewifyStore(MI))<br>
+ return false;<br>
+<br>
+ MachineInstr *PacketMI = PacketSU->getInstr();<br>
+<br>
+ // Check to see the store can be new value'ed.<br>
+ if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))<br>
+ return true;<br>
+<br>
+ // Check to see the compare/jump can be new value'ed.<br>
+ // This is done as a pass on its own. Don't need to check it here.<br>
+ return false;<br>
+}<br>
+<br>
+// Check to see if an instruction can be dot new<br>
+// There are three kinds.<br>
+// 1. dot new on predicate - V2/V3/V4<br>
+// 2. dot new on stores NV/ST - V4<br>
+// 3. dot new on jump NV/J - V4 -- This is generated in a pass.<br>
+bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,<br>
+ SUnit *PacketSU, unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit,<br>
+ MachineBasicBlock::iterator &MII,<br>
+ const TargetRegisterClass* RC )<br>
+{<br>
+ // already a dot new instruction<br>
+ if (isDotNewInst(MI) && !IsNewifyStore(MI))<br>
+ return false;<br>
+<br>
+ if (!isNewifiable(MI))<br>
+ return false;<br>
+<br>
+ // predicate .new<br>
+ if (RC == Hexagon::PredRegsRegisterClass && isCondInst(MI))<br>
+ return true;<br>
+ else if (RC != Hexagon::PredRegsRegisterClass &&<br>
+ !IsNewifyStore(MI)) // MI is not a new-value store<br>
+ return false;<br>
+ else {<br>
+ // Create a dot new machine instruction to see if resources can be<br>
+ // allocated. If not, bail out now.<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ int NewOpcode = GetDotNewOp(MI->getOpcode());<br>
+ const MCInstrDesc &desc = QII->get(NewOpcode);<br>
+ DebugLoc dl;<br>
+ MachineInstr *NewMI = MI->getParent()->getParent()->CreateMachineInstr(desc, dl);<br>
+ bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);<br>
+ MI->getParent()->getParent()->DeleteMachineInstr(NewMI);<br>
+<br>
+ if (!ResourcesAvailable)<br>
+ return false;<br>
+<br>
+ // new value store only<br>
+ // new new value jump generated as a passes<br>
+ if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {<br>
+ return false;<br>
+ }<br>
+ }<br>
+ return true;<br>
+}<br>
+<br>
+// Go through the packet instructions and search for anti dependency<br>
+// between them and DepReg from MI<br>
+// Consider this case:<br>
+// Trying to add<br>
+// a) %R1<def> = TFRI_cdNotPt %P3, 2<br>
+// to this packet:<br>
+// {<br>
+// b) %P0<def> = OR_pp %P3<kill>, %P0<kill><br>
+// c) %P3<def> = TFR_PdRs %R23<br>
+// d) %R1<def> = TFRI_cdnPt %P3, 4<br>
+// }<br>
+// The P3 from a) and d) will be complements after<br>
+// a)'s P3 is converted to .new form<br>
+// Anti Dep between c) and b) is irrelevant for this case<br>
+bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,<br>
+ unsigned DepReg,<br>
+ std::map <MachineInstr*, SUnit*> MIToSUnit) {<br>
+<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ SUnit* PacketSUDep = MIToSUnit[MI];<br>
+<br>
+ for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),<br>
+ VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {<br>
+<br>
+ // We only care for dependencies to predicated instructions<br>
+ if(!QII->isPredicated(*VIN)) continue;<br>
+<br>
+ // Scheduling Unit for current insn in the packet<br>
+ SUnit* PacketSU = MIToSUnit[*VIN];<br>
+<br>
+ // Look at dependencies between current members of the packet<br>
+ // and predicate defining instruction MI.<br>
+ // Make sure that dependency is on the exact register<br>
+ // we care about.<br>
+ if (PacketSU->isSucc(PacketSUDep)) {<br>
+ for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {<br>
+ if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&<br>
+ (PacketSU->Succs[i].getKind() == SDep::Anti) &&<br>
+ (PacketSU->Succs[i].getReg() == DepReg)) {<br>
+ return true;<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ return false;<br>
+}<br>
+<br>
+<br>
+// Given two predicated instructions, this function detects whether<br>
+// the predicates are complements<br>
+bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,<br>
+ MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {<br>
+<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+ // Currently can only reason about conditional transfers<br>
+ if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {<br>
+ return false;<br>
+ }<br>
+<br>
+ // Scheduling unit for candidate<br>
+ SUnit* SU = MIToSUnit[MI1];<br>
+<br>
+ // One corner case deals with the following scenario:<br>
+ // Trying to add<br>
+ // a) %R24<def> = TFR_cPt %P0, %R25<br>
+ // to this packet:<br>
+ //<br>
+ // {<br>
+ // b) %R25<def> = TFR_cNotPt %P0, %R24<br>
+ // c) %P0<def> = CMPEQri %R26, 1<br>
+ // }<br>
+ //<br>
+ // On general check a) and b) are complements, but<br>
+ // presence of c) will convert a) to .new form, and<br>
+ // then it is not a complement<br>
+ // We attempt to detect it by analyzing existing<br>
+ // dependencies in the packet<br>
+<br>
+ // Analyze relationships between all existing members of the packet.<br>
+ // Look for Anti dependecy on the same predicate reg<br>
+ // as used in the candidate<br>
+ for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),<br>
+ VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {<br>
+<br>
+ // Scheduling Unit for current insn in the packet<br>
+ SUnit* PacketSU = MIToSUnit[*VIN];<br>
+<br>
+ // If this instruction in the packet is succeeded by the candidate...<br>
+ if (PacketSU->isSucc(SU)) {<br>
+ for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {<br>
+ // The corner case exist when there is true data<br>
+ // dependency between candidate and one of current<br>
+ // packet members, this dep is on predicate reg, and<br>
+ // there already exist anti dep on the same pred in<br>
+ // the packet.<br>
+ if (PacketSU->Succs[i].getSUnit() == SU &&<br>
+ Hexagon::PredRegsRegisterClass->contains(<br>
+ PacketSU->Succs[i].getReg()) &&<br>
+ PacketSU->Succs[i].getKind() == SDep::Data &&<br>
+ // Here I know that *VIN is predicate setting instruction<br>
+ // with true data dep to candidate on the register<br>
+ // we care about - c) in the above example.<br>
+ // Now I need to see if there is an anti dependency<br>
+ // from c) to any other instruction in the<br>
+ // same packet on the pred reg of interest<br>
+ RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),<br>
+ MIToSUnit)) {<br>
+ return false;<br>
+ }<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ // If the above case does not apply, check regular<br>
+ // complement condition.<br>
+ // Check that the predicate register is the same and<br>
+ // that the predicate sense is different<br>
+ // We also need to differentiate .old vs. .new:<br>
+ // !p0 is not complimentary to p0.new<br>
+ return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&<br>
+ (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&<br>
+ (isDotNewInst(MI1) == isDotNewInst(MI2)));<br>
+}<br>
+<br>
+// initPacketizerState - Initialize packetizer flags<br>
+void HexagonPacketizerList::initPacketizerState(void) {<br>
+<br>
+ Dependence = false;<br>
+ PromotedToDotNew = false;<br>
+ GlueToNewValueJump = false;<br>
+ GlueAllocframeStore = false;<br>
+ FoundSequentialDependence = false;<br>
+<br>
+ return;<br>
+}<br>
+<br>
+// ignorePseudoInstruction - Ignore bundling of pseudo instructions.<br>
+bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,<br>
+ MachineBasicBlock *MBB) {<br>
+ if (MI->isDebugValue())<br>
+ return true;<br>
+<br>
+ // We must print out inline assembly<br>
+ if (MI->isInlineAsm())<br>
+ return false;<br>
+<br>
+ // We check if MI has any functional units mapped to it.<br>
+ // If it doesn't, we ignore the instruction.<br>
+ const MCInstrDesc& TID = MI->getDesc();<br>
+ unsigned SchedClass = TID.getSchedClass();<br>
+ const InstrStage* IS = ResourceTracker->getInstrItins()->beginStage(SchedClass);<br>
+ unsigned FuncUnits = IS->getUnits();<br>
+ return !FuncUnits;<br>
+}<br>
+<br>
+// isSoloInstruction: - Returns true for instructions that must be<br>
+// scheduled in their own packet.<br>
+bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {<br>
+<br>
+ if (MI->isInlineAsm())<br>
+ return true;<br>
+<br>
+ if (MI->isEHLabel())<br>
+ return true;<br>
+<br>
+ // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:<br>
+ // trap, pause, barrier, icinva, isync, and syncht are solo instructions.<br>
+ // They must not be grouped with other instructions in a packet.<br>
+ if (IsSchedBarrier(MI))<br>
+ return true;<br>
+<br>
+ return false;<br>
+}<br>
+<br>
+// isLegalToPacketizeTogether:<br>
+// SUI is the current instruction that is out side of the current packet.<br>
+// SUJ is the current instruction inside the current packet against which that<br>
+// SUI will be packetized.<br>
+bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {<br>
+ MachineInstr *I = SUI->getInstr();<br>
+ MachineInstr *J = SUJ->getInstr();<br>
+ assert(I && J && "Unable to packetize null instruction!");<br>
+<br>
+ const MCInstrDesc &MCIDI = I->getDesc();<br>
+ const MCInstrDesc &MCIDJ = J->getDesc();<br>
+<br>
+ MachineBasicBlock::iterator II = I;<br>
+<br>
+ const unsigned FrameSize = MF.getFrameInfo()->getStackSize();<br>
+ const HexagonRegisterInfo* QRI = (const HexagonRegisterInfo *) TM.getRegisterInfo();<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+<br>
+ // Inline asm cannot go in the packet.<br>
+ if (I->getOpcode() == Hexagon::INLINEASM)<br>
+ assert(0 && "Should not meet inline asm here!");<br>
+<br>
+ if (isSoloInstruction(I))<br>
+ assert(0 && "Should not meet solo instr here!");<br>
+<br>
+ // A save callee-save register function call can only be in a packet<br>
+ // with instructions that don't write to the callee-save registers.<br>
+ if ((QII->isSaveCalleeSavedRegsCall(I) &&<br>
+ DoesModifyCalleeSavedReg(J, QRI)) ||<br>
+ (QII->isSaveCalleeSavedRegsCall(J) &&<br>
+ DoesModifyCalleeSavedReg(I, QRI))) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+ // Two control flow instructions cannot go in the same packet.<br>
+ if (IsControlFlow(I) && IsControlFlow(J)) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+ // A LoopN instruction cannot appear in the same packet as a jump or call.<br>
+ if (IsLoopN(I) && ( IsDirectJump(J)<br>
+ || MCIDJ.isCall()<br>
+ || QII->isDeallocRet(J))) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+ if (IsLoopN(J) && ( IsDirectJump(I)<br>
+ || MCIDI.isCall()<br>
+ || QII->isDeallocRet(I))) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+ // dealloc_return cannot appear in the same packet as a conditional or<br>
+ // unconditional jump.<br>
+ if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()<br>
+ || MCIDJ.isCall()<br>
+ || MCIDJ.isBarrier())) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+<br>
+ // V4 allows dual store. But does not allow second store, if the<br>
+ // first store is not in SLOT0. New value store, new value jump,<br>
+ // dealloc_return and memop always take SLOT0.<br>
+ // Arch spec 3.4.4.2<br>
+ if (QRI->Subtarget.hasV4TOps()) {<br>
+<br>
+ if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+ if ( (QII->isMemOp(J) && MCIDI.mayStore())<br>
+ || (MCIDJ.mayStore() && QII->isMemOp(I))<br>
+ || (QII->isMemOp(J) && QII->isMemOp(I))) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+ //if dealloc_return<br>
+ if (MCIDJ.mayStore() && QII->isDeallocRet(I)){<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+<br>
+ // If an instruction feeds new value jump, glue it.<br>
+ MachineBasicBlock::iterator NextMII = I;<br>
+ ++NextMII;<br>
+ MachineInstr *NextMI = NextMII;<br>
+<br>
+ if (QII->isNewValueJump(NextMI)) {<br>
+<br>
+ bool secondRegMatch = false;<br>
+ bool maintainNewValueJump = false;<br>
+<br>
+ if (NextMI->getOperand(1).isReg() &&<br>
+ I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {<br>
+ secondRegMatch = true;<br>
+ maintainNewValueJump = true;<br>
+ }<br>
+<br>
+ if (!secondRegMatch &&<br>
+ I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {<br>
+ maintainNewValueJump = true;<br>
+ }<br>
+<br>
+ for (std::vector<MachineInstr*>::iterator<br>
+ VI = CurrentPacketMIs.begin(),<br>
+ VE = CurrentPacketMIs.end();<br>
+ (VI != VE && maintainNewValueJump); ++VI) {<br>
+ SUnit* PacketSU = MIToSUnit[*VI];<br>
+<br>
+ // NVJ can not be part of the dual jump - Arch Spec: section 7.8<br>
+ if (PacketSU->getInstr()->getDesc().isCall()) {<br>
+ Dependence = true;<br>
+ break;<br>
+ }<br>
+ // Validate<br>
+ // 1. Packet does not have a store in it.<br>
+ // 2. If the first operand of the nvj is newified, and the second<br>
+ // operand is also a reg, it (second reg) is not defined in<br>
+ // the same packet.<br>
+ // 3. If the second operand of the nvj is newified, (which means<br>
+ // first operand is also a reg), first reg is not defined in<br>
+ // the same packet.<br>
+ if (PacketSU->getInstr()->getDesc().mayStore() ||<br>
+ PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||<br>
+ // Check #2.<br>
+ (!secondRegMatch && NextMI->getOperand(1).isReg() &&<br>
+ PacketSU->getInstr()->modifiesRegister(<br>
+ NextMI->getOperand(1).getReg(), QRI)) ||<br>
+ // Check #3.<br>
+ (secondRegMatch &&<br>
+ PacketSU->getInstr()->modifiesRegister(<br>
+ NextMI->getOperand(0).getReg(), QRI))) {<br>
+ Dependence = true;<br>
+ break;<br>
+ }<br>
+ }<br>
+ if (!Dependence)<br>
+ GlueToNewValueJump = true;<br>
+ else<br>
+ return false;<br>
+ }<br>
+ }<br>
+<br>
+ if (SUJ->isSucc(SUI)) {<br>
+ for (unsigned i = 0;<br>
+ (i < SUJ->Succs.size()) && !FoundSequentialDependence;<br>
+ ++i) {<br>
+<br>
+ if (SUJ->Succs[i].getSUnit() != SUI) {<br>
+ continue;<br>
+ }<br>
+<br>
+ SDep::Kind DepType = SUJ->Succs[i].getKind();<br>
+<br>
+ // For direct calls:<br>
+ // Ignore register dependences for call instructions for<br>
+ // packetization purposes except for those due to r31 and<br>
+ // predicate registers.<br>
+ //<br>
+ // For indirect calls:<br>
+ // Same as direct calls + check for true dependences to the register<br>
+ // used in the indirect call.<br>
+ //<br>
+ // We completely ignore Order dependences for call instructions<br>
+ //<br>
+ // For returns:<br>
+ // Ignore register dependences for return instructions like jumpr,<br>
+ // dealloc return unless we have dependencies on the explicit uses<br>
+ // of the registers used by jumpr (like r31) or dealloc return<br>
+ // (like r29 or r30).<br>
+ //<br>
+ // TODO: Currently, jumpr is handling only return of r31. So, the<br>
+ // following logic (specificaly IsCallDependent) is working fine.<br>
+ // We need to enable jumpr for register other than r31 and then,<br>
+ // we need to rework the last part, where it handles indirect call<br>
+ // of that (IsCallDependent) function. Bug 6216 is opened for this.<br>
+ //<br>
+ unsigned DepReg;<br>
+ const TargetRegisterClass* RC;<br>
+ if (DepType == SDep::Data) {<br>
+ DepReg = SUJ->Succs[i].getReg();<br>
+ RC = QRI->getMinimalPhysRegClass(DepReg);<br>
+ }<br>
+ if ((MCIDI.isCall() || MCIDI.isReturn()) &&<br>
+ (!IsRegDependence(DepType) ||<br>
+ !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {<br>
+ /* do nothing */<br>
+ }<br>
+<br>
+ // For instructions that can be promoted to dot-new, try to promote.<br>
+ else if ((DepType == SDep::Data) &&<br>
+ CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&<br>
+ PromoteToDotNew(I, DepType, II, RC)) {<br>
+ PromotedToDotNew = true;<br>
+ /* do nothing */<br>
+ }<br>
+<br>
+ else if ((DepType == SDep::Data) &&<br>
+ (QII->isNewValueJump(I))) {<br>
+ /* do nothing */<br>
+ }<br>
+<br>
+ // For predicated instructions, if the predicates are complements<br>
+ // then there can be no dependence.<br>
+ else if (QII->isPredicated(I) &&<br>
+ QII->isPredicated(J) &&<br>
+ ArePredicatesComplements(I, J, MIToSUnit)) {<br>
+ /* do nothing */<br>
+<br>
+ }<br>
+ else if (IsDirectJump(I) &&<br>
+ !MCIDJ.isBranch() &&<br>
+ !MCIDJ.isCall() &&<br>
+ (DepType == SDep::Order)) {<br>
+ // Ignore Order dependences between unconditional direct branches<br>
+ // and non-control-flow instructions<br>
+ /* do nothing */<br>
+ }<br>
+ else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&<br>
+ (DepType != SDep::Output)) {<br>
+ // Ignore all dependences for jumps except for true and output<br>
+ // dependences<br>
+ /* do nothing */<br>
+ }<br>
+<br>
+ // Ignore output dependences due to superregs. We can<br>
+ // write to two different subregisters of R1:0 for instance<br>
+ // in the same cycle<br>
+ //<br>
+<br>
+ //<br>
+ // Let the<br>
+ // If neither I nor J defines DepReg, then this is a<br>
+ // superfluous output dependence. The dependence must be of the<br>
+ // form:<br>
+ // R0 = ...<br>
+ // R1 = ...<br>
+ // and there is an output dependence between the two instructions<br>
+ // with<br>
+ // DepReg = D0<br>
+ // We want to ignore these dependences.<br>
+ // Ideally, the dependence constructor should annotate such<br>
+ // dependences. We can then avoid this relatively expensive check.<br>
+ //<br>
+ else if (DepType == SDep::Output) {<br>
+ // DepReg is the register that's responsible for the dependence.<br>
+ unsigned DepReg = SUJ->Succs[i].getReg();<br>
+<br>
+ // Check if I and J really defines DepReg.<br>
+ if (I->definesRegister(DepReg) ||<br>
+ J->definesRegister(DepReg)) {<br>
+ FoundSequentialDependence = true;<br>
+ break;<br>
+ }<br>
+ }<br>
+<br>
+ // We ignore Order dependences for<br>
+ // 1. Two loads unless they are volatile.<br>
+ // 2. Two stores in V4 unless they are volatile.<br>
+ else if ((DepType == SDep::Order) &&<br>
+ !I->hasVolatileMemoryRef() &&<br>
+ !J->hasVolatileMemoryRef()) {<br>
+ if (QRI->Subtarget.hasV4TOps() &&<br>
+ // hexagonv4 allows dual store.<br>
+ MCIDI.mayStore() && MCIDJ.mayStore()) {<br>
+ /* do nothing */<br>
+ }<br>
+ // store followed by store-- not OK on V2<br>
+ // store followed by load -- not OK on all (OK if addresses<br>
+ // are not aliased)<br>
+ // load followed by store -- OK on all<br>
+ // load followed by load -- OK on all<br>
+ else if ( !MCIDJ.mayStore()) {<br>
+ /* do nothing */<br>
+ }<br>
+ else {<br>
+ FoundSequentialDependence = true;<br>
+ break;<br>
+ }<br>
+ }<br>
+<br>
+ // For V4, special case ALLOCFRAME. Even though there is dependency<br>
+ // between ALLOCAFRAME and subsequent store, allow it to be<br>
+ // packetized in a same packet. This implies that the store is using<br>
+ // caller's SP. Hense, offset needs to be updated accordingly.<br>
+ else if (DepType == SDep::Data<br>
+ && QRI->Subtarget.hasV4TOps()<br>
+ && J->getOpcode() == Hexagon::ALLOCFRAME<br>
+ && (I->getOpcode() == Hexagon::STrid<br>
+ || I->getOpcode() == Hexagon::STriw<br>
+ || I->getOpcode() == Hexagon::STrib)<br>
+ && I->getOperand(0).getReg() == QRI->getStackRegister()<br>
+ && QII->isValidOffset(I->getOpcode(),<br>
+ I->getOperand(1).getImm() -<br>
+ (FrameSize + HEXAGON_LRFP_SIZE)))<br>
+ {<br>
+ GlueAllocframeStore = true;<br>
+ // Since this store is to be glued with allocframe in the same<br>
+ // packet, it will use SP of the previous stack frame, i.e<br>
+ // caller's SP. Therefore, we need to recalculate offset according<br>
+ // to this change.<br>
+ I->getOperand(1).setImm(I->getOperand(1).getImm() -<br>
+ (FrameSize + HEXAGON_LRFP_SIZE));<br>
+ }<br>
+<br>
+ //<br>
+ // Skip over anti-dependences. Two instructions that are<br>
+ // anti-dependent can share a packet<br>
+ //<br>
+ else if (DepType != SDep::Anti) {<br>
+ FoundSequentialDependence = true;<br>
+ break;<br>
+ }<br>
+ }<br>
+<br>
+ if (FoundSequentialDependence) {<br>
+ Dependence = true;<br>
+ return false;<br>
+ }<br>
+ }<br>
+<br>
+ return true;<br>
+}<br>
+<br>
+// isLegalToPruneDependencies<br>
+bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {<br>
+ MachineInstr *I = SUI->getInstr();<br>
+ MachineInstr *J = SUJ->getInstr();<br>
+ assert(I && J && "Unable to packetize null instruction!");<br>
+<br>
+ const unsigned FrameSize = MF.getFrameInfo()->getStackSize();<br>
+<br>
+ if (Dependence) {<br>
+<br>
+ // Check if the instruction was promoted to a dot-new. If so, demote it<br>
+ // back into a dot-old.<br>
+ if (PromotedToDotNew) {<br>
+ DemoteToDotOld(I);<br>
+ }<br>
+<br>
+ // Check if the instruction (must be a store) was glued with an Allocframe<br>
+ // instruction. If so, restore its offset to its original value, i.e. use<br>
+ // curent SP instead of caller's SP.<br>
+ if (GlueAllocframeStore) {<br>
+ I->getOperand(1).setImm(I->getOperand(1).getImm() +<br>
+ FrameSize + HEXAGON_LRFP_SIZE);<br>
+ }<br>
+<br>
+ return false;<br>
+ }<br>
+ return true;<br>
+}<br>
+<br>
+MachineBasicBlock::iterator HexagonPacketizerList::addToPacket(MachineInstr *MI) {<br>
+<br>
+ MachineBasicBlock::iterator MII = MI;<br>
+ MachineBasicBlock *MBB = MI->getParent();<br>
+<br>
+ const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;<br>
+<br>
+ if (GlueToNewValueJump) {<br>
+<br>
+ ++MII;<br>
+ MachineInstr *nvjMI = MII;<br>
+ assert(ResourceTracker->canReserveResources(MI));<br>
+ ResourceTracker->reserveResources(MI);<br>
+ if (QII->isExtended(MI) &&<br>
+ !tryAllocateResourcesForConstExt(MI)) {<br>
+ endPacket(MBB, MI);<br>
+ ResourceTracker->reserveResources(MI);<br>
+ assert(canReserveResourcesForConstExt(MI) &&<br>
+ "Ensure that there is a slot");<br>
+ reserveResourcesForConstExt(MI);<br>
+ // Reserve resources for new value jump constant extender.<br>
+ assert(canReserveResourcesForConstExt(MI) &&<br>
+ "Ensure that there is a slot");<br>
+ reserveResourcesForConstExt(nvjMI);<br>
+ assert(ResourceTracker->canReserveResources(nvjMI) &&<br>
+ "Ensure that there is a slot");<br>
+<br>
+ } else if ( // Extended instruction takes two slots in the packet.<br>
+ // Try reserve and allocate 4-byte in the current packet first.<br>
+ (QII->isExtended(nvjMI)<br>
+ && (!tryAllocateResourcesForConstExt(nvjMI)<br>
+ || !ResourceTracker->canReserveResources(nvjMI)))<br>
+ || // For non-extended instruction, no need to allocate extra 4 bytes.<br>
+ (!QII->isExtended(nvjMI) && !ResourceTracker->canReserveResources(nvjMI)))<br>
+ {<br>
+ endPacket(MBB, MI);<br>
+ // A new and empty packet starts.<br>
+ // We are sure that the resources requirements can be satisfied.<br>
+ // Therefore, do not need to call "canReserveResources" anymore.<br>
+ ResourceTracker->reserveResources(MI);<br>
+ if (QII->isExtended(nvjMI))<br>
+ reserveResourcesForConstExt(nvjMI);<br>
+ }<br>
+ // Here, we are sure that "reserveResources" would succeed.<br>
+ ResourceTracker->reserveResources(nvjMI);<br>
+ CurrentPacketMIs.push_back(MI);<br>
+ CurrentPacketMIs.push_back(nvjMI);<br>
+ } else {<br>
+ if ( QII->isExtended(MI)<br>
+ && ( !tryAllocateResourcesForConstExt(MI)<br>
+ || !ResourceTracker->canReserveResources(MI)))<br>
+ {<br>
+ endPacket(MBB, MI);<br>
+ // Check if the instruction was promoted to a dot-new. If so, demote it<br>
+ // back into a dot-old<br>
+ if (PromotedToDotNew) {<br>
+ DemoteToDotOld(MI);<br>
+ }<br>
+ reserveResourcesForConstExt(MI);<br>
+ }<br>
+ // In case that "MI" is not an extended insn,<br>
+ // the resource availability has already been checked.<br>
+ ResourceTracker->reserveResources(MI);<br>
+ CurrentPacketMIs.push_back(MI);<br>
+ }<br>
+ return MII;<br>
+}<br>
+<br>
+//===----------------------------------------------------------------------===//<br>
+// Public Constructor Functions<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+FunctionPass *llvm::createHexagonPacketizer() {<br>
+ return new HexagonPacketizer();<br>
+}<br>
+<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp Thu Apr 12 16:06:38 2012<br>
@@ -15,6 +15,7 @@<br>
#include "Hexagon.h"<br>
#include "HexagonAsmPrinter.h"<br>
#include "HexagonInstPrinter.h"<br>
+#include "HexagonMCInst.h"<br>
#include "llvm/MC/MCInst.h"<br>
#include "llvm/MC/MCAsmInfo.h"<br>
#include "llvm/MC/MCExpr.h"<br>
@@ -37,20 +38,50 @@<br>
<br>
void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,<br>
StringRef Annot) {<br>
+ printInst((const HexagonMCInst*)(MI), O, Annot);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,<br>
+ StringRef Annot) {<br>
const char packetPadding[] = " ";<br>
const char startPacket = '{',<br>
endPacket = '}';<br>
// TODO: add outer HW loop when it's supported too.<br>
if (MI->getOpcode() == Hexagon::ENDLOOP0) {<br>
- MCInst Nop;<br>
+ // Ending a harware loop is different from ending an regular packet.<br>
+ assert(MI->isEndPacket() && "Loop end must also end the packet");<br>
<br>
- O << packetPadding << startPacket << '\n';<br>
- Nop.setOpcode(Hexagon::NOP);<br>
- printInstruction(&Nop, O);<br>
- O << packetPadding << endPacket;<br>
+ if (MI->isStartPacket()) {<br>
+ // There must be a packet to end a loop.<br>
+ // FIXME: when shuffling is always run, this shouldn't be needed.<br>
+ HexagonMCInst Nop;<br>
+ StringRef NoAnnot;<br>
+<br>
+ Nop.setOpcode (Hexagon::NOP);<br>
+ Nop.setStartPacket (MI->isStartPacket());<br>
+ printInst (&Nop, O, NoAnnot);<br>
+ }<br>
+<br>
+ // Close the packet.<br>
+ if (MI->isEndPacket())<br>
+ O << packetPadding << endPacket;<br>
+<br>
+ printInstruction(MI, O);<br>
+ }<br>
+ else {<br>
+ // Prefix the insn opening the packet.<br>
+ if (MI->isStartPacket())<br>
+ O << packetPadding << startPacket << '\n';<br>
+<br>
+ printInstruction(MI, O);<br>
+<br>
+ // Suffix the insn closing the packet.<br>
+ if (MI->isEndPacket())<br>
+ // Suffix the packet in a new line always, since the GNU assembler has<br>
+ // issues with a closing brace on the same line as CONST{32,64}.<br>
+ O << '\n' << packetPadding << endPacket;<br>
}<br>
<br>
- printInstruction(MI, O);<br>
printAnnotation(O, Annot);<br>
}<br>
<br>
@@ -69,18 +100,18 @@<br>
}<br>
}<br>
<br>
-void HexagonInstPrinter::printImmOperand<br>
- (const MCInst *MI, unsigned OpNo, raw_ostream &O) const {<br>
+void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
O << MI->getOperand(OpNo).getImm();<br>
}<br>
<br>
void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
+ raw_ostream &O) const {<br>
O << MI->getOperand(OpNo).getImm();<br>
}<br>
<br>
-void HexagonInstPrinter::printUnsignedImmOperand<br>
- (const MCInst *MI, unsigned OpNo, raw_ostream &O) const {<br>
+void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
O << MI->getOperand(OpNo).getImm();<br>
}<br>
<br>
@@ -89,13 +120,13 @@<br>
O << -MI->getOperand(OpNo).getImm();<br>
}<br>
<br>
-void HexagonInstPrinter::printNOneImmOperand<br>
- (const MCInst *MI, unsigned OpNo, raw_ostream &O) const {<br>
+void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
O << -1;<br>
}<br>
<br>
-void HexagonInstPrinter::printMEMriOperand<br>
- (const MCInst *MI, unsigned OpNo, raw_ostream &O) const {<br>
+void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
const MCOperand& MO0 = MI->getOperand(OpNo);<br>
const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>
<br>
@@ -103,8 +134,8 @@<br>
O << " + #" << MO1.getImm();<br>
}<br>
<br>
-void HexagonInstPrinter::printFrameIndexOperand<br>
- (const MCInst *MI, unsigned OpNo, raw_ostream &O) const {<br>
+void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
const MCOperand& MO0 = MI->getOperand(OpNo);<br>
const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h Thu Apr 12 16:06:38 2012<br>
@@ -14,6 +14,7 @@<br>
#ifndef HEXAGONINSTPRINTER_H<br>
#define HEXAGONINSTPRINTER_H<br>
<br>
+#include "HexagonMCInst.h"<br>
#include "llvm/MC/MCInstPrinter.h"<br>
<br>
namespace llvm {<br>
@@ -25,6 +26,7 @@<br>
: MCInstPrinter(MAI, MII, MRI) {}<br>
<br>
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);<br>
+ void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);<br>
virtual StringRef getOpcodeName(unsigned Opcode) const;<br>
void printInstruction(const MCInst *MI, raw_ostream &O);<br>
StringRef getRegName(unsigned RegNo) const;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=154616&r1=154615&r2=154616&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=154616&r1=154615&r2=154616&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Thu Apr 12 16:06:38 2012<br>
@@ -23,14 +23,41 @@<br>
/// instruction info tracks.<br>
///<br>
namespace HexagonII {<br>
-<br>
// *** The code below must match HexagonInstrFormat*.td *** //<br>
<br>
+ // Insn types.<br>
+ // *** Must match HexagonInstrFormat*.td ***<br>
+ enum Type {<br>
+ TypePSEUDO = 0,<br>
+ TypeALU32 = 1,<br>
+ TypeCR = 2,<br>
+ TypeJR = 3,<br>
+ TypeJ = 4,<br>
+ TypeLD = 5,<br>
+ TypeST = 6,<br>
+ TypeSYSTEM = 7,<br>
+ TypeXTYPE = 8,<br>
+ TypeMEMOP = 9,<br>
+ TypeNV = 10,<br>
+ TypePREFIX = 30, // Such as extenders.<br>
+ TypeMARKER = 31 // Such as end of a HW loop.<br>
+ };<br>
+<br>
+<br>
+<br>
// MCInstrDesc TSFlags<br>
+ // *** Must match HexagonInstrFormat*.td ***<br>
enum {<br>
+ // This 5-bit field describes the insn type.<br>
+ TypePos = 0,<br>
+ TypeMask = 0x1f,<br>
+<br>
+ // Solo instructions.<br>
+ SoloPos = 5,<br>
+ SoloMask = 0x1,<br>
<br>
// Predicated instructions.<br>
- PredicatedPos = 1,<br>
+ PredicatedPos = 6,<br>
PredicatedMask = 0x1<br>
};<br>
<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>