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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'>Commited in r153250 (mul.diff), r153251 (ldr.diff) and r153252
(addrmode3.diff).<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'><o:p> </o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'>Regards,<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'>Silviu<o:p></o:p></span></p>
<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";
color:#1F497D'><o:p> </o:p></span></p>
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<p class=MsoNormal><b><span lang=EN-US style='font-size:10.0pt;font-family:
"Tahoma","sans-serif"'>From:</span></b><span lang=EN-US style='font-size:10.0pt;
font-family:"Tahoma","sans-serif"'> Owen Anderson [mailto:owen@apple.com] <br>
<b>Sent:</b> 21 March 2012 23:14<br>
<b>To:</b> Jim Grosbach<br>
<b>Cc:</b> Silviu Baranga; Owen Anderson; llvm-commits@cs.uiuc.edu LLVM<br>
<b>Subject:</b> Re: [PATCH] Fix for some unpredictable instructions on ARM<o:p></o:p></span></p>
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<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Looks fine, other than a bit of trailing whitespace. ;-)<o:p></o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal>--Owen<o:p></o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal>On Mar 21, 2012, at 3:56 PM, Jim Grosbach <<a
href="mailto:grosbach@apple.com">grosbach@apple.com</a>> wrote:<o:p></o:p></p>
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<p class=MsoNormal>This all seems reasonable to me. Owen, what do you think?<o:p></o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal>-Jim<o:p></o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal>On Mar 21, 2012, at 3:47 AM, Silviu Baranga <<a
href="mailto:silbar01@arm.com">silbar01@arm.com</a>> wrote:<o:p></o:p></p>
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<br>
<o:p></o:p></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Hi,<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>The
ARM instructions:<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
STRD, STRH, LDRD, LDRH, LDRSH, LDRSB, LDRSBT, LDRHT, LDRSHT, MUL<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>have
some corner cases in which are unpredictable. In these cases the disassembler
should<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>still
disassemble the instructions instead of rejecting them.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>The
attached standalone patches fix this.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> -
addrmode3.diff – STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions.
The patch<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
modifies the C++ ARM disassembler code to add the checking conditions, which are<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
too complex to introduce with tablegen files.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> -
ldr.diff – LDRSBT, LDRHT and LDRSHT instructions. The patch introduces
a decoder<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
method because of the Rn == Rt unpredictability condition that is common to<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
all the instructions above.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>-
mul.diff - MUL instruction. The patch changes the TableGen description of
the MUL<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
Instruction in order to reflect the fact that the instruction is unpredictable
when<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>
either of the Rd, Rn or Rm register operands are the pc register.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>All
patches add regression tests for the modifications.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Please
review.<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Thanks,<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif"'>Silviu<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:13.5pt;font-family:"Helvetica","sans-serif"'><addrmode3.diff><ldr.diff><mul.diff><o:p></o:p></span></p>
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<p class=MsoNormal><o:p> </o:p></p>
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<p class=MsoNormal><o:p> </o:p></p>
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