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<p class=MsoNormal>Hi,<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>The ARM instructions:<o:p></o:p></p>
<p class=MsoNormal> STRD, STRH, LDRD, LDRH, LDRSH, LDRSB, LDRSBT,
LDRHT, LDRSHT, MUL<o:p></o:p></p>
<p class=MsoNormal>have some corner cases in which are unpredictable. In these cases
the disassembler should <o:p></o:p></p>
<p class=MsoNormal>still disassemble the instructions instead of rejecting them.<o:p></o:p></p>
<p class=MsoNormal>The attached standalone patches fix this.<o:p></o:p></p>
<p class=MsoNormal> <o:p></o:p></p>
<p class=MsoNormal> - addrmode3.diff – STRD, STRH, LDRD, LDRH, LDRSH
and LDRSB instructions. The patch<o:p></o:p></p>
<p class=MsoNormal>
modifies the C++ ARM disassembler code to add the checking conditions, which
are <o:p></o:p></p>
<p class=MsoNormal>
too complex to introduce with tablegen files. <o:p></o:p></p>
<p class=MsoNormal> - ldr.diff – LDRSBT, LDRHT and LDRSHT
instructions. The patch introduces a decoder <o:p></o:p></p>
<p class=MsoNormal>
method because of the Rn == Rt unpredictability condition that is common to<o:p></o:p></p>
<p class=MsoNormal>
all the instructions above. <o:p></o:p></p>
<p class=MsoNormal>- mul.diff - MUL instruction. The patch changes the TableGen
description of the MUL<o:p></o:p></p>
<p class=MsoNormal>
Instruction in order to reflect the fact that the instruction is unpredictable
when<o:p></o:p></p>
<p class=MsoNormal>
either of the Rd, Rn or Rm register operands are the pc register.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>All patches add regression tests for the modifications.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Please review.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Thanks,<o:p></o:p></p>
<p class=MsoNormal>Silviu<o:p></o:p></p>
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