<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Hi Jan,<div><br></div><div>The actual fixup bit twiddling is still the same between them. However, when a relocation should be generated is different. At least on Darwin, we always want a relocation for BL/BLX, but we don't mind if MC resolves a conditional branch destination statically. To do that, the fixups were split and the fixup handling logic taught to let the backend force a relocation even if MC thinks it shouldn't need one.</div><div><br></div><div>-Jim<br><div><div><br></div><div>On Mar 12, 2012, at 5:32 PM, Jan Voung <<a href="mailto:jvoung@google.com">jvoung@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Hi Jim,<div><br></div><div>How does "fixup_arm_bl" differ from the "<span style="">fixup_arm_condbranch" that was introduced in </span><a href="http://llvm.org/viewvc/llvm-project?view=rev&revision=124895">http://llvm.org/viewvc/llvm-project?view=rev&revision=124895</a>? For the change to <span style="">ARMELFObjectWriter.cpp, we still need conditional bl instructions to have R_ARM_JUMP24 relocs (which </span><font face="arial, sans-serif">fixup_arm_condbranch helped do), instead of R_ARM_CALL.</font></div>
<div><span style=""><br></span></div><div><span style="">- Jan</span></div><div><br><div class="gmail_quote">On Mon, Feb 27, 2012 at 1:36 PM, Jim Grosbach <span dir="ltr"><<a href="mailto:grosbach@apple.com">grosbach@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: grosbach<br>
Date: Mon Feb 27 15:36:23 2012<br>
New Revision: 151571<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=151571&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=151571&view=rev</a><br>
Log:<br>
ARM BL/BLX instruction fixups should use relocations.<br>
<br>
We on the linker to resolve calls to the appropriate BL/BLX instruction<br>
to make interworking function correctly. It uses the symbol in the<br>
relocation to do that, so we need to be careful about being too clever.<br>
<br>
To enable this for ARM mode, split the BL/BLX fixup kind off from the<br>
unconditional-branch fixups.<br>
<br>
<a href="rdar://10927209">rdar://10927209</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/MC/MCAsmBackend.h<br>
llvm/trunk/lib/MC/MCAssembler.cpp<br>
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp<br>
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp<br>
llvm/trunk/test/MC/ARM/arm_fixups.s<br>
llvm/trunk/test/MC/ARM/basic-arm-instructions.s<br>
<br>
Modified: llvm/trunk/include/llvm/MC/MCAsmBackend.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/MC/MCAsmBackend.h (original)<br>
+++ llvm/trunk/include/llvm/MC/MCAsmBackend.h Mon Feb 27 15:36:23 2012<br>
@@ -92,11 +92,13 @@<br>
virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;<br>
<br>
/// processFixupValue - Target hook to adjust the literal value of a fixup<br>
- /// if necessary. The default does nothing.<br>
+ /// if necessary. IsResolved signals whether the caller believes a relocation<br>
+ /// is needed; the target can modify the value. The default does nothing.<br>
virtual void processFixupValue(const MCAssembler &Asm,<br>
const MCAsmLayout &Layout,<br>
const MCFixup &Fixup, const MCFragment *DF,<br>
- MCValue &Target, uint64_t &Value) {}<br>
+ MCValue &Target, uint64_t &Value,<br>
+ bool &IsResolved) {}<br>
<br>
/// @}<br>
<br>
<br>
Modified: llvm/trunk/lib/MC/MCAssembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)<br>
+++ llvm/trunk/lib/MC/MCAssembler.cpp Mon Feb 27 15:36:23 2012<br>
@@ -299,8 +299,10 @@<br>
Value -= Offset;<br>
}<br>
<br>
- // Let the backend adjust the fixup value if necessary.<br>
- Backend.processFixupValue(*this, Layout, Fixup, DF, Target, Value);<br>
+ // Let the backend adjust the fixup value if necessary, including whether<br>
+ // we need a relocation.<br>
+ Backend.processFixupValue(*this, Layout, Fixup, DF, Target, Value,<br>
+ IsResolved);<br>
<br>
return IsResolved;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Feb 27 15:36:23 2012<br>
@@ -189,6 +189,8 @@<br>
unsigned Op) const { return 0; }<br>
unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
+ unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)<br>
+ const { return 0; }<br>
unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)<br>
const { return 0; }<br>
unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Feb 27 15:36:23 2012<br>
@@ -349,13 +349,11 @@<br>
// Call target for ARM. Handles conditional/unconditional<br>
// FIXME: rename bl_target to t2_bltarget?<br>
def bl_target : Operand<i32> {<br>
- // Encoded the same as branch targets.<br>
- let EncoderMethod = "getARMBranchTargetOpValue";<br>
+ let EncoderMethod = "getARMBLTargetOpValue";<br>
let OperandType = "OPERAND_PCREL";<br>
}<br>
<br>
def blx_target : Operand<i32> {<br>
- // Encoded the same as branch targets.<br>
let EncoderMethod = "getARMBLXTargetOpValue";<br>
let OperandType = "OPERAND_PCREL";<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Mon Feb 27 15:36:23 2012<br>
@@ -78,6 +78,8 @@<br>
{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },<br>
{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },<br>
{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },<br>
+{ "fixup_arm_bl", 0, 24, MCFixupKindInfo::FKF_IsPCRel },<br>
+{ "fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel },<br>
{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },<br>
{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel },<br>
{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel },<br>
@@ -106,18 +108,28 @@<br>
/// if necessary.<br>
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,<br>
const MCFixup &Fixup, const MCFragment *DF,<br>
- MCValue &Target, uint64_t &Value) {<br>
+ MCValue &Target, uint64_t &Value,<br>
+ bool &IsResolved) {<br>
+ const MCSymbolRefExpr *A = Target.getSymA();<br>
// Some fixups to thumb function symbols need the low bit (thumb bit)<br>
// twiddled.<br>
if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 &&<br>
(unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 &&<br>
(unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) {<br>
- if (const MCSymbolRefExpr *A = Target.getSymA()) {<br>
+ if (A) {<br>
const MCSymbol &Sym = A->getSymbol().AliasedSymbol();<br>
if (Asm.isThumbFunc(&Sym))<br>
Value |= 1;<br>
}<br>
}<br>
+ // We must always generate a relocation for BL/BLX instructions if we have<br>
+ // a symbol to reference, as the linker relies on knowing the destination<br>
+ // symbol's thumb-ness to get interworking right.<br>
+ if (A && ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_blx ||<br>
+ (unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl ||<br>
+ (unsigned)Fixup.getKind() == ARM::fixup_arm_blx ||<br>
+ (unsigned)Fixup.getKind() == ARM::fixup_arm_bl))<br>
+ IsResolved = false;<br>
}<br>
<br>
bool mayNeedRelaxation(const MCInst &Inst) const;<br>
@@ -343,6 +355,8 @@<br>
<br>
case ARM::fixup_arm_condbranch:<br>
case ARM::fixup_arm_uncondbranch:<br>
+ case ARM::fixup_arm_bl:<br>
+ case ARM::fixup_arm_blx:<br>
// These values don't encode the low two bits since they're always zero.<br>
// Offset by 8 just as above.<br>
return 0xffffff & ((Value - 8) >> 2);<br>
@@ -552,6 +566,8 @@<br>
case ARM::fixup_arm_ldst_pcrel_12:<br>
case ARM::fixup_arm_pcrel_10:<br>
case ARM::fixup_arm_adr_pcrel_12:<br>
+ case ARM::fixup_arm_bl:<br>
+ case ARM::fixup_arm_blx:<br>
case ARM::fixup_arm_condbranch:<br>
case ARM::fixup_arm_uncondbranch:<br>
return 3;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp Mon Feb 27 15:36:23 2012<br>
@@ -177,6 +177,8 @@<br>
break;<br>
}<br>
break;<br>
+ case ARM::fixup_arm_bl:<br>
+ case ARM::fixup_arm_blx:<br>
case ARM::fixup_arm_uncondbranch:<br>
switch (Modifier) {<br>
case MCSymbolRefExpr::VK_ARM_PLT:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h Mon Feb 27 15:36:23 2012<br>
@@ -59,6 +59,12 @@<br>
// fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.<br>
fixup_arm_thumb_br,<br>
<br>
+ // fixup_arm_bl - Fixup for ARM BL instructions.<br>
+ fixup_arm_bl,<br>
+<br>
+ // fixup_arm_blx - Fixup for ARM BLX instructions.<br>
+ fixup_arm_blx,<br>
+<br>
// fixup_arm_thumb_bl - Fixup for Thumb BL instructions.<br>
fixup_arm_thumb_bl,<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Mon Feb 27 15:36:23 2012<br>
@@ -118,8 +118,10 @@<br>
/// branch target.<br>
uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,<br>
SmallVectorImpl<MCFixup> &Fixups) const;<br>
+ uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,<br>
+ SmallVectorImpl<MCFixup> &Fixups) const;<br>
uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,<br>
- SmallVectorImpl<MCFixup> &Fixups) const;<br>
+ SmallVectorImpl<MCFixup> &Fixups) const;<br>
<br>
/// getAdrLabelOpValue - Return encoding info for 12-bit immediate<br>
/// ADR label target.<br>
@@ -592,16 +594,21 @@<br>
}<br>
<br>
uint32_t ARMMCCodeEmitter::<br>
+getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,<br>
+ SmallVectorImpl<MCFixup> &Fixups) const {<br>
+ const MCOperand MO = MI.getOperand(OpIdx);<br>
+ if (MO.isExpr())<br>
+ return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_bl, Fixups);<br>
+<br>
+ return MO.getImm() >> 2;<br>
+}<br>
+<br>
+uint32_t ARMMCCodeEmitter::<br>
getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,<br>
SmallVectorImpl<MCFixup> &Fixups) const {<br>
const MCOperand MO = MI.getOperand(OpIdx);<br>
- if (MO.isExpr()) {<br>
- if (HasConditionalBranch(MI))<br>
- return ::getBranchTargetOpValue(MI, OpIdx,<br>
- ARM::fixup_arm_condbranch, Fixups);<br>
- return ::getBranchTargetOpValue(MI, OpIdx,<br>
- ARM::fixup_arm_uncondbranch, Fixups);<br>
- }<br>
+ if (MO.isExpr())<br>
+ return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups);<br>
<br>
return MO.getImm() >> 1;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Mon Feb 27 15:36:23 2012<br>
@@ -82,6 +82,8 @@<br>
case ARM::fixup_arm_adr_pcrel_12:<br>
case ARM::fixup_arm_condbranch:<br>
case ARM::fixup_arm_uncondbranch:<br>
+ case ARM::fixup_arm_bl:<br>
+ case ARM::fixup_arm_blx:<br>
RelocType = unsigned(macho::RIT_ARM_Branch24Bit);<br>
// Report as 'long', even though that is not quite accurate.<br>
Log2Size = llvm::Log2_32(4);<br>
<br>
Modified: llvm/trunk/test/MC/ARM/arm_fixups.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_fixups.s?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_fixups.s?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/arm_fixups.s (original)<br>
+++ llvm/trunk/test/MC/ARM/arm_fixups.s Mon Feb 27 15:36:23 2012<br>
@@ -3,7 +3,7 @@<br>
<br>
bl _printf<br>
@ CHECK: bl _printf @ encoding: [A,A,A,0xeb]<br>
-@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch<br>
+@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_bl<br>
<br>
mov r9, :lower16:(_foo)<br>
movw r9, :lower16:(_foo)<br>
<br>
Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=151571&r1=151570&r2=151571&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=151571&r1=151570&r2=151571&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)<br>
+++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Mon Feb 27 15:36:23 2012<br>
@@ -388,9 +388,9 @@<br>
blx #16212288<br>
<br>
@ CHECK: bl _bar @ encoding: [A,A,A,0xeb]<br>
-@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch<br>
+@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_bl<br>
@ CHECK: blx _bar @ encoding: [A,A,A,0xfa]<br>
- @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch<br>
+ @ fixup A - offset: 0, value: _bar, kind: fixup_arm_blx<br>
@ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b]<br>
@ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa]<br>
@ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa]<br>
<br>
<br>
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</blockquote></div><br></div>
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