<html><head><base href="x-msg://2612/"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Hi James,<div>I did take a look at this patch and it LGTM, but admittedly this may be a case of the blind leading the blind as my experience with the DAGCombiner is only _slightly_ greater then yours.</div><div><br></div><div><div>+ // a destination type that is wider than the source, and neither does</div><div>+ // it have a FP_TO_[SU]INT instruction with a narrower dest than source.</div></div><div><br></div><div>, and neither -> nor</div><div>dest -> destination</div><div><br></div><div> Chad</div><div><br><div><div>On Feb 14, 2012, at 9:02 AM, James Molloy wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div lang="EN-GB" link="blue" vlink="purple"><div class="Section1" style="page: Section1; "><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "> Hi,<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">The following patch set improves the generated code on ARM for extending loads (addressing PR11836).<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">The first patch (affecting TargetSelectionDAG.td and ARMInstrNEON.td) teaches ISel how to perform extending loads (extload, zextload and sextload) for various vector types. It also teaches ISel that the same instructions can be used to perform extending loads of vectors that use only half the available lanes (v4i8 -> v4i16 for example), and how to use the widening instructions twice to go from e.g. v4i8 -> v4i32.<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">I also changed ARMIselLowering.cpp to inform the SelectionDAG that extending loads from v4i8 are in fact legal, not "Expand", and I allow FP_TO_UINT for v4i16 types from v4i32. The opposite (v4i32 = UINT_TO_FP v4i16) is already in ARMIselLowering.cpp. I also teach the DAGCombiner to use a custom combining op for v4i16 types on FP_TO_[US]INT.<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">The second patch adds an optimisation to the DAGCombiner. It looks for AND nodes with an EXTLOAD as one operand (or transitively, an EXTRACT_VECTOR_ELT then an EXTLOAD) and a constant (or vector splat) as the other. If the constant is the AllOnesValue for a correct bitwidth (such as 0xFF or 0xFFFF), the EXTLOAD will be converted to a ZEXTLOAD and the AND can be removed.<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">This fixes a poor code pattern in extending vector loads where a pointless AND would be inserted.<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">Please review – this is my first serious DAGCombiner change!<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">Cheers,<o:p></o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; "><o:p> </o:p></div><div style="margin-top: 0cm; margin-right: 0cm; margin-left: 0cm; margin-bottom: 0.0001pt; font-size: 11pt; font-family: Calibri, sans-serif; ">James<o:p></o:p></div></div><span><1.widening-and-narrowing.patch></span><span><2.anyexttozeroext.patch></span>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu" style="color: blue; text-decoration: underline; ">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" style="color: blue; text-decoration: underline; ">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></div></blockquote></div><br></div></body></html>