That's what I plan to work on next.<br><br><div class="gmail_quote">On Fri, Feb 17, 2012 at 12:58 AM, Chris Lattner <span dir="ltr"><<a href="mailto:clattner@apple.com">clattner@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="im"><br>
On Feb 16, 2012, at 11:02 PM, Craig Topper wrote:<br>
<br>
> Author: ctopper<br>
> Date: Fri Feb 17 01:02:34 2012<br>
> New Revision: 150795<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=150795&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=150795&view=rev</a><br>
> Log:<br>
> Remove the last of the old vector_shuffle patterns from X86 isel.<br>
<br>
</div>Very nice! A lot of predicates like isMOVHLPSMask can now become static functions.<br>
<span class="HOEnZb"><font color="#888888"><br>
-Chris<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
> llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=150795&r1=150794&r2=150795&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=150795&r1=150794&r2=150795&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Fri Feb 17 01:02:34 2012<br>
> @@ -342,12 +342,6 @@<br>
> return getI32Imm(N->getZExtValue() >> 3);<br>
> }]>;<br>
><br>
> -// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,<br>
> -// SHUFP* etc. imm.<br>
> -def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{<br>
> - return getI8Imm(X86::getShuffleSHUFImmediate(cast<ShuffleVectorSDNode>(N)));<br>
> -}]>;<br>
> -<br>
> // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index<br>
> // to VEXTRACTF128 imm.<br>
> def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{<br>
> @@ -360,26 +354,6 @@<br>
> return getI8Imm(X86::getInsertVINSERTF128Immediate(N));<br>
> }]>;<br>
><br>
> -def movhlps : PatFrag<(ops node:$lhs, node:$rhs),<br>
> - (vector_shuffle node:$lhs, node:$rhs), [{<br>
> - return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));<br>
> -}]>;<br>
> -<br>
> -def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),<br>
> - (vector_shuffle node:$lhs, node:$rhs), [{<br>
> - return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));<br>
> -}]>;<br>
> -<br>
> -def movlhps : PatFrag<(ops node:$lhs, node:$rhs),<br>
> - (vector_shuffle node:$lhs, node:$rhs), [{<br>
> - return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));<br>
> -}]>;<br>
> -<br>
> -def movlp : PatFrag<(ops node:$lhs, node:$rhs),<br>
> - (vector_shuffle node:$lhs, node:$rhs), [{<br>
> - return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));<br>
> -}]>;<br>
> -<br>
> def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),<br>
> (extract_subvector node:$bigvec,<br>
> node:$index), [{<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=150795&r1=150794&r2=150795&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=150795&r1=150794&r2=150795&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Feb 17 01:02:34 2012<br>
> @@ -945,30 +945,30 @@<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,<br>
> - PatFrag mov_frag, string base_opc,<br>
> + SDNode psnode, SDNode pdnode, string base_opc,<br>
> string asm_opr> {<br>
> def PSrm : PI<opc, MRMSrcMem,<br>
> (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),<br>
> !strconcat(base_opc, "s", asm_opr),<br>
> [(set RC:$dst,<br>
> - (mov_frag RC:$src1,<br>
> + (psnode RC:$src1,<br>
> (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],<br>
> IIC_DEFAULT, SSEPackedSingle>, TB;<br>
><br>
> def PDrm : PI<opc, MRMSrcMem,<br>
> (outs RC:$dst), (ins RC:$src1, f64mem:$src2),<br>
> !strconcat(base_opc, "d", asm_opr),<br>
> - [(set RC:$dst, (v2f64 (mov_frag RC:$src1,<br>
> + [(set RC:$dst, (v2f64 (pdnode RC:$src1,<br>
> (scalar_to_vector (loadf64 addr:$src2)))))],<br>
> IIC_DEFAULT, SSEPackedDouble>, TB, OpSize;<br>
> }<br>
><br>
> let AddedComplexity = 20 in {<br>
> - defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",<br>
> + defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",<br>
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;<br>
> }<br>
> let Constraints = "$src1 = $dst", AddedComplexity = 20 in {<br>
> - defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",<br>
> + defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",<br>
> "\t{$src2, $dst|$dst, $src2}">;<br>
> }<br>
><br>
> @@ -990,49 +990,17 @@<br>
> (iPTR 0))), addr:$dst)]>;<br>
><br>
> let Predicates = [HasAVX] in {<br>
> - let AddedComplexity = 20 in {<br>
> - // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS<br>
> - def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (VMOVLPSrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (VMOVLPSrm VR128:$src1, addr:$src2)>;<br>
> - // vector_shuffle v1, (load v2) <2, 1> using MOVLPS<br>
> - def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
> - }<br>
> -<br>
> - // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS<br>
> - def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),<br>
> - (VMOVLPSmr addr:$src1, VR128:$src2)>;<br>
> - def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),<br>
> - VR128:$src2)), addr:$src1),<br>
> - (VMOVLPSmr addr:$src1, VR128:$src2)>;<br>
> -<br>
> - // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS<br>
> - def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),<br>
> - (VMOVLPDmr addr:$src1, VR128:$src2)>;<br>
> - def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),<br>
> - (VMOVLPDmr addr:$src1, VR128:$src2)>;<br>
> -<br>
> // Shuffle with VMOVLPS<br>
> def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),<br>
> (VMOVLPSrm VR128:$src1, addr:$src2)>;<br>
> def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),<br>
> (VMOVLPSrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(X86Movlps VR128:$src1,<br>
> - (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),<br>
> - (VMOVLPSrm VR128:$src1, addr:$src2)>;<br>
><br>
> // Shuffle with VMOVLPD<br>
> def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),<br>
> (VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
> def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),<br>
> (VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(v2f64 (X86Movlpd VR128:$src1,<br>
> - (scalar_to_vector (loadf64 addr:$src2)))),<br>
> - (VMOVLPDrm VR128:$src1, addr:$src2)>;<br>
><br>
> // Store patterns<br>
> def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),<br>
> @@ -1050,23 +1018,10 @@<br>
> }<br>
><br>
> let Predicates = [HasSSE1] in {<br>
> - let AddedComplexity = 20 in {<br>
> - // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS<br>
> - def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
> - }<br>
> -<br>
> // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS<br>
> def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),<br>
> (iPTR 0))), addr:$src1),<br>
> (MOVLPSmr addr:$src1, VR128:$src2)>;<br>
> - def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),<br>
> - (MOVLPSmr addr:$src1, VR128:$src2)>;<br>
> - def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),<br>
> - VR128:$src2)), addr:$src1),<br>
> - (MOVLPSmr addr:$src1, VR128:$src2)>;<br>
><br>
> // Shuffle with MOVLPS<br>
> def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),<br>
> @@ -1074,9 +1029,6 @@<br>
> def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),<br>
> (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
> def : Pat<(X86Movlps VR128:$src1,<br>
> - (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),<br>
> - (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(X86Movlps VR128:$src1,<br>
> (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),<br>
> (MOVLPSrm VR128:$src1, addr:$src2)>;<br>
><br>
> @@ -1091,28 +1043,11 @@<br>
> }<br>
><br>
> let Predicates = [HasSSE2] in {<br>
> - let AddedComplexity = 20 in {<br>
> - // vector_shuffle v1, (load v2) <2, 1> using MOVLPS<br>
> - def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (MOVLPDrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),<br>
> - (MOVLPDrm VR128:$src1, addr:$src2)>;<br>
> - }<br>
> -<br>
> - // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS<br>
> - def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),<br>
> - (MOVLPDmr addr:$src1, VR128:$src2)>;<br>
> - def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),<br>
> - (MOVLPDmr addr:$src1, VR128:$src2)>;<br>
> -<br>
> // Shuffle with MOVLPD<br>
> def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),<br>
> (MOVLPDrm VR128:$src1, addr:$src2)>;<br>
> def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),<br>
> (MOVLPDrm VR128:$src1, addr:$src2)>;<br>
> - def : Pat<(v2f64 (X86Movlpd VR128:$src1,<br>
> - (scalar_to_vector (loadf64 addr:$src2)))),<br>
> - (MOVLPDrm VR128:$src1, addr:$src2)>;<br>
><br>
> // Store patterns<br>
> def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),<br>
> @@ -1128,11 +1063,11 @@<br>
> //===----------------------------------------------------------------------===//<br>
><br>
> let AddedComplexity = 20 in {<br>
> - defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",<br>
> + defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",<br>
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;<br>
> }<br>
> let Constraints = "$src1 = $dst", AddedComplexity = 20 in {<br>
> - defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",<br>
> + defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",<br>
> "\t{$src2, $dst|$dst, $src2}">;<br>
> }<br>
><br>
> @@ -1163,11 +1098,6 @@<br>
><br>
> let Predicates = [HasAVX] in {<br>
> // VMOVHPS patterns<br>
> - def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),<br>
> - (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;<br>
> - def : Pat<(X86Movlhps VR128:$src1,<br>
> - (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),<br>
> - (VMOVHPSrm VR128:$src1, addr:$src2)>;<br>
> def : Pat<(X86Movlhps VR128:$src1,<br>
> (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),<br>
> (VMOVHPSrm VR128:$src1, addr:$src2)>;<br>
> @@ -1182,20 +1112,10 @@<br>
> def : Pat<(v2f64 (X86Unpckl VR128:$src1,<br>
> (scalar_to_vector (loadf64 addr:$src2)))),<br>
> (VMOVHPDrm VR128:$src1, addr:$src2)>;<br>
> -<br>
> - // FIXME: This should be matched by a X86Movhpd instead. Same as above<br>
> - def : Pat<(v2f64 (X86Movlhpd VR128:$src1,<br>
> - (scalar_to_vector (loadf64 addr:$src2)))),<br>
> - (VMOVHPDrm VR128:$src1, addr:$src2)>;<br>
> }<br>
><br>
> let Predicates = [HasSSE1] in {<br>
> // MOVHPS patterns<br>
> - def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),<br>
> - (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;<br>
> - def : Pat<(X86Movlhps VR128:$src1,<br>
> - (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),<br>
> - (MOVHPSrm VR128:$src1, addr:$src2)>;<br>
> def : Pat<(X86Movlhps VR128:$src1,<br>
> (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),<br>
> (MOVHPSrm VR128:$src1, addr:$src2)>;<br>
> @@ -1212,11 +1132,6 @@<br>
> def : Pat<(v2f64 (X86Unpckl VR128:$src1,<br>
> (scalar_to_vector (loadf64 addr:$src2)))),<br>
> (MOVHPDrm VR128:$src1, addr:$src2)>;<br>
> -<br>
> - // FIXME: This should be matched by a X86Movhpd instead. Same as above<br>
> - def : Pat<(v2f64 (X86Movlhpd VR128:$src1,<br>
> - (scalar_to_vector (loadf64 addr:$src2)))),<br>
> - (MOVHPDrm VR128:$src1, addr:$src2)>;<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
><br>
><br>
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<br>
</div></div></blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>