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<p class=MsoNormal> Hi,<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>The following patch set improves the generated code on ARM
for extending loads (addressing PR11836).<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>The first patch (affecting TargetSelectionDAG.td and
ARMInstrNEON.td) teaches ISel how to perform extending loads (extload, zextload
and sextload) for various vector types. It also teaches ISel that the same
instructions can be used to perform extending loads of vectors that use only
half the available lanes (v4i8 -> v4i16 for example), and how to use the
widening instructions twice to go from e.g. v4i8 -> v4i32.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>I also changed ARMIselLowering.cpp to inform the
SelectionDAG that extending loads from v4i8 are in fact legal, not
"Expand", and I allow FP_TO_UINT for v4i16 types from v4i32. The
opposite (v4i32 = UINT_TO_FP v4i16) is already in ARMIselLowering.cpp. I also
teach the DAGCombiner to use a custom combining op for v4i16 types on
FP_TO_[US]INT.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>The second patch adds an optimisation to the DAGCombiner. It
looks for AND nodes with an EXTLOAD as one operand (or transitively, an
EXTRACT_VECTOR_ELT then an EXTLOAD) and a constant (or vector splat) as the
other. If the constant is the AllOnesValue for a correct bitwidth (such as 0xFF
or 0xFFFF), the EXTLOAD will be converted to a ZEXTLOAD and the AND can be
removed.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>This fixes a poor code pattern in extending vector loads
where a pointless AND would be inserted.<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Please review – this is my first serious
DAGCombiner change!<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>Cheers,<o:p></o:p></p>
<p class=MsoNormal><o:p> </o:p></p>
<p class=MsoNormal>James<o:p></o:p></p>
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