<div class="gmail_quote">On Thu, Feb 2, 2012 at 1:10 AM, Elena Demikhovsky <span dir="ltr"><<a href="mailto:elena.demikhovsky@intel.com">elena.demikhovsky@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: delena<br>
Date: Thu Feb 2 03:10:43 2012<br>
New Revision: 149600<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=149600&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=149600&view=rev</a><br>
Log:<br>
Optimization for SIGN_EXTEND operation on AVX.<br>
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32<br>
extensions.<br></blockquote><div><br></div><div>Why was this submitted without review? Your original patch was only mailed to the list 19 hours ago.</div><div><br></div><div>This patch doesn't adhere to LLVM coding conventions very closely at all. Please try to make your code look more like the surrounding code. I've commented a few obvious places below.</div>
<div><br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">+static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,<br>
+ TargetLowering::DAGCombinerInfo &DCI,<br>
+ const X86Subtarget *Subtarget) {<br>
+ if (!DCI.isBeforeLegalizeOps())<br>
+ return SDValue();<br>
+<br>
+ if (!Subtarget->hasAVX()) return SDValue();<br>
+<br>
+ // Optimize vectors in AVX mode<br>
+ // Sign extend v8i16 to v8i32 and<br>
+ // v4i32 to v4i64<br>
+ //<br>
+ // Divide input vector into two parts<br>
+ // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}<br>
+ // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32<br>
+ // concat the vectors to original VT<br></blockquote><div><br></div><div>Why is this comment block indented more than the rest of the code?</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+ EVT VT = N->getValueType(0);<br>
+ SDValue Op = N->getOperand(0);<br>
+ EVT OpVT = Op.getValueType();<br>
+ DebugLoc dl = N->getDebugLoc();<br>
+<br>
+ if (((VT == MVT::v4i64) && (OpVT == MVT::v4i32)) ||<br>
+ ((VT == MVT::v8i32) && (OpVT == MVT::v8i16))) {<br></blockquote><div><br></div><div>Please don't wrap comparison operators ('==', '>', '<', etc...) in extraneous parentheses. This defeats many warnings Clang and GCC both implement which use redundant parentheses to force explicit syntax for these two constructs:</div>
<div><br></div><div>if ((x = y)) { ... } // Here we assign, and use extra parens to indicate it was intended.</div><div>if (x == y) { ... } // Here we compare, and w/o the parens will get a warning if we typo '==' as '='.</div>
<div><br></div><div>Also, please line up with the open '('s at each level when breaking a line.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+ unsigned NumElems = OpVT.getVectorNumElements();<br>
+ SmallVector<int,8> ShufMask1(NumElems, -1);<br>
+ for (unsigned i=0; i< NumElems/2; i++) ShufMask1[i] = i;<br></blockquote><div><br></div><div>Please use the spacing and whitespace conventional in LLVM for your loops. spaces on both sides of '=' and '<' are ubiquitous.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+ SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),<br>
+ ShufMask1.data());<br></blockquote><div><br></div><div>Please line up with the '('.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+ SmallVector<int,8> ShufMask2(NumElems, -1);<br>
+ for (unsigned i=0; i< NumElems/2; i++) ShufMask2[i] = i+NumElems/2;<br>
+<br>
+ SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),<br>
+ ShufMask2.data());<br></blockquote><div><br></div><div>Please line up with the '('.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+ EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),<br>
+ VT.getVectorNumElements()/2);<br></blockquote><div><br></div><div>Please line up with the '('.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+<br>
+ OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);<br>
+ OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);<br>
+<br>
+ return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);<br>
+ }<br>
+ return SDValue();<br>
+}<br>
+<br>
static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,<br>
const X86Subtarget *Subtarget) {<br>
// (i32 zext (and (i8 x86isd::setcc_carry), 1)) -><br>
@@ -14886,6 +14936,7 @@<br>
case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);<br>
case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);<br>
case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);<br>
+ case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);<br>
case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);<br>
case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);<br>
case X86ISD::SHUFP: // Handle all target specific shuffles<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=149600&r1=149599&r2=149600&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=149600&r1=149599&r2=149600&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Feb 2 03:10:43 2012<br>
@@ -219,6 +219,9 @@<br>
// VZEXT_MOVL - Vector move low and zero extend.<br>
VZEXT_MOVL,<br>
<br>
+ // VZEXT_MOVL - Vector move low and sign extend.<br></blockquote><div><br></div><div>This comment is wrong.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+ VSEXT_MOVL,<br>
+<br>
// VSHL, VSRL - 128-bit vector logical left / right shift<br>
VSHLDQ, VSRLDQ,<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=149600&r1=149599&r2=149600&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=149600&r1=149599&r2=149600&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Feb 2 03:10:43 2012<br>
@@ -71,6 +71,9 @@<br>
SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;<br>
def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",<br>
SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;<br>
+def X86vsmovl : SDNode<"X86ISD::VSEXT_MOVL",<br>
+ SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisInt<1>, SDTCisInt<0>]>>;<br>
+<br>
def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,<br>
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;<br>
def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=149600&r1=149599&r2=149600&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=149600&r1=149599&r2=149600&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Feb 2 03:10:43 2012<br>
@@ -5478,6 +5478,16 @@<br>
(PMOVZXDQrm addr:$src)>;<br>
}<br>
<br>
+let Predicates = [HasAVX] in {<br>
+def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;<br>
+def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;<br>
+}<br>
+<br>
+let Predicates = [HasSSE41] in {<br>
+def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;<br>
+def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;<br>
+}<br>
+<br>
<br>
multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {<br>
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/avx-sext.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-sext.ll?rev=149600&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-sext.ll?rev=149600&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-sext.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-sext.ll Thu Feb 2 03:10:43 2012<br>
@@ -0,0 +1,17 @@<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s<br>
+<br>
+define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {<br>
+;CHECK: sext_8i16_to_8i32<br>
+;CHECK: vpmovsxwd<br>
+<br>
+ %B = sext <8 x i16> %A to <8 x i32><br>
+ ret <8 x i32>%B<br>
+}<br>
+<br>
+define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {<br>
+;CHECK: sext_4i32_to_4i64<br>
+;CHECK: vpmovsxdq<br>
+<br>
+ %B = sext <4 x i32> %A to <4 x i64><br>
+ ret <4 x i64>%B<br>
+}<br>
<br>
Propchange: llvm/trunk/test/CodeGen/X86/avx-sext.ll<br>
------------------------------------------------------------------------------<br>
svn:executable = *<br>
<br>
<br>
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</blockquote></div><br>