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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Hello Andy,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thank you for your comments. I have revised the patch as you suggested.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">I have also added “-mcpu=generic” to two additional tests (2010-02-19-TailCallRetAddrBug.ll and peep-test-3.ll) which were failing when run on Atom, after I
applied a Evan’s suggestion to change the scheduling preference to “Hybrid”.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Unless you have any other comments, please commit the attached patch.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Preston<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Andrew Trick [mailto:atrick@apple.com]
<br>
<b>Sent:</b> Tuesday, January 31, 2012 2:22 AM<br>
<b>To:</b> Gurd, Preston<br>
<b>Cc:</b> Evan Cheng; llvm-commits@cs.uiuc.edu<br>
<b>Subject:</b> Re: [llvm-commits] [llvm][PATCH - REVISED][Review request] X86 Instruction scheduler for the Intel Atom<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Jan 23, 2012, at 3:05 PM, "Gurd, Preston" <<a href="mailto:preston.gurd@intel.com">preston.gurd@intel.com</a>> wrote:<o:p></o:p></p>
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<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Revision 2: Tests which were failing, when run on an Atom, due to the tests finding a schedule different from what was expected, have been changed to use “-mcpu=generic”
in order to prevent the Atom scheduler from running, so that all “make check” tests pass.</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:black">From:</span></b><span class="apple-converted-space"><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:black"> </span></span><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:black">Gurd,
Preston<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>Tuesday, January 17, 2012 4:29 PM<br>
<b>To:</b><span class="apple-converted-space"> </span>Evan Cheng<br>
<b>Cc:</b><span class="apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu"><span style="color:purple">llvm-commits@cs.uiuc.edu</span></a><br>
<b>Subject:</b><span class="apple-converted-space"> </span>[llvm-commits] [llvm][PATCH - REVISED][Review request] X86 Instruction scheduler for the Intel Atom</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">The attached patch implements most of an instruction scheduler for the Intel Atom.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">It adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">It sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions
will be set in subsequent patches.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">It adds a test to verify that the scheduler is working.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">I realize that this patch is kind of large, but please consider that the vast majority of the changes consist only of adding an instruction itinerary class name to an instruction.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">Revision: the patch also changes the scheduling preference to “Hybrid” for i386 Atom, while leaving x86_64 as ILP.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">Please commit the patch if it seems acceptable.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">Preston<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:black">From:</span></b><span class="apple-converted-space"><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:black"> </span></span><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif";color:black">Evan
Cheng [mailto:evan.cheng@apple.com]<span class="apple-converted-space"> </span><br>
<b>Sent:</b><span class="apple-converted-space"> </span>Monday, January 16, 2012 12:01 PM<br>
<b>To:</b><span class="apple-converted-space"> </span>Gurd, Preston<br>
<b>Cc:</b><span class="apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu"><span style="color:purple">llvm-commits@cs.uiuc.edu</span></a><br>
<b>Subject:</b><span class="apple-converted-space"> </span>Re: [llvm-commits] [llvm][PATCH][Review request] X86 Instruction scheduler for the Intel Atom</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">Very nice. One question, I noticed you haven't changed the scheduling preference so x86_64 is still using ILP scheduler while i386 is using register pressure reduction scheduler. Have you tried changing the preference
to latency scheduler for Atom?<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">Evan<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="color:black">On Jan 13, 2012, at 3:26 PM, Gurd, Preston wrote:<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="color:black"> <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">The attached patch implements most of an instruction scheduler for the Intel Atom.</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">It adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">It sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td.
The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">It adds a test to verify that the scheduler is working.</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black"> </span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:black">I realize that this patch is kind of large, but please consider that the vast majority of the changes consist only of adding an instruction itinerary class name
to an instruction.</span><span style="color:black"><o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Hi Preston,<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">I just have a couple minor questions I'd like you to address before I commit this:<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">+def : AtomProc<"atom", [ProcIntelAtom, FeatureSSE3, FeatureCMPXCHG16B,<o:p></o:p></p>
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<p class="MsoNormal">+ FeatureMOVBE, FeatureSlowBTMem]>;<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">These features are already included in the ProcIntelAtom family. Why do you need to list them again? Please verify, but subtarget features should be transitively implied.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">+ //CriticalPathRCs.push_back(&X86::GPRRegClass);<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">If you want to leave this disabled, please add comments.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks,<o:p></o:p></p>
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<p class="MsoNormal">-Andy<o:p></o:p></p>
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