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Hi Tom,<br>
<pre wrap="">> How are you going to model bundle
> constraints? I'm not familiar with the Hexagon architecture, but our
> hardware has several bundle constraints. For example, some instructions
> can only be in a certain slot within the bundle, while other instructions
> fill all slots in the bundle.
Yes, we had to solve the same problem for Hexagon. We authored a target-independent packetizer (or bundler) that examines available slots and automatically constructs a DFA to represent slot restrictions in a VLIW architecture. This DFA can be queried by a target while bundling instructions. You may be interested in this posting on llvm-commit: <a class="moz-txt-link-freetext" href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20111128/132357.html">http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20111128/132357.html</a> The corresponding commit is: <a class="moz-txt-link-freetext" href="http://llvm.org/viewvc/llvm-project?view=rev&revision=145629">http://llvm.org/viewvc/llvm-project?view=rev&revision=145629</a>
Feel free to ping me if you have any questions on the DFA packetizer.
-Anshu
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On 1/31/2012 10:08 AM, Tom Stellard wrote:
<blockquote
cite="mid:20120131160838.GD2075@L7-CNU1252LKR-172027226155.amd.com"
type="cite">
<pre wrap="">On Tue, Jan 31, 2012 at 09:18:05AM -0600, Sergei Larin wrote:
</pre>
<blockquote type="cite">
<pre wrap="">
Hello everybody,
Attached is initial patch for a VLIW specific scheduler framework that
utilizes deterministic finite automaton (DFA) .
Several key points:
- The scheduler is largely based on the existing framework, but
introduces several VLIW specific concepts. It could be classified as a top
down list scheduler, critical path first, with DFA used for parallel
resources modeling. It also models and tracks register pressure in the way
similar to the current RegPressure scheduler. It employs a slightly
different way to compute "cost" function for all SUs in AQ which allows for
somewhat easier balancing of multiple heuristic inputs. Current version does
_not_ generates bundles/packets (but models them internally). It could be
easily modified to do so, and it is our plan to make it a part of bundle
generation in the near future.
- The scheduler is enabled for the Hexagon backend. Comparing to
any existing scheduler, for this VLIW target this code produces between 1.9%
slowdown and 11% speedup on our internal test suite. This test set comprised
from a variety of real world applications ranging from DSP specific
applications to SPEC. Some DSP kernels (when taken out of context) enjoy up
to 20% speedup when compared to the "default" scheduling mechanism
(RegPressure pre-RA + post RA). Main reason for this kind of corner case
behavior is long chains of independent memory accesses that are
conservatively serialized by the default scheduler (and there is no HW
scheduler to sort it out at the run time).
- This patch is an initial submission with a bare minimum of
features, and more heuristics will be added to it later. We prefer to submit
it in stages to simplify review process and improve SW management.
- Patch also contains minor updates to two Hexagon specific tests
in order to compensate for new order of instructions generated by the
Hexagon backend __with scheduler disabled__.
- SVN revision 149130. LLVM verification test run for x86 platform
detects no additional failures.
Comments and reviews are eagerly anticipated J
</pre>
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<pre wrap="">
Hi Sergei,
I'm glad to see a VLIW scheduler proposed for LLVM. We are working on
an LLVM backend for our Evergreen / Northern Islands open source drivers,
which are also VLIW. I'm hoping we can use this in our backend as well.
I just have a few questions and comments.
When you start doing bundle generation in the scheduler will you be
using the new MachineInstrBundle? How are you going to model bundle
constraints? I'm not familiar with the Hexagon architecture, but our
hardware has several bundle constraints. For example, some instructions
can only be in a certain slot within the bundle, while other instructions
fill all slots in the bundle. There is also a limit to the number of
constant registers (these are in a different register space than the GPRs)
that can be read from within the bundle, among other things. It would
be nice to have some way to apply these constraints in the scheduler.
A quick note on the patch, I noticed a few whitespace errors in
LinkAllCodegenComponents.h, SchedulerRegistry.h, and
HexagonInstrInfo.cpp
Nice Work!
-Tom Stellard
</pre>
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<pre wrap="">
Thanks.
Sergei Larin
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
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