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<div>Hi</div>
<div> </div>
<div>The attached patch file includes a fix for the following bug in AVX codegen for double-to-int conversions:</div>
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<li>"fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.</li><li>Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for “fp_to_sint” DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.</li><li>Consequently, the conversion produces incorrect numbers.</li></ul>
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<div>The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode. </div>
<div>As “fp_to_sint” DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn’t have an impact on other LLVM flows.</div>
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<div>The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec). </div>
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<div>I’d like to commit the fix to the LLVM trunk, and your feedback will be mostly appreciated.</div>
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<div>Thanks,</div>
<div> Victor</div>
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