<html><head><base href="x-msg://491/"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Can you confirm that this change is not predicated on OptimizeForSize and it's not designed to trade off speed for code size? I'm pretty sure that's what you mean but I want to be sure.<div><br></div><div>Thanks,</div><div><br></div><div>Evan</div><div><br><div><div>On Jan 23, 2012, at 5:11 PM, Zino Benaissa wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><span class="Apple-style-span" style="border-collapse: separate; font-family: Helvetica; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-border-horizontal-spacing: 0px; -webkit-border-vertical-spacing: 0px; -webkit-text-decorations-in-effect: none; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; font-size: medium; "><div lang="EN-US" link="blue" vlink="purple"><div class="WordSection1" style="page: WordSection1; "><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><b>Description:<o:p></o:p></b></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">This contribution extends LLVM greedy Register Allocator to optimize for code size when LLVM compiler targets ARM Thumb 2 instruction set. This heuristic favors<b><i><span style="color: rgb(31, 73, 125); "><span class="Apple-converted-space"> </span></span></i></b>assigning register R0 through R7 to operands used in instruction that can be encoded in 16 bits (16-bit is allowed only if R0-7 are used). Operands that appear most frequently in a function (and in instructions that qualify) get R0-7 register.<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">This heuristic is turned on by default and has impact on generated code only if -mthumb compiler switch is used. To turn this heuristic off use -disable-favor-r0-7 feature flag.<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><o:p> </o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">This patch modifies:<span class="Apple-converted-space"> </span><br>1) The LLVM greedy register allocator located in LLVM/CodeGen directory: To add the new code size heuristic.<br>2) The ARM-specific flies located in LLVM/Target/ARM directory: To add the function that determines<span style="color: rgb(31, 73, 125); "><span class="Apple-converted-space"> </span></span>which instruction can be encoded in 16-bits and a fix to enable the compiler to emit CMN instruction in 16-bits encoding.<span class="Apple-converted-space"> </span><br>3) The LLVM test suite: fix test/CodeGen/Thumb2/thumb2-cmn.ll test.<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><span style="color: rgb(31, 73, 125); "><o:p> </o:p></span></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><b>Performance impact:<o:p></o:p></b></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">I focused on –Os and –mthumb flags. But observed similar improvement with –O3 and –mthumb. Runtime measured on Qualcomm 8660.<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">Code size:<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0.5in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; text-indent: -0.25in; "><span>-<span style="font: normal normal normal 7pt/normal 'Times New Roman'; "> <span class="Apple-converted-space"> </span></span></span>SPEC2000 benchmarks between 0 to 0.6% code size reduction (with no noticeable regression). <o:p></o:p></div><div style="margin-right: 0in; margin-left: 0.5in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; text-indent: -0.25in; "><span>-<span style="font: normal normal normal 7pt/normal 'Times New Roman'; "> <span class="Apple-converted-space"> </span></span></span>EEMBC benchmarks between 0 to 6% reduction (no noticeable regression). Automotive and Networking average about 1% code size reduction and Consumer about 0.5%.<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">Runtime:<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0.5in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; text-indent: -0.25in; "><span>-<span style="font: normal normal normal 7pt/normal 'Times New Roman'; "> <span class="Apple-converted-space"> </span></span></span>SPEC2000 between -1% and 6% speed up (Spec2k/ammp 6%)<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0.5in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; text-indent: -0.25in; "><span>-<span style="font: normal normal normal 7pt/normal 'Times New Roman'; "> <span class="Apple-converted-space"> </span></span></span>EEMBC overall averages faster -1 to 5%.<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><span style="color: rgb(31, 73, 125); "><o:p></o:p></span></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><b>Modified:<o:p></o:p></b></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> test/CodeGen/Thumb2/thumb2-cmn.ll<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> include/llvm/Target/TargetInstrInfo.h<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> include/llvm/CodeGen/LiveInterval.h<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> lib/Target/ARM/Thumb2SizeReduction.cpp<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> lib/Target/ARM/ARMBaseInstrInfo.cpp<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> lib/Target/ARM/ARMBaseInstrInfo.h<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> lib/CodeGen/RegAllocGreedy.cpp<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> lib/CodeGen/CalcSpillWeights.cpp<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "> <o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">for details see RACodeSize.txt<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><o:p> </o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; "><b>Testing:<o:p></o:p></b></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">See ARMTestSuiteResult.txt and ARMSimple-Os-mthumb.txt<o:p></o:p></div><div style="margin-right: 0in; margin-left: 0in; font-size: 11pt; font-family: Calibri, sans-serif; margin-top: 0in; margin-bottom: 0.0001pt; ">Note –O3 is also completed on X86 and ARM CPUs<span style="color: rgb(31, 73, 125); "><o:p></o:p></span></div></div><span><RACodeSize.txt></span><span><ARMTestSuiteResult.txt></span><span><ARMsimple-Os-mthumb.txt></span>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu" style="color: blue; text-decoration: underline; ">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" style="color: blue; text-decoration: underline; ">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></div></span></blockquote></div><br></div></body></html>