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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><b>Description: <o:p></o:p></b></p><p class=MsoNormal>This contribution extends LLVM greedy Register Allocator to optimize for code size when LLVM compiler targets ARM Thumb 2 instruction set. This heuristic favors<b><i><span style='color:#1F497D'> </span></i></b>assigning register R0 through R7 to operands used in instruction that can be encoded in 16 bits (16-bit is allowed only if R0-7 are used). Operands that appear most frequently in a function (and in instructions that qualify) get R0-7 register.<o:p></o:p></p><p class=MsoNormal>This heuristic is turned on by default and has impact on generated code only if -mthumb compiler switch is used. To turn this heuristic off use -disable-favor-r0-7 feature flag. <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>This patch modifies: <br>1) The LLVM greedy register allocator located in LLVM/CodeGen directory: To add the new code size heuristic.<br>2) The ARM-specific flies located in LLVM/Target/ARM directory: To add the function that determines<span style='color:#1F497D'> </span>which instruction can be encoded in 16-bits and a fix to enable the compiler to emit CMN instruction in 16-bits encoding. <br>3) The LLVM test suite: fix test/CodeGen/Thumb2/thumb2-cmn.ll test.<o:p></o:p></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b>Performance impact: <o:p></o:p></b></p><p class=MsoNormal>I focused on –Os and –mthumb flags. But observed similar improvement with –O3 and –mthumb. Runtime measured on Qualcomm 8660.<o:p></o:p></p><p class=MsoNormal>Code size:<o:p></o:p></p><p class=MsoListParagraph style='text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>SPEC2000 benchmarks between 0 to 0.6% code size reduction (with no noticeable regression). <o:p></o:p></p><p class=MsoListParagraph style='text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>EEMBC benchmarks between 0 to 6% reduction (no noticeable regression). Automotive and Networking average about 1% code size reduction and Consumer about 0.5%.<o:p></o:p></p><p class=MsoNormal>Runtime:<o:p></o:p></p><p class=MsoListParagraph style='text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>SPEC2000 between -1% and 6% speed up (Spec2k/ammp 6%)<o:p></o:p></p><p class=MsoListParagraph style='text-indent:-.25in;mso-list:l0 level1 lfo1'><![if !supportLists]><span style='mso-list:Ignore'>-<span style='font:7.0pt "Times New Roman"'> </span></span><![endif]>EEMBC overall averages faster -1 to 5%.<o:p></o:p></p><p class=MsoNormal><span style='color:#1F497D'> <o:p></o:p></span></p><p class=MsoNormal><b>Modified:<o:p></o:p></b></p><p class=MsoNormal> test/CodeGen/Thumb2/thumb2-cmn.ll<o:p></o:p></p><p class=MsoNormal> include/llvm/Target/TargetInstrInfo.h<o:p></o:p></p><p class=MsoNormal> include/llvm/CodeGen/LiveInterval.h<o:p></o:p></p><p class=MsoNormal> lib/Target/ARM/Thumb2SizeReduction.cpp<o:p></o:p></p><p class=MsoNormal> lib/Target/ARM/ARMBaseInstrInfo.cpp<o:p></o:p></p><p class=MsoNormal> lib/Target/ARM/ARMBaseInstrInfo.h<o:p></o:p></p><p class=MsoNormal> lib/CodeGen/RegAllocGreedy.cpp<o:p></o:p></p><p class=MsoNormal> lib/CodeGen/CalcSpillWeights.cpp<o:p></o:p></p><p class=MsoNormal> <o:p></o:p></p><p class=MsoNormal>for details see RACodeSize.txt <o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><b>Testing: <o:p></o:p></b></p><p class=MsoNormal>See ARMTestSuiteResult.txt and ARMSimple-Os-mthumb.txt<o:p></o:p></p><p class=MsoNormal>Note –O3 is also completed on X86 and ARM CPUs<span style='color:#1F497D'><o:p></o:p></span></p></div></body></html>