<html><body><div style="color:#000; background-color:#fff; font-family:arial, helvetica, sans-serif;font-size:10pt"><div>What should be done with the other extensions: FMA3, FMA4 and XOP? Should they also be included in this list?</div><div><br></div><div>- Jan<br></div><div><br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; margin-top: 5px; padding-left: 5px;"> <div style="font-family: arial, helvetica, sans-serif; font-size: 10pt;"> <div style="font-family: times new roman, new york, times, serif; font-size: 12pt;"> <font face="Arial" size="2"> <hr size="1"> <b><span style="font-weight:bold;">From:</span></b> Craig Topper <craig.topper@gmail.com><br> <b><span style="font-weight: bold;">To:</span></b> llvm-commits@cs.uiuc.edu <br> <b><span style="font-weight: bold;">Sent:</span></b> Monday, January 9, 2012 4:02 AM<br> <b><span style="font-weight: bold;">Subject:</span></b> [llvm-commits] [llvm] r147770 - in
/llvm/trunk/lib/Target/X86: X86.td X86Subtarget.cpp X86Subtarget.h<br> </font> <br>
Author: ctopper<br>Date: Mon Jan 9 03:02:13 2012<br>New Revision: 147770<br><br>URL: http://llvm.org/viewvc/llvm-project?rev=147770&view=rev<br>Log:<br>Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.<br><br>Modified:<br> llvm/trunk/lib/Target/X86/X86.td<br> llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br> llvm/trunk/lib/Target/X86/X86Subtarget.h<br><br>Modified: llvm/trunk/lib/Target/X86/X86.td<br>URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=147770&r1=147769&r2=147770&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86.td (original)<br>+++ llvm/trunk/lib/Target/X86/X86.td Mon Jan 9 03:02:13 2012<br>@@ -80,9 +80,10 @@<br>
"Support SSE 4a instructions",<br> [FeatureSSE3]>;<br> <br>-def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",<br>- "Enable AVX instructions">;<br>-def FeatureAVX2 : SubtargetFeature<"avx2", "HasAVX2", "true",<br>+def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",<br>+ "Enable AVX instructions",<br>+
[FeatureSSE42]>;<br>+def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",<br> "Enable AVX2 instructions",<br> [FeatureAVX]>;<br> def FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true",<br><br>Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=147770&r1=147769&r2=147770&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Jan 9 03:02:13 2012<br>@@ -198,7
+198,7 @@<br> if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}<br> if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}<br> // FIXME: AVX codegen support is not ready.<br>- //if ((ECX >> 28) & 1) { HasAVX = true; ToggleFeature(X86::FeatureAVX); }<br>+ //if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }<br> <br> bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;<br> bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;<br>@@ -295,7 +295,7 @@<br> }<br> // FIXME: AVX2 codegen support is not ready.<br> //if ((EBX >> 5) & 0x1) {<br>- // HasAVX2 = true;<br>+ // X86SSELevel = AVX2;;<br> //
ToggleFeature(X86::FeatureAVX2);<br> //}<br> if ((EBX >> 8) & 0x1) {<br>@@ -317,8 +317,6 @@<br> , HasX86_64(false)<br> , HasPOPCNT(false)<br> , HasSSE4A(false)<br>- , HasAVX(false)<br>- , HasAVX2(false)<br> , HasAES(false)<br> , HasCLMUL(false)<br> , HasFMA3(false)<br>@@ -372,7 +370,7 @@<br> HasX86_64 = true; ToggleFeature(X86::Feature64Bit);<br> HasCMov = true; ToggleFeature(X86::FeatureCMOV);<br> <br>- if (!HasAVX && X86SSELevel < SSE2) {<br>+ if (X86SSELevel < SSE2) {<br> X86SSELevel = SSE2;<br> ToggleFeature(X86::FeatureSSE1);<br> ToggleFeature(X86::FeatureSSE2);<br>@@ -385,9 +383,6 @@<br> if (In64BitMode)<br>
ToggleFeature(X86::Mode64Bit);<br> <br>- if (HasAVX)<br>- X86SSELevel = MMX;<br>- <br> DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel<br> << ", 3DNowLevel " << X863DNowLevel<br> << ", 64bit " << HasX86_64 << "\n");<br><br>Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h<br>URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=147770&r1=147769&r2=147770&view=diff<br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)<br>+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon Jan 9 03:02:13 2012<br>@@ -42,7 +42,7 @@<br> class X86Subtarget : public X86GenSubtargetInfo {<br> protected:<br> enum X86SSEEnum {<br>-
NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42<br>+ NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2<br> };<br> <br> enum X863DNowEnum {<br>@@ -75,12 +75,6 @@<br> /// HasSSE4A - True if the processor supports SSE4A instructions.<br> bool HasSSE4A;<br> <br>- /// HasAVX - Target has AVX instructions<br>- bool HasAVX;<br>-<br>- /// HasAVX2 - Target has AVX2 instructions<br>- bool HasAVX2;<br>-<br> /// HasAES - Target has AES instructions<br> bool HasAES;<br> <br>@@ -179,24 +173,24 @@<br> <br> bool hasCMov() const { return HasCMov; }<br> bool hasMMX() const { return X86SSELevel >= MMX; }<br>- bool hasSSE1() const { return X86SSELevel >= SSE1; }<br>- bool hasSSE2() const { return X86SSELevel >= SSE2; }<br>- bool hasSSE3() const { return X86SSELevel >= SSE3; }<br>- bool hasSSSE3() const { return
X86SSELevel >= SSSE3; }<br>- bool hasSSE41() const { return X86SSELevel >= SSE41; }<br>- bool hasSSE42() const { return X86SSELevel >= SSE42; }<br>+ bool hasSSE1() const { return X86SSELevel >= SSE1 && !hasAVX(); }<br>+ bool hasSSE2() const { return X86SSELevel >= SSE2 && !hasAVX(); }<br>+ bool hasSSE3() const { return X86SSELevel >= SSE3 && !hasAVX(); }<br>+ bool hasSSSE3() const { return X86SSELevel >= SSSE3 && !hasAVX(); }<br>+ bool hasSSE41() const { return X86SSELevel >= SSE41 && !hasAVX(); }<br>+ bool hasSSE42() const { return X86SSELevel >= SSE42 && !hasAVX(); }<br> bool hasSSE4A() const { return HasSSE4A; }<br> bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }<br> bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }<br> bool hasPOPCNT() const { return HasPOPCNT;
}<br>- bool hasAVX() const { return HasAVX; }<br>- bool hasAVX2() const { return HasAVX2; }<br>- bool hasXMM() const { return hasSSE1() || hasAVX(); }<br>- bool hasXMMInt() const { return hasSSE2() || hasAVX(); }<br>- bool hasSSE3orAVX() const { return hasSSE3() || hasAVX(); }<br>- bool hasSSSE3orAVX() const { return hasSSSE3() || hasAVX(); }<br>- bool hasSSE41orAVX() const { return hasSSE41() || hasAVX(); }<br>- bool hasSSE42orAVX() const { return hasSSE42() || hasAVX(); }<br>+ bool hasAVX() const { return X86SSELevel >= AVX; }<br>+ bool hasAVX2() const { return X86SSELevel >= AVX2; }<br>+ bool hasXMM() const { return X86SSELevel >= SSE1; }<br>+ bool hasXMMInt() const { return X86SSELevel >= SSE2; }<br>+ bool hasSSE3orAVX() const { return X86SSELevel >= SSE3; }<br>+ bool hasSSSE3orAVX() const { return X86SSELevel >= SSSE3; }<br>+ bool
hasSSE41orAVX() const { return X86SSELevel >= SSE41; }<br>+ bool hasSSE42orAVX() const { return X86SSELevel >= SSE42; }<br> bool hasAES() const { return HasAES; }<br> bool hasCLMUL() const { return HasCLMUL; }<br> bool hasFMA3() const { return HasFMA3; }<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a ymailto="mailto:llvm-commits@cs.uiuc.edu" href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br><br><br> </div> </div> </blockquote></div> </div></body></html>