Doesn't having SSE42 explicitly imply popcnt make disabling popcnt through mattr also disable SSE42?<br><br><div class="gmail_quote">On Thu, Dec 29, 2011 at 12:20 PM, Benjamin Kramer <span dir="ltr"><<a href="mailto:benny.kra@googlemail.com">benny.kra@googlemail.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
On 29.12.2011, at 16:51, Craig Topper wrote:<br>
<br>
> Author: ctopper<br>
> Date: Thu Dec 29 09:51:45 2011<br>
> New Revision: 147339<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=147339&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=147339&view=rev</a><br>
> Log:<br>
> Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled on its own without disabling SSE4.2 or SSE4A.<br>
<br>
Hi Craig,<br>
<br>
What's your intention here? popcnt is part of sse42 and sse4a so you won't find a processor that has sse42/a and not popcnt. It simplifies the model descriptions in this file. You can still selectively enable sse42 and disable the popcnt feature (e.g. "llc -mattr=+sse42,-popcnt" or "clang -msse4.2 -mno-popcnt") and it won't emit popcnt instructions.<br>

<br>
This patch disables popcnt emission unless it's explicitly enabled (think of the JIT). Please revert this patch.<br>
<br>
- Ben<br>
<br>
><br>
> Modified:<br>
>    llvm/trunk/lib/Target/X86/X86.td<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=147339&r1=147338&r2=147339&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=147339&r1=147338&r2=147339&view=diff</a><br>

> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86.td Thu Dec 29 09:51:45 2011<br>
> @@ -55,7 +55,7 @@<br>
>                                       [FeatureSSSE3]>;<br>
> def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",<br>
>                                       "Enable SSE 4.2 instructions",<br>
> -                                      [FeatureSSE41, FeaturePOPCNT]>;<br>
> +                                      [FeatureSSE41]>;<br>
> def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",<br>
>                                       "Enable 3DNow! instructions",<br>
>                                       [FeatureMMX]>;<br>
> @@ -77,8 +77,7 @@<br>
>                                         "IsUAMemFast", "true",<br>
>                                         "Fast unaligned memory access">;<br>
> def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",<br>
> -                                      "Support SSE 4a instructions",<br>
> -                                      [FeaturePOPCNT]>;<br>
> +                                      "Support SSE 4a instructions">;<br>
><br>
> def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",<br>
>                                       "Enable AVX instructions">;<br>
><br>
><br>
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<br>
</blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>