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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple style='word-wrap: break-word;-webkit-nbsp-mode: space;-webkit-line-break: after-white-space'><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Chad, Anton, Bruno,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thank you for the suggestion.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Unfortunately, it won’t work in the case of brcond.ll file.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Indeed I can introduce different “check-prefix” values in order to separate checks for “core2” case from those for “penryn” case. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>However, the compilation of <b>all functions</b> in a file will be done <b>unconditionally</b> for both “RUN” cases. And this will inevitably lead to the test failure (in instruction selection) when a function using “ptest” LLVM intrinsic will be processed with “-mcpu=core2” option. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>That’s why I was not able to include the test cases for “ptest” intrinsic sequence to a file which will be compiled for a pre-Penryn target.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>A solution which does work is to have legacy brcond.ll LIT tests running under “-mcpu=penryn”. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I’m attaching the file. <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Are you OK with such solution?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Best Regards,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> Victor<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Chad Rosier [mailto:mcrosier@apple.com] <br><b>Sent:</b> Tuesday, December 06, 2011 19:48<br><b>To:</b> Umansky, Victor<br><b>Cc:</b> Bruno Cardoso Lopes; llvm-commits@cs.uiuc.edu<br><b>Subject:</b> Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review<o:p></o:p></span></p></div></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi Victor,<o:p></o:p></p><div><p class=MsoNormal>You should be able to include the test in brcond.ll by specifying a new run line and using the -check-prefix option.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>See: <a href="http://llvm.org/docs/TestingGuide.html#FileCheck">http://llvm.org/docs/TestingGuide.html#FileCheck</a><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>It would look something like this:<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><div><p class=MsoNormal>; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=penryn | FileCheck %s -check-prefix=FOO<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>declare i32 @llvm.x86.sse41.ptestz(<4 x float> %p1, <4 x float> %p2) nounwind<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>define <4 x float> @test1(<4 x float> %a, <4 x float> %b) nounwind {<o:p></o:p></p></div><div><p class=MsoNormal>entry:<o:p></o:p></p></div><div><p class=MsoNormal>; FOO: test1:<o:p></o:p></p></div><div><p class=MsoNormal>; FOO: ptest<o:p></o:p></p></div><div><p class=MsoNormal>; FOO-NEXT:<span class=apple-tab-span> </span>je<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>etc..<o:p></o:p></p></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal> Chad<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p><div><div><p class=MsoNormal>On Dec 6, 2011, at 12:52 AM, Umansky, Victor wrote:<o:p></o:p></p></div><p class=MsoNormal><br><br><o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Bruno,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thank you for the response.</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I’ve changed the LIT test towards common look (attached).</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Unfortunately, I cannot put it inside brcond.ll because the “ptest” instruction was introduced only with SSE4.1 (i.e. requires “-mcpu=penryn”), while the current version of brcond.ll is processed with “-mcpu=core2”.</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Will the replacement of–mcpu in brcond.ll with “penryn” be backward-compat with regard to LIT results?</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Best Regards,</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> Victor</span><o:p></o:p></p></div><div><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> </span><o:p></o:p></p></div><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in;border-width:initial;border-color:initial'><div><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span class=apple-converted-space><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> </span></span><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>Bruno Cardoso Lopes [mailto:bruno.cardoso@gmail.com]<span class=apple-converted-space> </span><br><b>Sent:</b><span class=apple-converted-space> </span>Monday, December 05, 2011 19:13<br><b>To:</b><span class=apple-converted-space> </span>Umansky, Victor<br><b>Cc:</b><span class=apple-converted-space> </span><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><b>Subject:</b><span class=apple-converted-space> </span>Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review</span><o:p></o:p></p></div></div><div><p class=MsoNormal> <o:p></o:p></p></div><p class=MsoNormal style='margin-bottom:12.0pt'>Hi Victor,<o:p></o:p></p><div><div><p class=MsoNormal>On Mon, Dec 5, 2011 at 10:26 AM, Umansky, Victor <<a href="mailto:victor.umansky@intel.com">victor.umansky@intel.com</a>> wrote:<o:p></o:p></p></div><div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>Hi,</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>My name is Victor Umansky; I’m an engineer in Intel OpenCL Team.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The attached patch contains an optimization of ptest-conditioned branch.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>I.e., the following LLVM IR code</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><table class=MsoNormalTable border=0 cellspacing=0 cellpadding=0 width=738 style='width:6.15in;border-collapse:collapse;border-width:initial;border-color:initial'><tr><td style='border:inset 1.0pt;padding:.75pt .75pt .75pt .75pt'><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind<span class=apple-converted-space> </span><br> %tmp = and i32 %res, 1<span class=apple-converted-space> </span><br> %one = icmp eq i32 %tmp, 0<span class=apple-converted-space> </span><br> br i1 %one, label %label1, label %label2</span><o:p></o:p></p></div></td></tr></table><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>ends with the following x86 machine code sequence:</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><table class=MsoNormalTable border=0 cellspacing=0 cellpadding=0 width=738 style='width:6.15in;border-collapse:collapse;border-width:initial;border-color:initial'><tr><td style='border:inset 1.0pt;padding:.75pt .75pt .75pt .75pt'><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> ptest XMM3, XMM3<span class=apple-converted-space> </span><br> sete AL<span class=apple-converted-space> </span><br> movzx EAX, AL<span class=apple-converted-space> </span><br> test EAX, EAX<span class=apple-converted-space> </span><br> jne LBB18_26</span><o:p></o:p></p></div></td></tr></table><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>which can be optimized to:</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><table class=MsoNormalTable border=0 cellspacing=0 cellpadding=0 width=738 style='width:6.15in;border-collapse:collapse;border-width:initial;border-color:initial'><tr><td style='border:inset 1.0pt;padding:.75pt .75pt .75pt .75pt'><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> ptest XMM3, XMM3<span class=apple-converted-space> </span><br> je LBB18_26</span><o:p></o:p></p></div></td></tr></table><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The current machine code sequence stems from the need to coordinate<span class=apple-converted-space> </span><b>i32 return type</b><span class=apple-converted-space> </span>from the ptestz intrinsic with<span class=apple-converted-space> </span><b>i1 condition type</b><span class=apple-converted-space> </span>for branch IR instruction.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>Consequently we can optimize it in x86 codegen backend where the both condition producer (ptest) amd consumer (jcc) use the<span class=apple-converted-space> </span><b>same x86 EFLAGS register</b>, and thus in-between conversions of the condition can be quietly dropped.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The optimization is focused on x86 DAG combining (post-legalization stage) which recognizes the sequence and converts it to the minimized one.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The attached patch file includes both the x86 backend instruction combining modification and a LIT regression test for it.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>I’d like to commit the fix to the LLVM trunk, and your feedback will be mostly appreciated.</span><o:p></o:p></p></div></div><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> </span><o:p></o:p></p></div></div></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>+; RUN: llc %s -march=x86-64 -mcpu=corei7 -o %t.asm<o:p></o:p></p></div></div><div><div><p class=MsoNormal>+; RUN: FileCheck %s --input-file=%t.asm<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><div><p class=MsoNormal>Please do like the other tests, and read the file with "< %s". Also, place it under test/CodeGen/X86/brcond.ll<o:p></o:p></p></div></div><div><div><p class=MsoNormal> <o:p></o:p></p></div></div><div><p class=MsoNormal>--<span class=apple-converted-space> </span><br>Bruno Cardoso Lopes<span class=apple-converted-space> </span><br><a href="http://www.brunocardoso.cc">http://www.brunocardoso.cc</a><o:p></o:p></p></div><p class=MsoNormal><span style='font-family:"Courier New"'>---------------------------------------------------------------------<br>Intel Israel (74) Limited<br><br>This e-mail and any attachments may contain confidential material for<br>the sole use of the intended recipient(s). Any review or distribution<br>by others is strictly prohibited. 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