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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi Bruno,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thank you for the response.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I’ve changed the LIT test towards common look (attached).<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Unfortunately, I cannot put it inside brcond.ll because the “ptest” instruction was introduced only with SSE4.1 (i.e. requires “-mcpu=penryn”), while the current version of brcond.ll is processed with “-mcpu=core2”.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Will the replacement of–mcpu in brcond.ll with “penryn” be backward-compat with regard to LIT results?<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Best Regards,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'> Victor<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><div style='border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> Bruno Cardoso Lopes [mailto:bruno.cardoso@gmail.com] <br><b>Sent:</b> Monday, December 05, 2011 19:13<br><b>To:</b> Umansky, Victor<br><b>Cc:</b> llvm-commits@cs.uiuc.edu<br><b>Subject:</b> Re: [llvm-commits] x86 branch sequence optimization in LLVM code gen: please review<o:p></o:p></span></p></div><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal style='margin-bottom:12.0pt'>Hi Victor,<o:p></o:p></p><div><p class=MsoNormal>On Mon, Dec 5, 2011 at 10:26 AM, Umansky, Victor <<a href="mailto:victor.umansky@intel.com">victor.umansky@intel.com</a>> wrote:<o:p></o:p></p><div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>Hi,<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>My name is Victor Umansky; I’m an engineer in Intel OpenCL Team.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The attached patch contains an optimization of ptest-conditioned branch. <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>I.e., the following LLVM IR code<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=738 style='width:6.15in;border-collapse:collapse;border:none'><tr><td style='padding:.75pt .75pt .75pt .75pt'><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind <br> %tmp = and i32 %res, 1 <br> %one = icmp eq i32 %tmp, 0 <br> br i1 %one, label %label1, label %label2</span><o:p></o:p></p></td></tr></table><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>ends with the following x86 machine code sequence:<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=738 style='width:6.15in;border-collapse:collapse;border:none'><tr><td style='padding:.75pt .75pt .75pt .75pt'><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> ptest XMM3, XMM3 <br> sete AL <br> movzx EAX, AL <br> test EAX, EAX <br> jne LBB18_26</span><o:p></o:p></p></td></tr></table><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>which can be optimized to: <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><table class=MsoNormalTable border=1 cellspacing=0 cellpadding=0 width=738 style='width:6.15in;border-collapse:collapse;border:none'><tr><td style='padding:.75pt .75pt .75pt .75pt'><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Verdana","sans-serif"'> ptest XMM3, XMM3 <br> je LBB18_26</span><o:p></o:p></p></td></tr></table><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The current machine code sequence stems from the need to coordinate <b>i32 return type</b> from the ptestz intrinsic with <b>i1 condition type</b> for branch IR instruction. <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>Consequently we can optimize it in x86 codegen backend where the both condition producer (ptest) amd consumer (jcc) use the <b>same x86 EFLAGS register</b>, and thus in-between conversions of the condition can be quietly dropped.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The optimization is focused on x86 DAG combining (post-legalization stage) which recognizes the sequence and converts it to the minimized one.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>The attached patch file includes both the x86 backend instruction combining modification and a LIT regression test for it.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'> <o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'>I’d like to commit the fix to the LLVM trunk, and your feedback will be mostly appreciated.<o:p></o:p></span></p></div><div><p class=MsoNormal><span style='font-size:10.0pt;font-family:"Calibri","sans-serif"'><o:p> </o:p></span></p></div></div></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>+; RUN: llc %s -march=x86-64 -mcpu=corei7 -o %t.asm<o:p></o:p></p></div><div><p class=MsoNormal>+; RUN: FileCheck %s --input-file=%t.asm<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Please do like the other tests, and read the file with "< %s". Also, place it under test/CodeGen/X86/brcond.ll<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal>-- <br>Bruno Cardoso Lopes <br><a href="http://www.brunocardoso.cc">http://www.brunocardoso.cc</a><o:p></o:p></p></div><font face="monospace">---------------------------------------------------------------------<br>
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