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<tt>Folks,<br>
<br>
Did anyone get a chance to take a look at the patch? Is it okay to
commit?<br>
<br>
Thanks<br>
-Anshu<br>
<br>
</tt><tt>--<br>
Qualcomm Innovation Center, Inc is a member of Code Aurora Forum<br>
<br>
<br>
</tt>On 11/18/2011 10:51 PM, Anshuman Dasgupta wrote:
<blockquote cite="mid:4EC735D2.4040801@codeaurora.org" type="cite">
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<tt>Hi,<br>
<br>
I'm attaching a patch that adds support for a deterministic
finite automaton (DFA) based packetizer for VLIW architectures.
Specifically, it automatically generates a DFA from a VLIW
target's Schedule.td file. In a VLIW machine, an instruction can
typically be dispatched to one or many function units. The DFA
determines whether there exists a legal mapping of instructions
to functional unit assignments in a packet. This DFA can then be
queried by a backend packetization pass to determine which
instructions can be grouped into a VLIW packet.<br>
<br>
This patch contains the machine-independent code that adds a
component to TableGen. The component autogenerates the DFA and
implements the API that can be used to query the DFA during
packetization. This can be used by any VLIW target to packetize
its instructions. After the Hexagon backend is committed, I will
post another Hexagon-specific patch that uses this mechanism to
construct packets in the Hexagon backend. I ran the llvm test
suite and this patch did not cause any regressions.<br>
<br>
I would appreciate reviews and comments.<br>
<br>
Thanks<br>
-Anshu<br>
<br>
</tt>
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Qualcomm Innovation Center, Inc is a member of Code Aurora Forum<br>
<br>
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