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<font size="2"><div class="PlainText">This patch enhances r141855 and fixes the failing test by adding the new -mattr=+bmi target attribute.<br>
<br>
Craig, is that correct?<br>
<br>
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<br>
Joe Abbey<br>
Software Architect<br>
Arxan Technologies, Inc.<br>
1305 Cumberland Ave, Ste 215<br>
West Lafayette, IN 47906<br>
W: 765-889-4756 x2<br>
C: 765-464-9893<br>
jabbey@arxan.com<br>
<a href="http://www.arxan.com">www.arxan.com</a><br>
<br>
<br>
On Oct 13, 2011, at 3:27 AM, Bill Wendling wrote:<br>
<br>
> Hi Craig,<br>
> <br>
> This is causing a failure on one of the public buildbots:<br>
> <br>
> <a href="http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101">http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101</a><br>
> <br>
> Could you take a look please?<br>
> <br>
> -bw<br>
> <br>
> On Oct 13, 2011, at 12:09 AM, Craig Topper wrote:<br>
> <br>
>> Author: ctopper<br>
>> Date: Thu Oct 13 02:09:14 2011<br>
>> New Revision: 141854<br>
>> <br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=141854&view=rev">http://llvm.org/viewvc/llvm-project?rev=141854&view=rev</a><br>
>> Log:<br>
>> Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.<br>
>> <br>
>> Added:<br>
>> llvm/trunk/test/CodeGen/X86/bmi.ll<br>
>> Modified:<br>
>> llvm/trunk/lib/Target/X86/X86.td<br>
>> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
>> llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
>> llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
>> llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt<br>
>> llvm/trunk/test/MC/Disassembler/X86/x86-32.txt<br>
>> <br>
>> Modified: llvm/trunk/lib/Target/X86/X86.td<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=141854&r1=141853&r2=141854&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=141854&r1=141853&r2=141854&view=diff</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/lib/Target/X86/X86.td (original)<br>
>> +++ llvm/trunk/lib/Target/X86/X86.td Thu Oct 13 02:09:14 2011<br>
>> @@ -104,6 +104,8 @@<br>
>> "Support 16-bit floating point conversion instructions">;<br>
>> def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",<br>
>> "Support LZCNT instruction">;<br>
>> +def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",<br>
>> + "Support BMI instructions">;<br>
>> <br>
>> //===----------------------------------------------------------------------===//<br>
>> // X86 processors supported.<br>
>> @@ -157,6 +159,11 @@<br>
>> def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,<br>
>> FeatureAES, FeatureCLMUL,<br>
>> FeatureRDRAND, FeatureF16C]>;<br>
>> +// Haswell<br>
>> +def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,<br>
>> + FeatureCLMUL, FeatureRDRAND, FeatureF16C,<br>
>> + FeatureFMA3, FeatureMOVBE, FeatureLZCNT,<br>
>> + FeatureBMI]>;<br>
>> <br>
>> def : Proc<"k6", [FeatureMMX]>;<br>
>> def : Proc<"k6-2", [Feature3DNow]>;<br>
>> <br>
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=141854&r1=141853&r2=141854&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=141854&r1=141853&r2=141854&view=diff</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Oct 13 02:09:14 2011<br>
>> @@ -379,11 +379,15 @@<br>
>> setOperationAction(ISD::FREM , MVT::f80 , Expand);<br>
>> setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);<br>
>> <br>
>> - setOperationAction(ISD::CTTZ , MVT::i8 , Custom);<br>
>> - setOperationAction(ISD::CTTZ , MVT::i16 , Custom);<br>
>> - setOperationAction(ISD::CTTZ , MVT::i32 , Custom);<br>
>> - if (Subtarget->is64Bit())<br>
>> - setOperationAction(ISD::CTTZ , MVT::i64 , Custom);<br>
>> + if (Subtarget->hasBMI()) {<br>
>> + setOperationAction(ISD::CTTZ , MVT::i8 , Promote);<br>
>> + } else {<br>
>> + setOperationAction(ISD::CTTZ , MVT::i8 , Custom);<br>
>> + setOperationAction(ISD::CTTZ , MVT::i16 , Custom);<br>
>> + setOperationAction(ISD::CTTZ , MVT::i32 , Custom);<br>
>> + if (Subtarget->is64Bit())<br>
>> + setOperationAction(ISD::CTTZ , MVT::i64 , Custom);<br>
>> + }<br>
>> <br>
>> if (Subtarget->hasLZCNT()) {<br>
>> setOperationAction(ISD::CTLZ , MVT::i8 , Promote);<br>
>> <br>
>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=141854&r1=141853&r2=141854&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=141854&r1=141853&r2=141854&view=diff</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Oct 13 02:09:14 2011<br>
>> @@ -478,6 +478,7 @@<br>
>> def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;<br>
>> def HasF16C : Predicate<"Subtarget->hasF16C()">;<br>
>> def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;<br>
>> +def HasBMI : Predicate<"Subtarget->hasBMI()">;<br>
>> def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;<br>
>> def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;<br>
>> def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;<br>
>> @@ -1373,6 +1374,37 @@<br>
>> }<br>
>> <br>
>> //===----------------------------------------------------------------------===//<br>
>> +// BMI Instructions<br>
>> +//<br>
>> +let Predicates = [HasBMI], Defs = [EFLAGS] in {<br>
>> + def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),<br>
>> + "tzcnt{w}\t{$src, $dst|$dst, $src}",<br>
>> + [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,<br>
>> + OpSize;<br>
>> + def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),<br>
>> + "tzcnt{w}\t{$src, $dst|$dst, $src}",<br>
>> + [(set GR16:$dst, (cttz (loadi16 addr:$src))),<br>
>> + (implicit EFLAGS)]>, XS, OpSize;<br>
>> +<br>
>> + def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
>> + "tzcnt{l}\t{$src, $dst|$dst, $src}",<br>
>> + [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS;<br>
>> + def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
>> + "tzcnt{l}\t{$src, $dst|$dst, $src}",<br>
>> + [(set GR32:$dst, (cttz (loadi32 addr:$src))),<br>
>> + (implicit EFLAGS)]>, XS;<br>
>> +<br>
>> + def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
>> + "tzcnt{q}\t{$src, $dst|$dst, $src}",<br>
>> + [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,<br>
>> + XS;<br>
>> + def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),<br>
>> + "tzcnt{q}\t{$src, $dst|$dst, $src}",<br>
>> + [(set GR64:$dst, (cttz (loadi64 addr:$src))),<br>
>> + (implicit EFLAGS)]>, XS;<br>
>> +}<br>
>> +<br>
>> +//===----------------------------------------------------------------------===//<br>
>> // Subsystems.<br>
>> //===----------------------------------------------------------------------===//<br>
>> <br>
>> <br>
>> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=141854&r1=141853&r2=141854&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=141854&r1=141853&r2=141854&view=diff</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)<br>
>> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Oct 13 02:09:14 2011<br>
>> @@ -102,6 +102,9 @@<br>
>> /// HasLZCNT - Processor has LZCNT instruction.<br>
>> bool HasLZCNT;<br>
>> <br>
>> + /// HasBMI - Processor has BMI1 instructions.<br>
>> + bool HasBMI;<br>
>> +<br>
>> /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.<br>
>> bool IsBTMemSlow;<br>
>> <br>
>> @@ -188,6 +191,7 @@<br>
>> bool hasRDRAND() const { return HasRDRAND; }<br>
>> bool hasF16C() const { return HasF16C; }<br>
>> bool hasLZCNT() const { return HasLZCNT; }<br>
>> + bool hasBMI() const { return HasBMI; }<br>
>> bool isBTMemSlow() const { return IsBTMemSlow; }<br>
>> bool isUnalignedMemAccessFast() const { return IsUAMemFast; }<br>
>> bool hasVectorUAMem() const { return HasVectorUAMem; }<br>
>> <br>
>> Added: llvm/trunk/test/CodeGen/X86/bmi.ll<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=141854&view=auto">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=141854&view=auto</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/test/CodeGen/X86/bmi.ll (added)<br>
>> +++ llvm/trunk/test/CodeGen/X86/bmi.ll Thu Oct 13 02:09:14 2011<br>
>> @@ -0,0 +1,38 @@<br>
>> +; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s<br>
>> +<br>
>> +define i32 @t1(i32 %x) nounwind {<br>
>> + %tmp = tail call i32 @llvm.cttz.i32( i32 %x )<br>
>> + ret i32 %tmp<br>
>> +; CHECK: t1:<br>
>> +; CHECK: tzcntl<br>
>> +}<br>
>> +<br>
>> +declare i32 @llvm.cttz.i32(i32) nounwind readnone<br>
>> +<br>
>> +define i16 @t2(i16 %x) nounwind {<br>
>> + %tmp = tail call i16 @llvm.cttz.i16( i16 %x )<br>
>> + ret i16 %tmp<br>
>> +; CHECK: t2:<br>
>> +; CHECK: tzcntw<br>
>> +}<br>
>> +<br>
>> +declare i16 @llvm.cttz.i16(i16) nounwind readnone<br>
>> +<br>
>> +define i64 @t3(i64 %x) nounwind {<br>
>> + %tmp = tail call i64 @llvm.cttz.i64( i64 %x )<br>
>> + ret i64 %tmp<br>
>> +; CHECK: t3:<br>
>> +; CHECK: tzcntq<br>
>> +}<br>
>> +<br>
>> +declare i64 @llvm.cttz.i64(i64) nounwind readnone<br>
>> +<br>
>> +define i8 @t4(i8 %x) nounwind {<br>
>> + %tmp = tail call i8 @llvm.cttz.i8( i8 %x )<br>
>> + ret i8 %tmp<br>
>> +; CHECK: t4:<br>
>> +; CHECK: tzcntw<br>
>> +}<br>
>> +<br>
>> +declare i8 @llvm.cttz.i8(i8) nounwind readnone<br>
>> +<br>
>> <br>
>> Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=141854&r1=141853&r2=141854&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=141854&r1=141853&r2=141854&view=diff</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)<br>
>> +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Thu Oct 13 02:09:14 2011<br>
>> @@ -497,3 +497,12 @@<br>
>> <br>
>> # CHECK: lzcntq %rax, %rax<br>
>> 0xf3 0x48 0x0f 0xbd 0xc0<br>
>> +<br>
>> +# CHECK: tzcntl %eax, %eax<br>
>> +0xf3 0x0f 0xbc 0xc0<br>
>> +<br>
>> +# CHECK: tzcntw %ax, %ax<br>
>> +0x66 0xf3 0x0f 0xbc 0xc0<br>
>> +<br>
>> +# CHECK: tzcntq %rax, %rax<br>
>> +0xf3 0x48 0x0f 0xbc 0xc0<br>
>> <br>
>> Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt<br>
>> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=141854&r1=141853&r2=141854&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=141854&r1=141853&r2=141854&view=diff</a><br>
>> ==============================================================================<br>
>> --- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)<br>
>> +++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Thu Oct 13 02:09:14 2011<br>
>> @@ -477,3 +477,9 @@<br>
>> <br>
>> # CHECK: lzcntw %ax, %ax<br>
>> 0x66 0xf3 0x0f 0xbd 0xc0<br>
>> +<br>
>> +# CHECK: tzcntl %eax, %eax<br>
>> +0xf3 0x0f 0xbc 0xc0<br>
>> +<br>
>> +# CHECK: tzcntw %ax, %ax<br>
>> +0x66 0xf3 0x0f 0xbc 0xc0<br>
>> <br>
>> <br>
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