I'll fix it tonight unless someone beats me to it.<br><br><div class="gmail_quote">On Tue, Oct 4, 2011 at 12:25 AM, James Molloy <span dir="ltr"><<a href="mailto:james.molloy@arm.com">james.molloy@arm.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Hi Craig,<br>
<br>
This commit breaks our opensource build.<br>
<br>
X86DisassemblerDecoder.c:906:5: error: C++ style comments are not allowed in<br>
ISO C90<br>
<br>
Could you please change the comments to C-style?<br>
<br>
Cheers,<br>
<br>
James<br>
<br>
-----Original Message-----<br>
From: <a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a><br>
[mailto:<a href="mailto:llvm-commits-bounces@cs.uiuc.edu">llvm-commits-bounces@cs.uiuc.edu</a>] On Behalf Of Craig Topper<br>
Sent: 02 October 2011 17:56<br>
To: <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
Subject: [llvm-commits] [llvm] r140971 - in /llvm/trunk:<br>
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c<br>
test/MC/Disassembler/X86/simple-tests.txt<br>
<br>
Author: ctopper<br>
Date: Sun Oct  2 11:56:09 2011<br>
New Revision: 140971<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=140971&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=140971&view=rev</a><br>
Log:<br>
Special case disassembler handling of REX.B prefix on NOP instruction to<br>
decode as XCHG R8D, EAX instead. Fixes PR10344.<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c<br>
    llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt<br>
<br>
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X%0A86DisassemblerDecoder.c?rev=140971&r1=140970&r2=140971&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X<br>

86DisassemblerDecoder.c?rev=140971&r1=140970&r2=140971&view=diff</a><br>
============================================================================<br>
==<br>
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c<br>
(original)<br>
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Sun Oct<br>
2 11:56:09 2011<br>
@@ -58,8 +58,8 @@<br>
  * @return            - TRUE if the ModR/M byte is required, FALSE<br>
otherwise.<br>
  */<br>
 static int modRMRequired(OpcodeType type,<br>
-                                InstructionContext insnContext,<br>
-                                uint8_t opcode) {<br>
+                         InstructionContext insnContext,<br>
+                         uint8_t opcode) {<br>
   const struct ContextDecision* decision = 0;<br>
<br>
   switch (type) {<br>
@@ -885,6 +885,43 @@<br>
     }<br>
     return 0;<br>
   }<br>
+<br>
+  if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&<br>
+      insn->rexPrefix & 0x01) {<br>
+    /*<br>
+     * NOOP shouldn't decode as NOOP if REX.b is set. Instead<br>
+     * it should decode as XCHG %r8, %eax.<br>
+     */<br>
+<br>
+    const struct InstructionSpecifier *spec;<br>
+    uint16_t instructionIDWithNewOpcode;<br>
+    const struct InstructionSpecifier *specWithNewOpcode;<br>
+<br>
+    spec = specifierForUID(instructionID);<br>
+<br>
+    // Borrow opcode from one of the other XCHGar opcodes<br>
+    insn->opcode = 0x91;<br>
+<br>
+    if (getIDWithAttrMask(&instructionIDWithNewOpcode,<br>
+                          insn,<br>
+                          attrMask)) {<br>
+      insn->opcode = 0x90;<br>
+<br>
+      insn->instructionID = instructionID;<br>
+      insn->spec = spec;<br>
+      return 0;<br>
+    }<br>
+<br>
+    specWithNewOpcode = specifierForUID(instructionIDWithNewOpcode);<br>
+<br>
+    // Change back<br>
+    insn->opcode = 0x90;<br>
+<br>
+    insn->instructionID = instructionIDWithNewOpcode;<br>
+    insn->spec = specWithNewOpcode;<br>
+<br>
+    return 0;<br>
+  }<br>
<br>
   insn->instructionID = instructionID;<br>
   insn->spec = specifierForUID(insn->instructionID);<br>
<br>
Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt<br>
URL:<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simp%0Ale-tests.txt?rev=140971&r1=140970&r2=140971&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simp<br>

le-tests.txt?rev=140971&r1=140970&r2=140971&view=diff</a><br>
============================================================================<br>
==<br>
--- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)<br>
+++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Sun Oct  2 11:56:09<br>
2011<br>
@@ -308,3 +308,6 @@<br>
<br>
 # CHECK: invvpid (%rax), %rax<br>
 0x66 0x0f 0x38 0x81 0x00<br>
+<br>
+# CHECK: xchgl %r8d, %eax<br>
+0x41 0x90<br>
<br>
<br>
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<br>
<br>
<br>
<br>
</blockquote></div><br><br clear="all"><br>-- <br>~Craig<br>