<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Hi Jakob,<div>I'm seeing a failure for one of the clang llvm-gcc tests. Bisect brought me to this revision, which seems very relevant.</div><div><span class="Apple-style-span" style="font-family: Times; "><pre style="font-family: 'Courier New', courier, monotype; "><span class="stdout" style="font-family: 'Courier New', courier, monotype; color: black; ">gcc.target/i386/pr30848.c (test for excess errors)</span></pre></span></div><div><div>mcrosier$ /Users/mcrosier/llvm-clean/install/bin/clang /Users/mcrosier/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c -ansi -pedantic-errors -fno-show-column -S -o pr30848.s</div><div>fatal error: error in backend: Inline asm fixed outputs must be last on the x87 stack</div><div><br></div></div><div>This one is also failing:</div><div><span class="Apple-style-span" style="font-family: Times; "><pre style="font-family: 'Courier New', courier, monotype; "><span class="stdout" style="font-family: 'Courier New', courier, monotype; color: black; ">gcc.c-torture/execute/conversion.c execution, -O0</span></pre></span></div><div>Looks to be a miscompile, but I didn't have time to dig to deep; I need to get moving an unrelated P1 radar ASAP.</div><div><br></div><div> Chad</div><div><br></div><div><br><div><div>On Jun 28, 2011, at 11:32 AM, Jakob Stoklund Olesen wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: stoklund<br>Date: Tue Jun 28 13:32:28 2011<br>New Revision: 134018<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=134018&view=rev">http://llvm.org/viewvc/llvm-project?rev=134018&view=rev</a><br>Log:<br>Clean up the handling of the x87 fp stack to make it more robust.<br><br>Drop the FpMov instructions, use plain COPY instead.<br><br>Drop the FpSET/GET instruction for accessing fixed stack positions.<br>Instead use normal COPY to/from ST registers around inline assembly, and<br>provide a single new FpPOP_RETVAL instruction that can access the return<br>value(s) from a call. This is still necessary since you cannot tell from<br>the CALL instruction alone if it returns anything on the FP stack. Teach<br>fast isel to use this.<br><br>This provides a much more robust way of handling fixed stack registers -<br>we can tolerate arbitrary FP stack instructions inserted around calls<br>and inline assembly. Live range splitting could sometimes break x87 code<br>by inserting spill code in unfortunate places.<br><br>As a bonus we handle floating point inline assembly correctly now.<br><br>Modified:<br> llvm/trunk/lib/Target/X86/X86FastISel.cpp<br> llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp<br> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br> llvm/trunk/lib/Target/X86/X86InstrFPStack.td<br> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp<br> llvm/trunk/lib/Target/X86/X86RegisterInfo.td<br> llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll<br><br>Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jun 28 13:32:28 2011<br>@@ -1848,16 +1848,18 @@<br> // stack, but where we prefer to use the value in xmm registers, copy it<br> // out as F80 and use a truncate to move it from fp stack reg to xmm reg.<br> if ((RVLocs[i].getLocReg() == X86::ST0 ||<br>- RVLocs[i].getLocReg() == X86::ST1) &&<br>- isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {<br>- CopyVT = MVT::f80;<br>+ RVLocs[i].getLocReg() == X86::ST1)) {<br>+ if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))<br>+ CopyVT = MVT::f80;<br> CopyReg = createResultReg(X86::RFP80RegisterClass);<br>+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),<br>+ CopyReg);<br>+ } else {<br>+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),<br>+ CopyReg).addReg(RVLocs[i].getLocReg());<br>+ UsedRegs.push_back(RVLocs[i].getLocReg());<br> }<br><br>- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),<br>- CopyReg).addReg(RVLocs[i].getLocReg());<br>- UsedRegs.push_back(RVLocs[i].getLocReg());<br>-<br> if (CopyVT != RVLocs[i].getValVT()) {<br> // Round the F80 the right size, which also moves to the appropriate xmm<br> // register. This is accomplished by storing the F80 value in memory and<br><br>Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Jun 28 13:32:28 2011<br>@@ -37,6 +37,7 @@<br> #include "llvm/CodeGen/MachineInstrBuilder.h"<br> #include "llvm/CodeGen/MachineRegisterInfo.h"<br> #include "llvm/CodeGen/Passes.h"<br>+#include "llvm/InlineAsm.h"<br> #include "llvm/Support/Debug.h"<br> #include "llvm/Support/ErrorHandling.h"<br> #include "llvm/Support/raw_ostream.h"<br>@@ -134,11 +135,36 @@<br> unsigned Stack[8]; // FP<n> Registers in each stack slot...<br> unsigned StackTop; // The current top of the FP stack.<br><br>+ enum {<br>+ NumFPRegs = 16 // Including scratch pseudo-registers.<br>+ };<br>+<br> // For each live FP<n> register, point to its Stack[] entry.<br> // The first entries correspond to FP0-FP6, the rest are scratch registers<br> // used when we need slightly different live registers than what the<br> // register allocator thinks.<br>- unsigned RegMap[16];<br>+ unsigned RegMap[NumFPRegs];<br>+<br>+ // Pending fixed registers - Inline assembly needs FP registers to appear<br>+ // in fixed stack slot positions. This is handled by copying FP registers<br>+ // to ST registers before the instruction, and copying back after the<br>+ // instruction.<br>+ //<br>+ // This is modeled with pending ST registers. NumPendingSTs is the number<br>+ // of ST registers (ST0-STn) we are tracking. PendingST[n] points to an FP<br>+ // register that holds the ST value. The ST registers are not moved into<br>+ // place until immediately before the instruction that needs them.<br>+ //<br>+ // It can happen that we need an ST register to be live when no FP register<br>+ // holds the value:<br>+ //<br>+ // %ST0 = COPY %FP4<kill><br>+ //<br>+ // When that happens, we allocate a scratch FP register to hold the ST<br>+ // value. That means every register in PendingST must be live.<br>+<br>+ unsigned NumPendingSTs;<br>+ unsigned char PendingST[8];<br><br> // Set up our stack model to match the incoming registers to MBB.<br> void setupBlockStack();<br>@@ -152,13 +178,15 @@<br> dbgs() << " FP" << Stack[i];<br> assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");<br> }<br>+ for (unsigned i = 0; i != NumPendingSTs; ++i)<br>+ dbgs() << ", ST" << i << " in FP" << unsigned(PendingST[i]);<br> dbgs() << "\n";<br> }<br><br> /// getSlot - Return the stack slot number a particular register number is<br> /// in.<br> unsigned getSlot(unsigned RegNo) const {<br>- assert(RegNo < array_lengthof(RegMap) && "Regno out of range!");<br>+ assert(RegNo < NumFPRegs && "Regno out of range!");<br> return RegMap[RegNo];<br> }<br><br>@@ -170,12 +198,17 @@<br><br> /// getScratchReg - Return an FP register that is not currently in use.<br> unsigned getScratchReg() {<br>- for (int i = array_lengthof(RegMap) - 1; i >= 8; --i)<br>+ for (int i = NumFPRegs - 1; i >= 8; --i)<br> if (!isLive(i))<br> return i;<br> llvm_unreachable("Ran out of scratch FP registers");<br> }<br><br>+ /// isScratchReg - Returns trus if RegNo is a scratch FP register.<br>+ bool isScratchReg(unsigned RegNo) {<br>+ return RegNo > 8 && RegNo < NumFPRegs;<br>+ }<br>+<br> /// getStackEntry - Return the X86::FP<n> register in register ST(i).<br> unsigned getStackEntry(unsigned STi) const {<br> if (STi >= StackTop)<br>@@ -191,7 +224,7 @@<br><br> // pushReg - Push the specified FP<n> register onto the stack.<br> void pushReg(unsigned Reg) {<br>- assert(Reg < array_lengthof(RegMap) && "Register number out of range!");<br>+ assert(Reg < NumFPRegs && "Register number out of range!");<br> if (StackTop >= 8)<br> report_fatal_error("Stack overflow!");<br> Stack[StackTop] = Reg;<br>@@ -261,7 +294,14 @@<br> void handleCondMovFP(MachineBasicBlock::iterator &I);<br> void handleSpecialFP(MachineBasicBlock::iterator &I);<br><br>- bool translateCopy(MachineInstr*);<br>+ // Check if a COPY instruction is using FP registers.<br>+ bool isFPCopy(MachineInstr *MI) {<br>+ unsigned DstReg = MI->getOperand(0).getReg();<br>+ unsigned SrcReg = MI->getOperand(1).getReg();<br>+<br>+ return X86::RFP80RegClass.contains(DstReg) ||<br>+ X86::RFP80RegClass.contains(SrcReg);<br>+ }<br> };<br> char FPS::ID = 0;<br> }<br>@@ -351,6 +391,7 @@<br> bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {<br> bool Changed = false;<br> MBB = &BB;<br>+ NumPendingSTs = 0;<br><br> setupBlockStack();<br><br>@@ -362,7 +403,7 @@<br> if (MI->isInlineAsm())<br> FPInstClass = X86II::SpecialFP;<br><br>- if (MI->isCopy() && translateCopy(MI))<br>+ if (MI->isCopy() && isFPCopy(MI))<br> FPInstClass = X86II::SpecialFP;<br><br> if (FPInstClass == X86II::NotFP)<br>@@ -891,7 +932,8 @@<br> continue;<br> // (Reg st0) (OldReg st0) = (Reg OldReg st0)<br> moveToTop(Reg, I);<br>- moveToTop(OldReg, I);<br>+ if (FixCount > 0)<br>+ moveToTop(OldReg, I);<br> }<br> DEBUG(dumpStack());<br> }<br>@@ -1249,142 +1291,309 @@<br> MachineInstr *MI = I;<br> switch (MI->getOpcode()) {<br> default: llvm_unreachable("Unknown SpecialFP instruction!");<br>- case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!<br>- case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!<br>- case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!<br>- assert(StackTop == 0 && "Stack should be empty after a call!");<br>- pushReg(getFPReg(MI->getOperand(0)));<br>- break;<br>- case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!<br>- case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!<br>- case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!<br>- // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.<br>- // The pattern we expect is:<br>- // CALL<br>- // FP1 = FpGET_ST0<br>- // FP4 = FpGET_ST1<br>- //<br>- // At this point, we've pushed FP1 on the top of stack, so it should be<br>- // present if it isn't dead. If it was dead, we already emitted a pop to<br>- // remove it from the stack and StackTop = 0.<br>- <br>- // Push FP4 as top of stack next.<br>- pushReg(getFPReg(MI->getOperand(0)));<br>+ case TargetOpcode::COPY: {<br>+ // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.<br>+ const MachineOperand &MO1 = MI->getOperand(1);<br>+ const MachineOperand &MO0 = MI->getOperand(0);<br>+ unsigned DstST = MO0.getReg() - X86::ST0;<br>+ unsigned SrcST = MO1.getReg() - X86::ST0;<br>+ bool KillsSrc = MI->killsRegister(MO1.getReg());<br>+<br>+ // ST = COPY FP. Set up a pending ST register.<br>+ if (DstST < 8) {<br>+ unsigned SrcFP = getFPReg(MO1);<br>+ assert(isLive(SrcFP) && "Cannot copy dead register");<br>+ assert(!MO0.isDead() && "Cannot copy to dead ST register");<br>+<br>+ // Unallocated STs are marked as the nonexistent FP255.<br>+ while (NumPendingSTs <= DstST)<br>+ PendingST[NumPendingSTs++] = NumFPRegs;<br>+<br>+ // STi could still be live from a previous inline asm.<br>+ if (isScratchReg(PendingST[DstST])) {<br>+ DEBUG(dbgs() << "Clobbering old ST in FP" << unsigned(PendingST[DstST])<br>+ << '\n');<br>+ freeStackSlotBefore(MI, PendingST[DstST]);<br>+ }<br><br>- // If StackTop was 0 before we pushed our operand, then ST(0) must have been<br>- // dead. In this case, the ST(1) value is the only thing that is live, so<br>- // it should be on the TOS (after the pop that was emitted) and is. Just<br>- // continue in this case.<br>- if (StackTop == 1)<br>+ // When the source is killed, allocate a scratch FP register.<br>+ if (KillsSrc) {<br>+ unsigned Slot = getSlot(SrcFP);<br>+ unsigned SR = getScratchReg();<br>+ PendingST[DstST] = SR;<br>+ Stack[Slot] = SR;<br>+ RegMap[SR] = Slot;<br>+ } else<br>+ PendingST[DstST] = SrcFP;<br> break;<br>- <br>- // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top<br>- // elements so that our accounting is correct.<br>- unsigned RegOnTop = getStackEntry(0);<br>- unsigned RegNo = getStackEntry(1);<br>- <br>- // Swap the slots the regs are in.<br>- std::swap(RegMap[RegNo], RegMap[RegOnTop]);<br>- <br>- // Swap stack slot contents.<br>- if (RegMap[RegOnTop] >= StackTop)<br>- report_fatal_error("Access past stack top!");<br>- std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);<br>- break;<br>- }<br>- case X86::FpSET_ST0_32:<br>- case X86::FpSET_ST0_64:<br>- case X86::FpSET_ST0_80: {<br>- // FpSET_ST0_80 is generated by copyRegToReg for setting up inline asm<br>- // arguments that use an st constraint. We expect a sequence of<br>- // instructions: Fp_SET_ST0 Fp_SET_ST1? INLINEASM<br>- unsigned Op0 = getFPReg(MI->getOperand(0));<br>-<br>- if (!MI->killsRegister(X86::FP0 + Op0)) {<br>- // Duplicate Op0 into a temporary on the stack top.<br>- duplicateToTop(Op0, getScratchReg(), I);<br>- } else {<br>- // Op0 is killed, so just swap it into position.<br>- moveToTop(Op0, I);<br> }<br>- --StackTop; // "Forget" we have something on the top of stack!<br>- break;<br>- }<br>- case X86::FpSET_ST1_32:<br>- case X86::FpSET_ST1_64:<br>- case X86::FpSET_ST1_80: {<br>- // Set up st(1) for inline asm. We are assuming that st(0) has already been<br>- // set up by FpSET_ST0, and our StackTop is off by one because of it.<br>- unsigned Op0 = getFPReg(MI->getOperand(0));<br>- // Restore the actual StackTop from before Fp_SET_ST0.<br>- // Note we can't handle Fp_SET_ST1 without a preceding Fp_SET_ST0, and we<br>- // are not enforcing the constraint.<br>- ++StackTop;<br>- unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0).<br>- if (!MI->killsRegister(X86::FP0 + Op0)) {<br>- duplicateToTop(Op0, getScratchReg(), I);<br>- moveToTop(RegOnTop, I);<br>- } else if (getSTReg(Op0) != X86::ST1) {<br>- // We have the wrong value at st(1). Shuffle! Untested!<br>- moveToTop(getStackEntry(1), I);<br>- moveToTop(Op0, I);<br>- moveToTop(RegOnTop, I);<br>+<br>+ // FP = COPY ST. Extract fixed stack value.<br>+ // Any instruction defining ST registers must have assigned them to a<br>+ // scratch register.<br>+ if (SrcST < 8) {<br>+ unsigned DstFP = getFPReg(MO0);<br>+ assert(!isLive(DstFP) && "Cannot copy ST to live FP register");<br>+ assert(NumPendingSTs > SrcST && "Cannot copy from dead ST register");<br>+ unsigned SrcFP = PendingST[SrcST];<br>+ assert(isScratchReg(SrcFP) && "Expected ST in a scratch register");<br>+ assert(isLive(SrcFP) && "Scratch holding ST is dead");<br>+<br>+ // DstFP steals the stack slot from SrcFP.<br>+ unsigned Slot = getSlot(SrcFP);<br>+ Stack[Slot] = DstFP;<br>+ RegMap[DstFP] = Slot;<br>+<br>+ // Always treat the ST as killed.<br>+ PendingST[SrcST] = NumFPRegs;<br>+ while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs)<br>+ --NumPendingSTs;<br>+ break;<br> }<br>- assert(StackTop >= 2 && "Too few live registers");<br>- StackTop -= 2; // "Forget" both st(0) and st(1).<br>- break;<br>- }<br>- case X86::MOV_Fp3232:<br>- case X86::MOV_Fp3264:<br>- case X86::MOV_Fp6432:<br>- case X86::MOV_Fp6464: <br>- case X86::MOV_Fp3280:<br>- case X86::MOV_Fp6480:<br>- case X86::MOV_Fp8032:<br>- case X86::MOV_Fp8064: <br>- case X86::MOV_Fp8080: {<br>- const MachineOperand &MO1 = MI->getOperand(1);<br>- unsigned SrcReg = getFPReg(MO1);<br><br>- const MachineOperand &MO0 = MI->getOperand(0);<br>- unsigned DestReg = getFPReg(MO0);<br>- if (MI->killsRegister(X86::FP0+SrcReg)) {<br>+ // FP <- FP copy.<br>+ unsigned DstFP = getFPReg(MO0);<br>+ unsigned SrcFP = getFPReg(MO1);<br>+ assert(isLive(SrcFP) && "Cannot copy dead register");<br>+ if (KillsSrc) {<br> // If the input operand is killed, we can just change the owner of the<br> // incoming stack slot into the result.<br>- unsigned Slot = getSlot(SrcReg);<br>- assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");<br>- Stack[Slot] = DestReg;<br>- RegMap[DestReg] = Slot;<br>-<br>+ unsigned Slot = getSlot(SrcFP);<br>+ Stack[Slot] = DstFP;<br>+ RegMap[DstFP] = Slot;<br> } else {<br>- // For FMOV we just duplicate the specified value to a new stack slot.<br>+ // For COPY we just duplicate the specified value to a new stack slot.<br> // This could be made better, but would require substantial changes.<br>- duplicateToTop(SrcReg, DestReg, I);<br>+ duplicateToTop(SrcFP, DstFP, I);<br> }<br>+ break;<br>+ }<br>+<br>+ case X86::FpPOP_RETVAL: {<br>+ // The FpPOP_RETVAL instruction is used after calls that return a value on<br>+ // the floating point stack. We cannot model this with ST defs since CALL<br>+ // instructions have fixed clobber lists. This instruction is interpreted<br>+ // to mean that there is one more live register on the stack than we<br>+ // thought.<br>+ //<br>+ // This means that StackTop does not match the hardware stack between a<br>+ // call and the FpPOP_RETVAL instructions. We do tolerate FP instructions<br>+ // between CALL and FpPOP_RETVAL as long as they don't overflow the<br>+ // hardware stack.<br>+ unsigned DstFP = getFPReg(MI->getOperand(0));<br>+<br>+ // Move existing stack elements up to reflect reality.<br>+ assert(StackTop < 8 && "Stack overflowed before FpPOP_RETVAL");<br>+ if (StackTop) {<br>+ std::copy_backward(Stack, Stack + StackTop, Stack + StackTop + 1);<br>+ for (unsigned i = 0; i != NumFPRegs; ++i)<br>+ ++RegMap[i];<br> }<br>+ ++StackTop;<br>+<br>+ // DstFP is the new bottom of the stack.<br>+ Stack[0] = DstFP;<br>+ RegMap[DstFP] = 0;<br>+<br>+ // DstFP will be killed by processBasicBlock if this was a dead def.<br> break;<br>+ }<br>+<br> case TargetOpcode::INLINEASM: {<br> // The inline asm MachineInstr currently only *uses* FP registers for the<br> // 'f' constraint. These should be turned into the current ST(x) register<br>- // in the machine instr. Also, any kills should be explicitly popped after<br>- // the inline asm.<br>- unsigned Kills = 0;<br>+ // in the machine instr.<br>+ //<br>+ // There are special rules for x87 inline assembly. The compiler must know<br>+ // exactly how many registers are popped and pushed implicitly by the asm.<br>+ // Otherwise it is not possible to restore the stack state after the inline<br>+ // asm.<br>+ //<br>+ // There are 3 kinds of input operands:<br>+ //<br>+ // 1. Popped inputs. These must appear at the stack top in ST0-STn. A<br>+ // popped input operand must be in a fixed stack slot, and it is either<br>+ // tied to an output operand, or in the clobber list. The MI has ST use<br>+ // and def operands for these inputs.<br>+ //<br>+ // 2. Fixed inputs. These inputs appear in fixed stack slots, but are<br>+ // preserved by the inline asm. The fixed stack slots must be STn-STm<br>+ // following the popped inputs. A fixed input operand cannot be tied to<br>+ // an output or appear in the clobber list. The MI has ST use operands<br>+ // and no defs for these inputs.<br>+ //<br>+ // 3. Preserved inputs. These inputs use the "f" constraint which is<br>+ // represented as an FP register. The inline asm won't change these<br>+ // stack slots.<br>+ //<br>+ // Outputs must be in ST registers, FP outputs are not allowed. Clobbered<br>+ // registers do not count as output operands. The inline asm changes the<br>+ // stack as if it popped all the popped inputs and then pushed all the<br>+ // output operands.<br>+<br>+ // Scan the assembly for ST registers used, defined and clobbered. We can<br>+ // only tell clobbers from defs by looking at the asm descriptor.<br>+ unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;<br>+ unsigned NumOps = 0;<br>+ for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();<br>+ i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {<br>+ unsigned Flags = MI->getOperand(i).getImm();<br>+ NumOps = InlineAsm::getNumOperandRegisters(Flags);<br>+ if (NumOps != 1)<br>+ continue;<br>+ const MachineOperand &MO = MI->getOperand(i + 1);<br>+ if (!MO.isReg())<br>+ continue;<br>+ unsigned STReg = MO.getReg() - X86::ST0;<br>+ if (STReg >= 8)<br>+ continue;<br>+<br>+ switch (InlineAsm::getKind(Flags)) {<br>+ case InlineAsm::Kind_RegUse:<br>+ STUses |= (1u << STReg);<br>+ break;<br>+ case InlineAsm::Kind_RegDef:<br>+ case InlineAsm::Kind_RegDefEarlyClobber:<br>+ STDefs |= (1u << STReg);<br>+ if (MO.isDead())<br>+ STDeadDefs |= (1u << STReg);<br>+ break;<br>+ case InlineAsm::Kind_Clobber:<br>+ STClobbers |= (1u << STReg);<br>+ break;<br>+ default:<br>+ break;<br>+ }<br>+ }<br>+<br>+ if (STUses && !isMask_32(STUses))<br>+ report_fatal_error("Inline asm fixed inputs"<br>+ " must be last on the x87 stack");<br>+ unsigned NumSTUses = CountTrailingOnes_32(STUses);<br>+<br>+ // Defs must be contiguous from the stack top. ST0-STn.<br>+ if (STDefs && !isMask_32(STDefs))<br>+ report_fatal_error("Inline asm fixed outputs"<br>+ " must be last on the x87 stack");<br>+ unsigned NumSTDefs = CountTrailingOnes_32(STDefs);<br>+<br>+ // So must the clobbered stack slots. ST0-STm, m >= n.<br>+ if (STClobbers && !isMask_32(STDefs | STClobbers))<br>+ report_fatal_error("Inline asm clobbers must be last on the x87 stack");<br>+<br>+ // Popped inputs are the ones that are also clobbered or defined.<br>+ unsigned STPopped = STUses & (STDefs | STClobbers);<br>+ if (STPopped && !isMask_32(STPopped))<br>+ report_fatal_error("Inline asm popped inputs"<br>+ " must be last on the x87 stack");<br>+ unsigned NumSTPopped = CountTrailingOnes_32(STPopped);<br>+<br>+ DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "<br>+ << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");<br>+<br>+ // Scan the instruction for FP uses corresponding to "f" constraints.<br>+ // Collect FP registers to kill afer the instruction.<br>+ // Always kill all the scratch regs.<br>+ unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;<br>+ unsigned FPUsed = 0;<br> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br> MachineOperand &Op = MI->getOperand(i);<br> if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)<br> continue;<br>- assert(Op.isUse() && "Only handle inline asm uses right now");<br>- <br>+ if (!Op.isUse())<br>+ report_fatal_error("Illegal \"f\" output constraint in inline asm");<br> unsigned FPReg = getFPReg(Op);<br>- Op.setReg(getSTReg(FPReg));<br>- <br>+ FPUsed |= 1U << FPReg;<br>+<br> // If we kill this operand, make sure to pop it from the stack after the<br> // asm. We just remember it for now, and pop them all off at the end in<br> // a batch.<br> if (Op.isKill())<br>- Kills |= 1U << FPReg;<br>+ FPKills |= 1U << FPReg;<br> }<br><br>+ // The popped inputs will be killed by the instruction, so duplicate them<br>+ // if the FP register needs to be live after the instruction, or if it is<br>+ // used in the instruction itself. We effectively treat the popped inputs<br>+ // as early clobbers.<br>+ for (unsigned i = 0; i < NumSTPopped; ++i) {<br>+ if ((FPKills & ~FPUsed) & (1u << PendingST[i]))<br>+ continue;<br>+ unsigned SR = getScratchReg();<br>+ duplicateToTop(PendingST[i], SR, I);<br>+ DEBUG(dbgs() << "Duplicating ST" << i << " in FP"<br>+ << unsigned(PendingST[i]) << " to avoid clobbering it.\n");<br>+ PendingST[i] = SR;<br>+ }<br>+<br>+ // Make sure we have a unique live register for every fixed use. Some of<br>+ // them could be undef uses, and we need to emit LD_F0 instructions.<br>+ for (unsigned i = 0; i < NumSTUses; ++i) {<br>+ if (i < NumPendingSTs && PendingST[i] < NumFPRegs) {<br>+ // Check for shared assignments.<br>+ for (unsigned j = 0; j < i; ++j) {<br>+ if (PendingST[j] != PendingST[i])<br>+ continue;<br>+ // STi and STj are inn the same register, create a copy.<br>+ unsigned SR = getScratchReg();<br>+ duplicateToTop(PendingST[i], SR, I);<br>+ DEBUG(dbgs() << "Duplicating ST" << i << " in FP"<br>+ << unsigned(PendingST[i])<br>+ << " to avoid collision with ST" << j << '\n');<br>+ PendingST[i] = SR;<br>+ }<br>+ continue;<br>+ }<br>+ unsigned SR = getScratchReg();<br>+ DEBUG(dbgs() << "Emitting LD_F0 for ST" << i << " in FP" << SR << '\n');<br>+ BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0));<br>+ pushReg(SR);<br>+ PendingST[i] = SR;<br>+ if (NumPendingSTs == i)<br>+ ++NumPendingSTs;<br>+ }<br>+ assert(NumPendingSTs >= NumSTUses && "Fixed registers should be assigned");<br>+<br>+ // Now we can rearrange the live registers to match what was requested.<br>+ shuffleStackTop(PendingST, NumPendingSTs, I);<br>+ DEBUG({dbgs() << "Before asm: "; dumpStack();});<br>+<br>+ // With the stack layout fixed, rewrite the FP registers.<br>+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br>+ MachineOperand &Op = MI->getOperand(i);<br>+ if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)<br>+ continue;<br>+ unsigned FPReg = getFPReg(Op);<br>+ Op.setReg(getSTReg(FPReg));<br>+ }<br>+<br>+ // Simulate the inline asm popping its inputs and pushing its outputs.<br>+ StackTop -= NumSTPopped;<br>+<br>+ // Hold the fixed output registers in scratch FP registers. They will be<br>+ // transferred to real FP registers by copies.<br>+ NumPendingSTs = 0;<br>+ for (unsigned i = 0; i < NumSTDefs; ++i) {<br>+ unsigned SR = getScratchReg();<br>+ pushReg(SR);<br>+ FPKills &= ~(1u << SR);<br>+ }<br>+ for (unsigned i = 0; i < NumSTDefs; ++i)<br>+ PendingST[NumPendingSTs++] = getStackEntry(i);<br>+ DEBUG({dbgs() << "After asm: "; dumpStack();});<br>+<br>+ // If any of the ST defs were dead, pop them immediately. Our caller only<br>+ // handles dead FP defs.<br>+ MachineBasicBlock::iterator InsertPt = MI;<br>+ for (unsigned i = 0; STDefs & (1u << i); ++i) {<br>+ if (!(STDeadDefs & (1u << i)))<br>+ continue;<br>+ freeStackSlotAfter(InsertPt, PendingST[i]);<br>+ PendingST[i] = NumFPRegs;<br>+ }<br>+ while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs)<br>+ --NumPendingSTs;<br>+<br> // If this asm kills any FP registers (is the last use of them) we must<br> // explicitly emit pop instructions for them. Do this now after the asm has<br> // executed so that the ST(x) numbers are not off (which would happen if we<br>@@ -1392,16 +1601,16 @@<br> //<br> // Note: this might be a non-optimal pop sequence. We might be able to do<br> // better by trying to pop in stack order or something.<br>- MachineBasicBlock::iterator InsertPt = MI;<br>- while (Kills) {<br>- unsigned FPReg = CountTrailingZeros_32(Kills);<br>- freeStackSlotAfter(InsertPt, FPReg);<br>- Kills &= ~(1U << FPReg);<br>+ while (FPKills) {<br>+ unsigned FPReg = CountTrailingZeros_32(FPKills);<br>+ if (isLive(FPReg))<br>+ freeStackSlotAfter(InsertPt, FPReg);<br>+ FPKills &= ~(1U << FPReg);<br> }<br> // Don't delete the inline asm!<br> return;<br> }<br>- <br>+<br> case X86::RET:<br> case X86::RETI:<br> // If RET has an FP register use operand, pass the first one in ST(0) and<br>@@ -1499,33 +1708,3 @@<br> } else<br> --I;<br> }<br>-<br>-// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands.<br>-bool FPS::translateCopy(MachineInstr *MI) {<br>- unsigned DstReg = MI->getOperand(0).getReg();<br>- unsigned SrcReg = MI->getOperand(1).getReg();<br>-<br>- if (DstReg == X86::ST0) {<br>- MI->setDesc(TII->get(X86::FpSET_ST0_80));<br>- MI->RemoveOperand(0);<br>- return true;<br>- }<br>- if (DstReg == X86::ST1) {<br>- MI->setDesc(TII->get(X86::FpSET_ST1_80));<br>- MI->RemoveOperand(0);<br>- return true;<br>- }<br>- if (SrcReg == X86::ST0) {<br>- MI->setDesc(TII->get(X86::FpGET_ST0_80));<br>- return true;<br>- }<br>- if (SrcReg == X86::ST1) {<br>- MI->setDesc(TII->get(X86::FpGET_ST1_80));<br>- return true;<br>- }<br>- if (X86::RFP80RegClass.contains(DstReg, SrcReg)) {<br>- MI->setDesc(TII->get(X86::MOV_Fp8080));<br>- return true;<br>- }<br>- return false;<br>-}<br><br>Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 28 13:32:28 2011<br>@@ -1511,20 +1511,15 @@<br> // If this is a call to a function that returns an fp value on the floating<br> // point stack, we must guarantee the the value is popped from the stack, so<br> // a CopyFromReg is not good enough - the copy instruction may be eliminated<br>- // if the return value is not used. We use the FpGET_ST0 instructions<br>+ // if the return value is not used. We use the FpPOP_RETVAL instruction<br> // instead.<br> if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {<br> // If we prefer to use the value in xmm registers, copy it out as f80 and<br> // use a truncate to move it from fp stack reg to xmm reg.<br> if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;<br>- bool isST0 = VA.getLocReg() == X86::ST0;<br>- unsigned Opc = 0;<br>- if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;<br>- if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;<br>- if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;<br> SDValue Ops[] = { Chain, InFlag };<br>- Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,<br>- Ops, 2), 1);<br>+ Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,<br>+ MVT::Other, MVT::Glue, Ops, 2), 1);<br> Val = Chain.getValue(0);<br><br> // Round the f80 to the right size, which also moves it to the appropriate<br><br>Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)<br>+++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Jun 28 13:32:28 2011<br>@@ -112,31 +112,8 @@<br> // a pattern) and the FPI instruction should have emission info (e.g. opcode<br> // encoding and asm printing info).<br><br>-// Pseudo Instructions for FP stack return values.<br>-def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)<br>-def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)<br>-def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)<br>-<br>-// FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when<br>-// there are two values live out on the stack from a call or inlineasm. This<br>-// magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and<br>-// then FpGET_ST0*. In addition, it is invalid for any FP-using operations to<br>-// occur between them.<br>-def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)<br>-def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)<br>-def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)<br>-<br>-let Defs = [ST0] in {<br>-def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR<br>-def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR<br>-def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR<br>-}<br>-<br>-let Defs = [ST1] in {<br>-def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR<br>-def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR<br>-def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR<br>-}<br>+// Pseudo Instruction for FP stack return values.<br>+def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>;<br><br> // FpIf32, FpIf64 - Floating Point Pseudo Instruction template.<br> // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.<br>@@ -147,19 +124,6 @@<br> class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :<br> FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;<br><br>-// Register copies. Just copies, the shortening ones do not truncate.<br>-let neverHasSideEffects = 1 in {<br>- def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; <br>- def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; <br>- def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; <br>- def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>; <br>- def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>; <br>- def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>; <br>- def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>; <br>- def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>; <br>- def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>; <br>-}<br>-<br> // Factoring for arithmetic.<br> multiclass FPBinary_rr<SDNode OpNode> {<br> // Register op register -> register<br><br>Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)<br>+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 28 13:32:28 2011<br>@@ -500,18 +500,6 @@<br> Reserved.set(X86::BPL);<br> }<br><br>- // Mark the x87 stack registers as reserved, since they don't behave normally<br>- // with respect to liveness. We don't fully model the effects of x87 stack<br>- // pushes and pops after stackification.<br>- Reserved.set(X86::ST0);<br>- Reserved.set(X86::ST1);<br>- Reserved.set(X86::ST2);<br>- Reserved.set(X86::ST3);<br>- Reserved.set(X86::ST4);<br>- Reserved.set(X86::ST5);<br>- Reserved.set(X86::ST6);<br>- Reserved.set(X86::ST7);<br>-<br> // Mark the segment registers as reserved.<br> Reserved.set(X86::CS);<br> Reserved.set(X86::SS);<br><br>Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)<br>+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Jun 28 13:32:28 2011<br>@@ -206,15 +206,22 @@<br> def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>;<br> }<br><br>- // Floating point stack registers<br>- def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;<br>- def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;<br>- def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;<br>- def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;<br>- def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;<br>- def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;<br>- def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;<br>- def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;<br>+ class STRegister<string Name, list<Register> A> : Register<Name> {<br>+ let Aliases = A;<br>+ }<br>+<br>+ // Floating point stack registers. These don't map one-to-one to the FP<br>+ // pseudo registers, but we still mark them as aliasing FP registers. That<br>+ // way both kinds can be live without exceeding the stack depth. ST registers<br>+ // are only live around inline assembly.<br>+ def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>;<br>+ def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>;<br>+ def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>;<br>+ def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>;<br>+ def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>;<br>+ def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>;<br>+ def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>;<br>+ def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>;<br><br> // Status flags register<br> def EFLAGS : Register<"flags">;<br><br>Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=134018&r1=134017&r2=134018&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=134018&r1=134017&r2=134018&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll (original)<br>+++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Tue Jun 28 13:32:28 2011<br>@@ -106,6 +106,25 @@<br> <span class="Apple-tab-span" style="white-space:pre"> </span>ret void<br> }<br><br>+; Passing a non-killed value through asm in {st}.<br>+; Make sure it is not duped before.<br>+; Second asm kills st(0), so we shouldn't pop anything<br>+; CHECK: testPR4185b<br>+; CHECK-NOT: fld %st(0)<br>+; CHECK: fistl<br>+; CHECK-NOT: fstp<br>+; CHECK: fistpl<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+; A valid alternative would be to remat the constant pool load before each<br>+; inline asm.<br>+define void @testPR4185b() {<br>+return:<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>call void asm sideeffect "fistl $0", "{st}"(double 1.000000e+06)<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06)<br>+<span class="Apple-tab-span" style="white-space:pre"> </span>ret void<br>+}<br>+<br> ; PR4459<br> ; The return value from ceil must be duped before being consumed by asm.<br> ; CHECK: testPR4459<br>@@ -160,3 +179,153 @@<br> <span class="Apple-tab-span" style="white-space:pre"> </span>tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5)<br> <span class="Apple-tab-span" style="white-space:pre"> </span>ret void<br> }<br>+<br>+; An input argument in a fixed position is implicitly popped by the asm only if<br>+; the input argument is tied to an output register, or it is in the clobber list.<br>+; The clobber list case is tested above.<br>+;<br>+; This doesn't implicitly pop the stack:<br>+;<br>+; void fist1(long double x, int *p) {<br>+; asm volatile ("fistl %1" : : "t"(x), "m"(*p));<br>+; }<br>+;<br>+; CHECK: fist1<br>+; CHECK: fldt<br>+; CHECK: fistl (%e<br>+; CHECK: fstp<br>+; CHECK: ret<br>+define void @fist1(x86_fp80 %x, i32* %p) nounwind ssp {<br>+entry:<br>+ tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind<br>+ ret void<br>+}<br>+<br>+; Here, the input operand is tied to an output which means that is is<br>+; implicitly popped (and then the output is implicitly pushed).<br>+;<br>+; long double fist2(long double x, int *p) {<br>+; long double y;<br>+; asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory");<br>+; return y;<br>+; }<br>+;<br>+; CHECK: fist2<br>+; CHECK: fldt<br>+; CHECK: fistl (%e<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+define x86_fp80 @fist2(x86_fp80 %x, i32* %p) nounwind ssp {<br>+entry:<br>+ %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind<br>+ ret x86_fp80 %0<br>+}<br>+<br>+; An 'f' constraint is never implicitly popped:<br>+;<br>+; void fucomp1(long double x, long double y) {<br>+; asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st");<br>+; }<br>+; CHECK: fucomp1<br>+; CHECK: fldt<br>+; CHECK: fldt<br>+; CHECK: fucomp %st<br>+; CHECK: fstp<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp {<br>+entry:<br>+ tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind<br>+ ret void<br>+}<br>+<br>+; The 'u' constraint is only popped implicitly when clobbered:<br>+;<br>+; void fucomp2(long double x, long double y) {<br>+; asm volatile ("fucomp %1" : : "t"(x), "u"(y) : "st");<br>+; }<br>+;<br>+; void fucomp3(long double x, long double y) {<br>+; asm volatile ("fucompp %1" : : "t"(x), "u"(y) : "st", "st(1)");<br>+; }<br>+;<br>+; CHECK: fucomp2<br>+; CHECK: fldt<br>+; CHECK: fldt<br>+; CHECK: fucomp %st(1)<br>+; CHECK: fstp<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+;<br>+; CHECK: fucomp3<br>+; CHECK: fldt<br>+; CHECK: fldt<br>+; CHECK: fucompp %st(1)<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp {<br>+entry:<br>+ tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind<br>+ ret void<br>+}<br>+define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp {<br>+entry:<br>+ tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind<br>+ ret void<br>+}<br>+<br>+; One input, two outputs, one dead output.<br>+%complex = type { float, float }<br>+; CHECK: sincos1<br>+; CHECK: flds<br>+; CHECK-NOT: fxch<br>+; CHECK: sincos<br>+; CHECK-NOT: fstp<br>+; CHECK: fstp %st(1)<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+define float @sincos1(float %x) nounwind ssp {<br>+entry:<br>+ %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind<br>+ %asmresult = extractvalue %complex %0, 0<br>+ ret float %asmresult<br>+}<br>+<br>+; Same thing, swapped output operands.<br>+; CHECK: sincos2<br>+; CHECK: flds<br>+; CHECK-NOT: fxch<br>+; CHECK: sincos<br>+; CHECK-NOT: fstp<br>+; CHECK: fstp %st(1)<br>+; CHECK-NOT: fstp<br>+; CHECK: ret<br>+define float @sincos2(float %x) nounwind ssp {<br>+entry:<br>+ %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind<br>+ %asmresult = extractvalue %complex %0, 1<br>+ ret float %asmresult<br>+}<br>+<br>+; Clobber st(0) after it was live-out/dead from the previous asm.<br>+; CHECK: sincos3<br>+; Load x, make a copy for the second asm.<br>+; CHECK: flds<br>+; CHECK: fld %st(0)<br>+; CHECK: sincos<br>+; Discard dead result in st(0), bring x to the top.<br>+; CHECK: fstp %st(0)<br>+; CHECK: fxch<br>+; x is now in st(0) for the second asm<br>+; CHECK: sincos<br>+; Discard both results.<br>+; CHECK: fstp<br>+; CHECK: fstp<br>+; CHECK: ret<br>+define float @sincos3(float %x) nounwind ssp {<br>+entry:<br>+ %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind<br>+ %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind<br>+ %asmresult = extractvalue %complex %0, 0<br>+ ret float %asmresult<br>+}<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>