Args: Debug+Asserts/bin/llc test/CodeGen/X86/add-of-carry.ll -debug Subtarget features: SSELevel 4, 3DNowLevel 0, 64bit 1 === test1 Initial selection DAG: BB#0 'test1:entry' SelectionDAG has 15 nodes: 0x96e84f4: ch = EntryToken [ORD=1] 0x96fecc8: i32 = undef [ORD=1] 0x96e84f4: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] 0x96fecc8: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] 0x96fee60: 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] 0x96fecc8: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] 0x96e84f4: 0x96ff218: i32 = Register %EAX 0x96feee8: 0x96feee8: 0x96fee60: 0x96fef70: ch = setult [ORD=2] 0x96feff8: i1 = setcc 0x96feee8, 0x96fee60, 0x96fef70 [ORD=2] 0x96ff080: i32 = zero_extend 0x96feff8 [ORD=3] 0x96ff108: i32 = add 0x96feee8, 0x96ff080 [ORD=4] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff108 0x96ff2a0: 0x96ff190: i16 = TargetConstant<0> 0x96ff2a0: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 Optimized lowered selection DAG: BB#0 'test1:entry' SelectionDAG has 17 nodes: 0x96e84f4: ch = EntryToken [ORD=1] 0x96fecc8: i32 = undef [ORD=1] 0x96e84f4: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] 0x96fecc8: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] 0x96fee60: 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] 0x96fecc8: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] 0x96e84f4: 0x96ff218: i32 = Register %EAX 0x96feee8: 0x96feee8: 0x96fee60: 0x96fef70: ch = setult [ORD=2] 0x96feff8: i1 = setcc 0x96feee8, 0x96fee60, 0x96fef70 [ORD=2] 0x96ff080: i32 = zero_extend 0x96feff8 [ORD=3] 0x96ff108: i32 = add 0x96feee8, 0x96ff080 [ORD=4] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff108 0x96ff3b0: i32 = Constant<0> 0x96ff438: i32 = Constant<1> 0x96ff2a0: 0x96ff190: i16 = TargetConstant<0> 0x96ff2a0: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 Legally typed node: 0x96ff438: i32 = Constant<1> [ID=0] Legally typed node: 0x96ff3b0: i32 = Constant<0> [ID=0] Legally typed node: 0x96ff218: i32 = Register %EAX [ID=0] Legally typed node: 0x96ff190: i16 = TargetConstant<0> [ID=0] Legally typed node: 0x96fef70: ch = setult [ORD=2] [ID=0] Legally typed node: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] [ID=0] Legally typed node: 0x96fecc8: i32 = undef [ORD=1] [ID=0] Legally typed node: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] [ID=0] Legally typed node: 0x96e84f4: ch = EntryToken [ORD=1] [ID=0] Legally typed node: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] [ID=0] Legally typed node: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=0] Legally typed node: 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=0] Promote integer result: 0x96feff8: i1 = setcc 0x96feee8, 0x96fee60, 0x96fef70 [ORD=2] [ID=0] Promote integer operand: 0x96ff080: i32 = zero_extend 0x96feff8 [ORD=3] [ID=0] Legally typed node: 0x96ff4c0: i8 = setcc 0x96feee8, 0x96fee60, 0x96fef70 [ID=0] Legally typed node: 0x96ff548: i32 = any_extend 0x96ff4c0 [ID=0] Legally typed node: 0x96ff5d0: i32 = and 0x96ff548, 0x96ff438 [ID=0] Legally typed node: 0x96ff108: i32 = add 0x96feee8, 0x96ff5d0 [ORD=4] [ID=0] Legally typed node: 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff108 [ID=0] Legally typed node: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=0] Legally typed node: 0xffc1c558: ch = handlenode 0x96ff328 [ID=0] Type-legalized selection DAG: BB#0 'test1:entry' SelectionDAG has 17 nodes: 0x96e84f4: ch = EntryToken [ORD=1] [ID=-3] 0x96fecc8: i32 = undef [ORD=1] [ID=-3] 0x96e84f4: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] [ID=-3] 0x96fecc8: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=-3] 0x96fee60: 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] [ID=-3] 0x96fecc8: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] [ID=-3] 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=-3] 0x96e84f4: 0x96ff218: i32 = Register %EAX [ID=-3] 0x96feee8: 0x96feee8: 0x96fee60: 0x96fef70: ch = setult [ORD=2] [ID=-3] 0x96ff4c0: i8 = setcc 0x96feee8, 0x96fee60, 0x96fef70 [ID=-3] 0x96ff548: i32 = any_extend 0x96ff4c0 [ID=-3] 0x96ff438: i32 = Constant<1> [ID=-3] 0x96ff5d0: i32 = and 0x96ff548, 0x96ff438 [ID=-3] 0x96ff108: i32 = add 0x96feee8, 0x96ff5d0 [ORD=4] [ID=-3] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff108 [ID=-3] 0x96ff2a0: 0x96ff190: i16 = TargetConstant<0> [ID=-3] 0x96ff2a0: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=-3] Replacing.1 0x96ff5d0: i32 = and 0x96ff548, 0x96ff438 [ID=-3] With: 0x96feff8: i32 = zero_extend 0x96ff4c0 and 0 other values Replacing.1 0x96ff548: i32 = any_extend 0x96ff4c0 [ID=-3] With: 0x96feff8: i32 = zero_extend 0x96ff4c0 and 0 other values Optimized type-legalized selection DAG: BB#0 'test1:entry' SelectionDAG has 16 nodes: 0x96e84f4: ch = EntryToken [ORD=1] [ID=-3] 0x96fecc8: i32 = undef [ORD=1] [ID=-3] 0x96e84f4: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] [ID=-3] 0x96fecc8: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=-3] 0x96fee60: 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] [ID=-3] 0x96fecc8: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] [ID=-3] 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=-3] 0x96e84f4: 0x96ff218: i32 = Register %EAX [ID=-3] 0x96feee8: 0x96feee8: 0x96fee60: 0x96fef70: ch = setult [ORD=2] [ID=-3] 0x96ff4c0: i8 = setcc 0x96feee8, 0x96fee60, 0x96fef70 [ID=-3] 0x96feff8: i32 = zero_extend 0x96ff4c0 0x96ff108: i32 = add 0x96feee8, 0x96feff8 [ORD=4] [ID=-3] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff108 [ID=-3] 0x96ff548: i32 = Constant<0> 0x96ff2a0: 0x96ff190: i16 = TargetConstant<0> [ID=-3] 0x96ff2a0: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=-3] Legalized selection DAG: BB#0 'test1:entry' SelectionDAG has 16 nodes: 0x96e84f4: ch = EntryToken [ORD=1] [ID=0] 0x96fecc8: i32 = undef [ORD=1] [ID=2] 0x96e84f4: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] [ID=3] 0x96fecc8: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=8] 0x96fee60: 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] [ID=1] 0x96fecc8: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] [ID=7] 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=9] 0x96e84f4: 0x96ff218: i32 = Register %EAX [ID=6] 0x96feee8: 0x96ff438: i8 = Constant<2> 0x96feee8: 0x96fee60: 0x96ff548: i32 = X86ISD::CMP 0x96feee8, 0x96fee60 0x96ff5d0: i8 = X86ISD::SETCC 0x96ff438, 0x96ff548 0x96feff8: i32 = zero_extend 0x96ff5d0 [ID=11] 0x96ff108: i32 = add 0x96feee8, 0x96feff8 [ORD=4] [ID=12] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff108 [ID=13] 0x96ff2a0: 0x96ff190: i16 = TargetConstant<0> [ID=5] 0x96ff2a0: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=14] Replacing.3 0x96ff5d0: i8 = X86ISD::SETCC 0x96ff438, 0x96ff548 With: 0x96ff080: i8 = and 0x96ff4c0, 0x96fef70 Replacing.3 0x96feff8: i32 = zero_extend 0x96ff080 [ID=11] With: 0x96ff658: i32 = and 0x96ff5d0, 0x96ff3b0 Replacing.3 0x96ff108: i32 = add 0x96feee8, 0x96ff658 [ORD=4] [ID=12] With: 0x96ff080: i32 = sub 0x96feee8, 0x96fef70 Optimized legalized selection DAG: BB#0 'test1:entry' SelectionDAG has 16 nodes: 0x96e84f4: ch = EntryToken [ORD=1] [ID=0] 0x96fecc8: i32 = undef [ORD=1] [ID=2] 0x96e84f4: 0x96fedd8: i32 = FrameIndex<-2> [ORD=1] [ID=3] 0x96fecc8: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=8] 0x96fee60: 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=1] [ID=1] 0x96fecc8: 0x96fed50: i32,ch = load 0x96e84f4, 0x96fec40, 0x96fecc8 [ORD=1] [ID=7] 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=9] 0x96e84f4: 0x96ff218: i32 = Register %EAX [ID=6] 0x96feee8: 0x96ff438: i8 = Constant<2> 0x96feee8: 0x96fee60: 0x96ff548: i32 = X86ISD::CMP 0x96feee8, 0x96fee60 0x96ff4c0: i8 = X86ISD::SETCC_CARRY 0x96ff438, 0x96ff548 0x96fef70: i32 = sign_extend 0x96ff4c0 0x96ff080: i32 = sub 0x96feee8, 0x96fef70 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 [ID=13] 0x96ff2a0: 0x96ff190: i16 = TargetConstant<0> [ID=5] 0x96ff2a0: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=14] ===== Instruction selection begins: BB#0 'entry' Selecting: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=15] ISEL: Starting pattern match on root node: 0x96ff328: ch = X86ISD::RET_FLAG 0x96ff2a0, 0x96ff190, 0x96ff2a0:1 [ID=15] Morphed node: 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 ISEL: Match complete! => 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 Selecting: 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 [ID=14] => 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 Selecting: 0x96ff080: i32 = sub 0x96feee8, 0x96fef70 [ID=13] ISEL: Starting pattern match on root node: 0x96ff080: i32 = sub 0x96feee8, 0x96fef70 [ID=13] Initial Opcode index to 59325 Match failed at index 59331 Continuing at 59517 TypeSwitch[i32] from 59519 to 59522 MatchAddress: X86ISelAddressMode 0xffc1b438 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 MatchAddress: X86ISelAddressMode 0xffc1b438 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 MatchAddress: X86ISelAddressMode 0xffc1b438 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 MatchAddress: X86ISelAddressMode 0xffc1b438 Base_Reg 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ID=8] Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 Match failed at index 59526 Continuing at 59541 Match failed at index 59542 Continuing at 59559 Continuing at 59578 Match failed at index 59582 Continuing at 59648 Match failed at index 59651 Continuing at 59701 Match failed at index 59712 Continuing at 59835 Match failed at index 59836 Continuing at 59848 Match failed at index 59849 Continuing at 59861 Morphed node: 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 ISEL: Match complete! => 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 Selecting: 0x96fef70: i32 = sign_extend 0x96ff4c0 [ID=12] ISEL: Starting pattern match on root node: 0x96fef70: i32 = sign_extend 0x96ff4c0 [ID=12] Initial Opcode index to 69122 TypeSwitch[i32] from 69138 to 69154 Morphed node: 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 ISEL: Match complete! => 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 Selecting: 0x96ff548: i32 = X86ISD::CMP 0x96feee8, 0x96fee60 [ID=10] ISEL: Starting pattern match on root node: 0x96ff548: i32 = X86ISD::CMP 0x96feee8, 0x96fee60 [ID=10] Initial Opcode index to 13002 Match failed at index 13007 Continuing at 13652 Skipped scope entry (due to false predicate) at index 13657, continuing at 13690 Skipped scope entry (due to false predicate) at index 13691, continuing at 13724 Match failed at index 13734 Continuing at 13758 Match failed at index 13759 Continuing at 13792 Continuing at 13793 Match failed at index 13796 Continuing at 13893 Skipped scope entry (due to false predicate) at index 13897, continuing at 13955 Skipped scope entry (due to false predicate) at index 13956, continuing at 14014 Match failed at index 13895 Continuing at 14015 Match failed at index 14019 Continuing at 14195 Skipped scope entry (due to false predicate) at index 14200, continuing at 14251 Skipped scope entry (due to false predicate) at index 14252, continuing at 14321 Match failed at index 14328 Continuing at 14340 Match failed at index 14346 Continuing at 14379 Morphed node: 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 ISEL: Match complete! => 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 Selecting: 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=9] ISEL: Starting pattern match on root node: 0x96feee8: i32 = add 0x96fee60, 0x96fed50 [ORD=1] [ID=9] Initial Opcode index to 57594 Match failed at index 57613 Continuing at 57633 Match failed at index 57637 Continuing at 57657 MatchAddress: X86ISelAddressMode 0xffc1b440 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 Morphed node: 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] ISEL: Match complete! => 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] Selecting: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=8] ISEL: Starting pattern match on root node: 0x96fee60: i32,ch = load 0x96e84f4, 0x96fedd8, 0x96fecc8 [ORD=1] [ID=8] Initial Opcode index to 63681 Match failed at index 63693 Continuing at 63711 Match failed at index 63714 Continuing at 63732 MatchAddress: X86ISelAddressMode 0xffc1b440 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 Morphed node: 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] ISEL: Match complete! => 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] Selecting: 0x96ff218: i32 = Register %EAX [ID=5] => 0x96ff218: i32 = Register %EAX Selecting: 0x96e84f4: ch = EntryToken [ORD=1] [ID=0] => 0x96e84f4: ch = EntryToken [ORD=1] ===== Instruction selection ends: Selected selection DAG: BB#0 'test1:entry' SelectionDAG has 16 nodes: 0x96e84f4: ch = EntryToken [ORD=1] 0x96fec40: i32 = TargetFrameIndex<-2> 0x96ff4c0: 0x96ff190: 0x96ff658: 0x96ff190: 0x96e84f4: 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] 0x96fee60: 0x96ff438: i32 = TargetFrameIndex<-1> 0x96ff4c0: 0x96ff190: 0x96ff658: 0x96ff190: 0x96e84f4: 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] 0x96e84f4: 0x96ff218: i32 = Register %EAX 0x96feee8: 0x96e84f4: 0x96ff5d0: i32 = Register %EFLAGS 0x96feee8: 0x96fee60: 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 0x96ff3b0: ch,glue = CopyToReg 0x96e84f4, 0x96ff5d0, 0x96ff548 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 0x96ff190: i32 = Register %noreg 0x96ff4c0: i8 = TargetConstant<1> 0x96ff658: i32 = TargetConstant<0> 0x96ff2a0: 0x96ff2a0: 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 ********** List Scheduling BB#0 'entry' ********** SU(0): 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 [ID=0] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 [ID=0] # preds left : 1 # succs left : 0 # rdefs left : 0 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x970477c - SU(1): Latency=1 SU(1): 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 [ID=1] # preds left : 2 # succs left : 1 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x9704a6c - SU(5): Latency=1 val #0x9704838 - SU(2): Latency=1 Successors: val #0x97046c0 - SU(0): Latency=1 SU(2): 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 [ID=2] 0x96ff3b0: ch,glue = CopyToReg 0x96e84f4, 0x96ff5d0, 0x96ff548 [ID=2] # preds left : 1 # succs left : 1 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x97048f4 - SU(3): Latency=1 Successors: val #0x970477c - SU(1): Latency=1 SU(3): 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 [ID=3] # preds left : 2 # succs left : 1 # rdefs left : 0 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x9704a6c - SU(5): Latency=1 val #0x97049b0 - SU(4): Latency=1 Successors: val #0x9704838 - SU(2): Latency=1 SU(4): 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=4] # preds left : 0 # succs left : 2 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Successors: val #0x97048f4 - SU(3): Latency=1 val #0x9704a6c - SU(5): Latency=1 SU(5): 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=5] # preds left : 1 # succs left : 2 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x97049b0 - SU(4): Latency=1 Successors: val #0x970477c - SU(1): Latency=1 val #0x97048f4 - SU(3): Latency=1 Examining Available: Height 0: SU(0): 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 [ID=0] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 [ID=0] *** Scheduling [0]: SU(0): 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 [ID=0] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 [ID=0] Examining Available: Height 1: SU(1): 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 [ID=1] *** Scheduling [1]: SU(1): 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 [ID=1] Examining Available: Height 2: SU(2): 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 [ID=2] 0x96ff3b0: ch,glue = CopyToReg 0x96e84f4, 0x96ff5d0, 0x96ff548 [ID=2] *** Scheduling [2]: SU(2): 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 [ID=2] 0x96ff3b0: ch,glue = CopyToReg 0x96e84f4, 0x96ff5d0, 0x96ff548 [ID=2] Examining Available: Height 3: SU(3): 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 [ID=3] *** Scheduling [3]: SU(3): 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 [ID=3] Examining Available: Height 4: SU(5): 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=5] *** Scheduling [4]: SU(5): 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=5] Examining Available: Height 5: SU(4): 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=4] *** Scheduling [5]: SU(4): 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=4] PressureDiff 0 RegUses 0 Stall 0 Height 0 Depth 0 Static 0 Other 0 *** Final schedule *** SU(4): 0x96fee60: i32,ch = MOV32rm 0x96fec40, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=4] SU(5): 0x96feee8: i32,i32,ch = ADD32rm 0x96fee60, 0x96ff438, 0x96ff4c0, 0x96ff190, 0x96ff658, 0x96ff190, 0x96e84f4 [ORD=1] [ID=5] SU(3): 0x96ff548: i32 = CMP32rr 0x96feee8, 0x96fee60 [ID=3] SU(2): 0x96fef70: i32,i32 = SETB_C32r 0x96ff3b0:1 [ID=2] 0x96ff3b0: ch,glue = CopyToReg 0x96e84f4, 0x96ff5d0, 0x96ff548 [ID=2] SU(1): 0x96ff080: i32,i32 = SUB32rr 0x96feee8, 0x96fef70 [ID=1] SU(0): 0x96ff328: ch = RET 0x96ff2a0, 0x96ff2a0:1 [ID=0] 0x96ff2a0: ch,glue = CopyToReg 0x96e84f4, 0x96ff218, 0x96ff080 [ID=0] Total amount of phi nodes to update: 0 ******** Pre-regalloc Machine LICM: test1 ******** Entering: entry Exiting: entry ******** Machine Sinking ******** Machine Function ********** REWRITING TWO-ADDR INSTRS ********** ********** Function: test1 %vreg1 = ADD32rm %vreg0, , 1, %noreg, 0, %noreg, %EFLAGS; mem:LD4[FixedStack-1](align=16) GR32:%vreg1,%vreg0 2addr: UNFOLDING: %vreg1 = ADD32rm %vreg0, , 1, %noreg, 0, %noreg, %EFLAGS; mem:LD4[FixedStack-1](align=16) GR32:%vreg1,%vreg0 2addr: NEW LOAD: %vreg4 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg4 2addr: NEW INST: %vreg1 = ADD32rr %vreg0, %vreg4, %EFLAGS; GR32:%vreg1,%vreg0,%vreg4 2addr: COMMUTING : %vreg1 = ADD32rr %vreg0, %vreg4, %EFLAGS; GR32:%vreg1,%vreg0,%vreg4 2addr: COMMUTED TO: %vreg1 = ADD32rr %vreg4, %vreg0, %EFLAGS; GR32:%vreg1,%vreg4,%vreg0 prepend: %vreg1 = COPY %vreg4; GR32:%vreg1,%vreg4 rewrite to: %vreg1 = ADD32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 %vreg3 = SUB32rr %vreg1, %vreg2, %EFLAGS; GR32:%vreg3,%vreg1,%vreg2 prepend: %vreg3 = COPY %vreg1; GR32:%vreg3,%vreg1 rewrite to: %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 ********** PROCESS IMPLICIT DEFS ********** ********** Function: test1 0 16 %vreg0 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] GR32:%vreg0 32 %vreg4 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg4 48 %vreg1 = COPY %vreg4; GR32:%vreg1,%vreg4 64 %vreg1 = ADD32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 80 CMP32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 96 %vreg2 = SETB_C32r %EFLAGS, %EFLAGS; GR32:%vreg2 112 %vreg3 = COPY %vreg1; GR32:%vreg3,%vreg1 128 %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 144 %EAX = COPY %vreg3; GR32:%vreg3 160 RET %EAX 176 BB#0 [0L;176L) ********** COMPUTING LIVE INTERVALS ********** ********** Function: test1 BB#0: # derived from entry 16L %vreg0 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] GR32:%vreg0 register: %vreg0 +[16d,80d:0) 32L %vreg4 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg4 register: %vreg4 +[32d,48d:0) 48L %vreg1 = COPY %vreg4; GR32:%vreg1,%vreg4 register: %vreg1 +[48d,112d:0) 64L %vreg1 = ADD32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 register: %EFLAGS dead +[64d,64S:0) register: %vreg1 replace range with [48d,64d:1) RESULT: %vreg1 = [48d,64d:1)[64d,112d:0) 0@64d 1@48d 80L CMP32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 register: %EFLAGS killed +[80d,96d:1) 96L %vreg2 = SETB_C32r %EFLAGS, %EFLAGS; GR32:%vreg2 register: %EFLAGS dead +[96d,96S:2) register: %vreg2 +[96d,128d:0) 112L %vreg3 = COPY %vreg1; GR32:%vreg3,%vreg1 register: %vreg3 +[112d,144d:0) 128L %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 register: %EFLAGS dead +[128d,128S:3) register: %vreg3 replace range with [112d,128d:1) RESULT: %vreg3 = [112d,128d:1)[128d,144d:0) 0@128d 1@112d 144L %EAX = COPY %vreg3; GR32:%vreg3 register: %EAX killed +[144d,160d:0) 160L RET %EAX ********** INTERVALS ********** %vreg0 = [16d,80d:0) 0@16d %vreg2 = [96d,128d:0) 0@96d %vreg4 = [32d,48d:0) 0@32d %EFLAGS,inf = [64d,64S:0)[80d,96d:1)[96d,96S:2)[128d,128S:3) 0@64d 1@80d 2@96d 3@128d %vreg1 = [48d,64d:1)[64d,112d:0) 0@64d 1@48d %vreg3 = [112d,128d:1)[128d,144d:0) 0@128d 1@112d %EAX,inf = [144d,160d:0) 0@144d ********** MACHINEINSTRS ********** # Machine code for function test1: Frame Objects: fi#-2: size=4, align=4, fixed, at location [SP+8] fi#-1: size=4, align=16, fixed, at location [SP+4] Function Live Outs: %EAX 0L BB#0: derived from LLVM BB %entry 16L %vreg0 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] GR32:%vreg0 32L %vreg4 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg4 48L %vreg1 = COPY %vreg4; GR32:%vreg1,%vreg4 64L %vreg1 = ADD32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 80L CMP32rr %vreg1, %vreg0, %EFLAGS; GR32:%vreg1,%vreg0 96L %vreg2 = SETB_C32r %EFLAGS, %EFLAGS; GR32:%vreg2 112L %vreg3 = COPY %vreg1; GR32:%vreg3,%vreg1 128L %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 144L %EAX = COPY %vreg3; GR32:%vreg3 160L RET %EAX # End machine code for function test1. ********** COMPUTING LIVE DEBUG VARIABLES: test1 ********** ********** DEBUG VARIABLES ********** ********** SIMPLE REGISTER COALESCING ********** ********** Function: test1 ********** JOINING INTERVALS *********** entry: 144L %EAX = COPY %vreg3; GR32:%vreg3 Considering merging %vreg3 with %EAX Physreg joins disabled. 48L %vreg1 = COPY %vreg4; GR32:%vreg1,%vreg4 Considering merging %vreg4 with %vreg1 RHS = %vreg4 = [32d,48d:0) 0@32d LHS = %vreg1 = [48d,64d:1)[64d,112d:0) 0@64d 1@48d updated: 32L %vreg1 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg1 Joined. Result = %vreg1 = [32d,64d:1)[64d,112d:0) 0@64d 1@32d 112L %vreg3 = COPY %vreg1; GR32:%vreg3,%vreg1 Considering merging %vreg1 with %vreg3 RHS = %vreg1 = [32d,64d:1)[64d,112d:0) 0@64d 1@32d LHS = %vreg3 = [112d,128d:1)[128d,144d:0) 0@128d 1@112d updated: 64L %vreg3 = ADD32rr %vreg3, %vreg0, %EFLAGS; GR32:%vreg3,%vreg0 updated: 32L %vreg3 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg3 updated: 80L CMP32rr %vreg3, %vreg0, %EFLAGS; GR32:%vreg3,%vreg0 Joined. Result = %vreg3 = [32d,64d:2)[64d,128d:1)[128d,144d:0) 0@128d 1@64d 2@32d ********** INTERVALS POST JOINING ********** %vreg0 = [16d,80d:0) 0@16d %vreg2 = [96d,128d:0) 0@96d %EFLAGS,inf = [64d,64S:0)[80d,96d:1)[96d,96S:2)[128d,128S:3) 0@64d 1@80d 2@96d 3@128d %vreg3 = [32d,64d:2)[64d,128d:1)[128d,144d:0) 0@128d 1@64d 2@32d %EAX,inf = [144d,160d:0) 0@144d ********** INTERVALS ********** %vreg0 = [16d,80d:0) 0@16d %vreg2 = [96d,128d:0) 0@96d %EFLAGS,inf = [64d,64S:0)[80d,96d:1)[96d,96S:2)[128d,128S:3) 0@64d 1@80d 2@96d 3@128d %vreg3 = [32d,64d:2)[64d,128d:1)[128d,144d:0) 0@128d 1@64d 2@32d %EAX,inf = [144d,160d:0) 0@144d ********** MACHINEINSTRS ********** # Machine code for function test1: Frame Objects: fi#-2: size=4, align=4, fixed, at location [SP+8] fi#-1: size=4, align=16, fixed, at location [SP+4] Function Live Outs: %EAX 0L BB#0: derived from LLVM BB %entry 16L %vreg0 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] GR32:%vreg0 32L %vreg3 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg3 64L %vreg3 = ADD32rr %vreg3, %vreg0, %EFLAGS; GR32:%vreg3,%vreg0 80L CMP32rr %vreg3, %vreg0, %EFLAGS; GR32:%vreg3,%vreg0 96L %vreg2 = SETB_C32r %EFLAGS, %EFLAGS; GR32:%vreg2 128L %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 144L %EAX = COPY %vreg3; GR32:%vreg3 160L RET %EAX # End machine code for function test1. ********** DEBUG VARIABLES ********** ********** Compute Spill Weights ********** ********** Function: test1 ********** GREEDY REGISTER ALLOCATION ********** ********** Function: test1 selectOrSplit GR32:%vreg3,1.380859e-02 = [32d,64d:2)[64d,128d:1)[128d,144d:0) 0@128d 1@64d 2@32d AllocationOrder(GR32) = [ %EAX %ECX %EDX ] assigning %vreg3 to %EAX selectOrSplit GR32:%vreg0,3.232759e-03 = [16d,80d:0) 0@16d assigning %vreg0 to %ECX selectOrSplit GR32:%vreg2,inf = [96d,128d:0) 0@96d assigning %vreg2 to %ECX ********** REWRITE VIRTUAL REGISTERS ********** ********** Function: test1 ********** REGISTER MAP ********** [%vreg0 -> %ECX] GR32 [%vreg2 -> %ECX] GR32 [%vreg3 -> %EAX] GR32 0L BB#0: derived from LLVM BB %entry 16L %vreg0 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] GR32:%vreg0 32L %vreg3 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) GR32:%vreg3 64L %vreg3 = ADD32rr %vreg3, %vreg0, %EFLAGS; GR32:%vreg3,%vreg0 80L CMP32rr %vreg3, %vreg0, %EFLAGS; GR32:%vreg3,%vreg0 96L %vreg2 = SETB_C32r %EFLAGS, %EFLAGS; GR32:%vreg2 128L %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 144L %EAX = COPY %vreg3; GR32:%vreg3 160L RET %EAX > %ECX = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] > %EAX = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-1](align=16) > %EAX = ADD32rr %EAX, %ECX, %EFLAGS > CMP32rr %EAX, %ECX, %EFLAGS > %ECX = SETB_C32r %EFLAGS, %EFLAGS > %EAX = SUB32rr %EAX, %ECX, %EFLAGS > %EAX = COPY %EAX Deleting identity copy. > RET %EAX ********** EMITTING LIVE DEBUG VARIABLES ********** ********** Stack Slot Coloring ********** ********** Function: test1 ******** Post-regalloc Machine LICM: test1 ******** Machine Function ********** LOWERING SUBREG INSTRS ********** ********** Function: test1 === test2 Initial selection DAG: BB#0 'test2:entry' SelectionDAG has 13 nodes: 0x96e84f4: ch = EntryToken [ORD=5] 0x96ff658: i32 = undef [ORD=5] 0x96e84f4: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] 0x96ff658: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] 0x96ff658: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] 0x96ff5d0: i32,i1 = uaddo 0x96ff3b0, 0x96ff4c0 [ORD=5] 0x96e84f4: 0x96ff080: i32 = Register %EAX 0x96ff5d0: 0x96ff5d0: 0x96ff190: i32 = zero_extend 0x96ff5d0:1 [ORD=8] 0x96ff328: i32 = add 0x96ff5d0, 0x96ff190 [ORD=9] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96ff328 0x96fef70: 0x96ff2a0: i16 = TargetConstant<0> 0x96fef70: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 Optimized lowered selection DAG: BB#0 'test2:entry' SelectionDAG has 13 nodes: 0x96e84f4: ch = EntryToken [ORD=5] 0x96ff658: i32 = undef [ORD=5] 0x96e84f4: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] 0x96ff658: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] 0x96ff658: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] 0x96ff5d0: i32,i1 = uaddo 0x96ff3b0, 0x96ff4c0 [ORD=5] 0x96e84f4: 0x96ff080: i32 = Register %EAX 0x96ff5d0: 0x96ff5d0: 0x96ff190: i32 = zero_extend 0x96ff5d0:1 [ORD=8] 0x96ff328: i32 = add 0x96ff5d0, 0x96ff190 [ORD=9] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96ff328 0x96fef70: 0x96ff2a0: i16 = TargetConstant<0> 0x96fef70: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 Legally typed node: 0x96ff080: i32 = Register %EAX [ID=0] Legally typed node: 0x96ff2a0: i16 = TargetConstant<0> [ID=0] Legally typed node: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] [ID=0] Legally typed node: 0x96ff658: i32 = undef [ORD=5] [ID=0] Legally typed node: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] [ID=0] Legally typed node: 0x96e84f4: ch = EntryToken [ORD=5] [ID=0] Legally typed node: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] [ID=0] Legally typed node: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=0] Promote integer result: 0x96ff5d0: i32,i1 = uaddo 0x96ff3b0, 0x96ff4c0 [ORD=5] [ID=0] Promote integer operand: 0x96ff190: i32 = zero_extend 0x96ff5d0:1 [ORD=8] [ID=0] Legally typed node: 0x96ff218: i32 = Constant<1> [ID=0] Legally typed node: 0x96feee8: i32,i8 = uaddo 0x96ff3b0, 0x96ff4c0 [ID=0] Legally typed node: 0x96fee60: i32 = any_extend 0x96feee8:1 [ID=0] Legally typed node: 0x96fedd8: i32 = and 0x96fee60, 0x96ff218 [ID=0] Legally typed node: 0x96ff328: i32 = add 0x96feee8, 0x96fedd8 [ORD=9] [ID=0] Legally typed node: 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96ff328 [ID=0] Legally typed node: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=0] Legally typed node: 0xffc1c558: ch = handlenode 0x96ff548 [ID=0] Type-legalized selection DAG: BB#0 'test2:entry' SelectionDAG has 15 nodes: 0x96e84f4: ch = EntryToken [ORD=5] [ID=-3] 0x96ff658: i32 = undef [ORD=5] [ID=-3] 0x96e84f4: 0x96ff080: i32 = Register %EAX [ID=-3] 0x96feee8: 0x96feee8: 0x96fee60: i32 = any_extend 0x96feee8:1 [ID=-3] 0x96ff218: i32 = Constant<1> [ID=-3] 0x96fedd8: i32 = and 0x96fee60, 0x96ff218 [ID=-3] 0x96ff328: i32 = add 0x96feee8, 0x96fedd8 [ORD=9] [ID=-3] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96ff328 [ID=-3] 0x96e84f4: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] [ID=-3] 0x96ff658: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=-3] 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] [ID=-3] 0x96ff658: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] [ID=-3] 0x96feee8: i32,i8 = uaddo 0x96ff3b0, 0x96ff4c0 [ID=-3] 0x96fef70: 0x96ff2a0: i16 = TargetConstant<0> [ID=-3] 0x96fef70: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=-3] Replacing.1 0x96fedd8: i32 = and 0x96fee60, 0x96ff218 [ID=-3] With: 0x96ff5d0: i32 = zero_extend 0x96feee8:1 and 0 other values Replacing.1 0x96fee60: i32 = any_extend 0x96feee8:1 [ID=-3] With: 0x96ff5d0: i32 = zero_extend 0x96feee8:1 and 0 other values Optimized type-legalized selection DAG: BB#0 'test2:entry' SelectionDAG has 13 nodes: 0x96e84f4: ch = EntryToken [ORD=5] [ID=-3] 0x96ff658: i32 = undef [ORD=5] [ID=-3] 0x96e84f4: 0x96ff080: i32 = Register %EAX [ID=-3] 0x96feee8: 0x96feee8: 0x96ff5d0: i32 = zero_extend 0x96feee8:1 0x96ff328: i32 = add 0x96feee8, 0x96ff5d0 [ORD=9] [ID=-3] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96ff328 [ID=-3] 0x96e84f4: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] [ID=-3] 0x96ff658: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=-3] 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] [ID=-3] 0x96ff658: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] [ID=-3] 0x96feee8: i32,i8 = uaddo 0x96ff3b0, 0x96ff4c0 [ID=-3] 0x96fef70: 0x96ff2a0: i16 = TargetConstant<0> [ID=-3] 0x96fef70: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=-3] Legalized selection DAG: BB#0 'test2:entry' SelectionDAG has 15 nodes: 0x96e84f4: ch = EntryToken [ORD=5] [ID=0] 0x96ff658: i32 = undef [ORD=5] [ID=2] 0x96e84f4: 0x96ff080: i32 = Register %EAX [ID=5] 0x96ff218: 0x96fee60: i32 = Constant<2> 0x96ff218: 0x96fedd8: i8 = X86ISD::SETCC 0x96fee60, 0x96ff218:1 0x96ff5d0: i32 = zero_extend 0x96fedd8 [ID=9] 0x96ff328: i32 = add 0x96ff218, 0x96ff5d0 [ORD=9] [ID=10] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96ff328 [ID=11] 0x96e84f4: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] [ID=3] 0x96ff658: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=7] 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] [ID=1] 0x96ff658: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] [ID=6] 0x96ff218: i32,i32 = X86ISD::ADD 0x96ff3b0, 0x96ff4c0 0x96fef70: 0x96ff2a0: i16 = TargetConstant<0> [ID=4] 0x96fef70: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=12] Replacing.3 0x96fedd8: i8 = X86ISD::SETCC 0x96fee60, 0x96ff218:1 With: 0x96fed50: i8 = and 0x96fecc8, 0x96feee8 Replacing.3 0x96ff5d0: i32 = zero_extend 0x96fed50 [ID=9] With: 0x96ff108: i32 = and 0x96fee60, 0x96fedd8 Replacing.3 0x96ff328: i32 = add 0x96ff218, 0x96ff108 [ORD=9] [ID=10] With: 0x96fed50: i32 = sub 0x96ff218, 0x96feee8 Optimized legalized selection DAG: BB#0 'test2:entry' SelectionDAG has 15 nodes: 0x96e84f4: ch = EntryToken [ORD=5] [ID=0] 0x96ff658: i32 = undef [ORD=5] [ID=2] 0x96e84f4: 0x96ff080: i32 = Register %EAX [ID=5] 0x96ff218: 0x96ff190: i8 = Constant<2> 0x96ff218: 0x96fecc8: i8 = X86ISD::SETCC_CARRY 0x96ff190, 0x96ff218:1 0x96feee8: i32 = sign_extend 0x96fecc8 0x96fed50: i32 = sub 0x96ff218, 0x96feee8 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 [ID=11] 0x96e84f4: 0x96ff438: i32 = FrameIndex<-2> [ORD=5] [ID=3] 0x96ff658: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=7] 0x96e84f4: 0x96fec40: i32 = FrameIndex<-1> [ORD=5] [ID=1] 0x96ff658: 0x96ff4c0: i32,ch = load 0x96e84f4, 0x96fec40, 0x96ff658 [ORD=5] [ID=6] 0x96ff218: i32,i32 = X86ISD::ADD 0x96ff3b0, 0x96ff4c0 0x96fef70: 0x96ff2a0: i16 = TargetConstant<0> [ID=4] 0x96fef70: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=12] ===== Instruction selection begins: BB#0 'entry' Selecting: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=14] ISEL: Starting pattern match on root node: 0x96ff548: ch = X86ISD::RET_FLAG 0x96fef70, 0x96ff2a0, 0x96fef70:1 [ID=14] Initial Opcode index to 70111 Morphed node: 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 ISEL: Match complete! => 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 Selecting: 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 [ID=13] => 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 Selecting: 0x96fed50: i32 = sub 0x96ff218, 0x96feee8 [ID=12] ISEL: Starting pattern match on root node: 0x96fed50: i32 = sub 0x96ff218, 0x96feee8 [ID=12] Initial Opcode index to 59325 Match failed at index 59331 Continuing at 59517 TypeSwitch[i32] from 59519 to 59522 MatchAddress: X86ISelAddressMode 0xffc1b438 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 MatchAddress: X86ISelAddressMode 0xffc1b438 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 Match failed at index 59526 Continuing at 59541 Match failed at index 59542 Continuing at 59559 Continuing at 59578 Match failed at index 59582 Continuing at 59648 Match failed at index 59651 Continuing at 59701 Match failed at index 59712 Continuing at 59835 Match failed at index 59836 Continuing at 59848 Match failed at index 59849 Continuing at 59861 Morphed node: 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 ISEL: Match complete! => 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 Selecting: 0x96fee60: i32 = Constant<0> [ID=12] ISEL: Starting pattern match on root node: 0x96fee60: i32 = Constant<0> [ID=12] Initial Opcode index to 71222 TypeSwitch[i32] from 71226 to 71259 Morphed node: 0x96fee60: i32,i32 = MOV32r0 ISEL: Match complete! => 0x96fee60: i32,i32 = MOV32r0 Selecting: 0x96feee8: i32 = sign_extend 0x96fecc8 [ID=11] ISEL: Starting pattern match on root node: 0x96feee8: i32 = sign_extend 0x96fecc8 [ID=11] Initial Opcode index to 69122 TypeSwitch[i32] from 69138 to 69154 Morphed node: 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 ISEL: Match complete! => 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 Selecting: 0x96ff218: i32,i32 = X86ISD::ADD 0x96ff3b0, 0x96ff4c0 [ID=9] ISEL: Starting pattern match on root node: 0x96ff218: i32,i32 = X86ISD::ADD 0x96ff3b0, 0x96ff4c0 [ID=9] Initial Opcode index to 54133 Match failed at index 54152 Continuing at 54172 Match failed at index 54176 Continuing at 54196 MatchAddress: X86ISelAddressMode 0xffc1b440 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 Morphed node: 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 ISEL: Match complete! => 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 Selecting: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=8] ISEL: Starting pattern match on root node: 0x96ff3b0: i32,ch = load 0x96e84f4, 0x96ff438, 0x96ff658 [ORD=5] [ID=8] Initial Opcode index to 63681 Match failed at index 63693 Continuing at 63711 Match failed at index 63714 Continuing at 63732 MatchAddress: X86ISelAddressMode 0xffc1b440 Base_Reg nul Base.FrameIndex 0 Scale1 IndexReg nul Disp 0 GV nul CP nul ES nul JT-1 Align0 Morphed node: 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] ISEL: Match complete! => 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] Selecting: 0x96ff080: i32 = Register %EAX [ID=5] => 0x96ff080: i32 = Register %EAX Selecting: 0x96e84f4: ch = EntryToken [ORD=5] [ID=0] => 0x96e84f4: ch = EntryToken [ORD=5] ===== Instruction selection ends: Selected selection DAG: BB#0 'test2:entry' SelectionDAG has 17 nodes: 0x96e84f4: ch = EntryToken [ORD=5] 0x96fec40: i32 = TargetFrameIndex<-2> 0x96fecc8: 0x96ff2a0: 0x96ff5d0: 0x96ff2a0: 0x96e84f4: 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] 0x96ff190: i32 = TargetFrameIndex<-1> 0x96fecc8: 0x96ff2a0: 0x96ff5d0: 0x96ff2a0: 0x96e84f4: 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 0x96e84f4: 0x96ff108: i32 = Register %EFLAGS 0x96ff218: 0x96ff328: ch,glue = CopyToReg 0x96e84f4, 0x96ff108, 0x96ff218:1 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 0x96fee60: i32,i32 = MOV32r0 0x96feee8: 0x96fedd8: i32 = sub 0x96fee60, 0x96feee8 [ID=12] 0x96e84f4: 0x96ff080: i32 = Register %EAX 0x96ff218: 0x96feee8: 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 0x96ff2a0: i32 = Register %noreg 0x96fecc8: i8 = TargetConstant<1> 0x96ff5d0: i32 = TargetConstant<0> 0x96fef70: 0x96fef70: 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 ********** List Scheduling BB#0 'entry' ********** SU(0): 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 [ID=0] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 [ID=0] # preds left : 1 # succs left : 0 # rdefs left : 0 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x97195e4 - SU(1): Latency=1 SU(1): 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 [ID=1] # preds left : 2 # succs left : 1 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x971975c - SU(3): Latency=1 val #0x97196a0 - SU(2): Latency=1 Successors: val #0x9719528 - SU(0): Latency=1 SU(2): 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 [ID=2] 0x96ff328: ch,glue = CopyToReg 0x96e84f4, 0x96ff108, 0x96ff218:1 [ID=2] # preds left : 1 # succs left : 1 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x971975c - SU(3): Latency=1 Successors: val #0x97195e4 - SU(1): Latency=1 SU(3): 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ID=3] # preds left : 1 # succs left : 2 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Predecessors: val #0x9719818 - SU(4): Latency=1 Successors: val #0x97195e4 - SU(1): Latency=1 val #0x97196a0 - SU(2): Latency=1 SU(4): 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] [ID=4] # preds left : 0 # succs left : 1 # rdefs left : 1 Latency : 1 Depth : 0 Height : 0 Successors: val #0x971975c - SU(3): Latency=1 Adding a pseudo-two-addr edge from SU #1 to SU #2 Examining Available: Height 0: SU(0): 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 [ID=0] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 [ID=0] *** Scheduling [0]: SU(0): 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 [ID=0] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 [ID=0] Examining Available: Height 1: SU(1): 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 [ID=1] *** Scheduling [1]: SU(1): 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 [ID=1] Examining Available: Height 2: SU(2): 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 [ID=2] 0x96ff328: ch,glue = CopyToReg 0x96e84f4, 0x96ff108, 0x96ff218:1 [ID=2] *** Scheduling [2]: SU(2): 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 [ID=2] 0x96ff328: ch,glue = CopyToReg 0x96e84f4, 0x96ff108, 0x96ff218:1 [ID=2] Examining Available: Height 3: SU(3): 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ID=3] *** Scheduling [3]: SU(3): 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ID=3] Examining Available: Height 4: SU(4): 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] [ID=4] *** Scheduling [4]: SU(4): 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] [ID=4] PressureDiff 0 RegUses 0 Stall 0 Height 0 Depth 0 Static 0 Other 0 *** Final schedule *** SU(4): 0x96ff3b0: i32,ch = MOV32rm 0x96fec40, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ORD=5] [ID=4] SU(3): 0x96ff218: i32,i32,ch = ADD32rm 0x96ff3b0, 0x96ff190, 0x96fecc8, 0x96ff2a0, 0x96ff5d0, 0x96ff2a0, 0x96e84f4 [ID=3] SU(2): 0x96feee8: i32,i32 = SETB_C32r 0x96ff328:1 [ID=2] 0x96ff328: ch,glue = CopyToReg 0x96e84f4, 0x96ff108, 0x96ff218:1 [ID=2] SU(1): 0x96fed50: i32,i32 = SUB32rr 0x96ff218, 0x96feee8 [ID=1] SU(0): 0x96ff548: ch = RET 0x96fef70, 0x96fef70:1 [ID=0] 0x96fef70: ch,glue = CopyToReg 0x96e84f4, 0x96ff080, 0x96fed50 [ID=0] Total amount of phi nodes to update: 0 ******** Pre-regalloc Machine LICM: test2 ******** Entering: entry Exiting: entry ******** Machine Sinking ******** Machine Function ********** REWRITING TWO-ADDR INSTRS ********** ********** Function: test2 %vreg1 = ADD32rm %vreg0, , 1, %noreg, 0, %noreg, %EFLAGS; mem:LD4[FixedStack-1](align=16) GR32:%vreg1,%vreg0 prepend: %vreg1 = COPY %vreg0; GR32:%vreg1,%vreg0 rewrite to: %vreg1 = ADD32rm %vreg1, , 1, %noreg, 0, %noreg, %EFLAGS; mem:LD4[FixedStack-1](align=16) GR32:%vreg1 %vreg3 = SUB32rr %vreg1, %vreg2, %EFLAGS; GR32:%vreg3,%vreg1,%vreg2 prepend: %vreg3 = COPY %vreg1; GR32:%vreg3,%vreg1 rewrite to: %vreg3 = SUB32rr %vreg3, %vreg2, %EFLAGS; GR32:%vreg3,%vreg2 ********** PROCESS IMPLICIT DEFS ********** ********** Function: test2 0 16 %vreg0 = MOV32rm , 1, %noreg, 0, %noreg; mem:LD4[FixedStack-2] GR32:%vreg0 32 %vreg1 = COPY %vreg0; GR32:%vreg1,%vreg0 48 %vreg1 = ADD32rm %vreg1, , 1, %noreg, 0, %noreg, %EFLAGS; mem:LD4[FixedStack-1](align=16) GR32:%vreg1 64 %vreg2