<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><div><div>On May 26, 2011, at 10:02 PM, Bob Wilson wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Can you add a test for the auto-upgrade code? Look in test/Bitcode for examples of how to do that. Basically you commit a binary .bc file with the old intrinsics and then add a .ll test file that checks for the correct auto-upgrades.<font class="Apple-style-span" color="#000000"><font class="Apple-style-span" color="#144FAE"><br></font></font></div></blockquote><div><br></div><div>Done. See revisions 132163 and 132207.</div><br><blockquote type="cite"><div>Also, please include the PR or Radar number in the commit message.<br></div></blockquote><div><br></div><div>Will do going forward.</div><div><br></div><div> Chad</div><br><blockquote type="cite"><div>On May 26, 2011, at 4:13 PM, Chad Rosier wrote:<br><br><blockquote type="cite">Author: mcrosier<br></blockquote><blockquote type="cite">Date: Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">New Revision: 132163<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=132163&view=rev">http://llvm.org/viewvc/llvm-project?rev=132163&view=rev</a><br></blockquote><blockquote type="cite">Log:<br></blockquote><blockquote type="cite">Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. <br></blockquote><blockquote type="cite">crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and<br></blockquote><blockquote type="cite">crc64.[8|16|32] have been renamed to .crc32.64.[8|64].<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Added:<br></blockquote><blockquote type="cite"> llvm/trunk/test/CodeGen/X86/sse42_64.ll<br></blockquote><blockquote type="cite">Modified:<br></blockquote><blockquote type="cite"> llvm/trunk/include/llvm/IntrinsicsX86.td<br></blockquote><blockquote type="cite"> llvm/trunk/lib/Analysis/ValueTracking.cpp<br></blockquote><blockquote type="cite"> llvm/trunk/lib/Target/X86/X86InstrSSE.td<br></blockquote><blockquote type="cite"> llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp<br></blockquote><blockquote type="cite"> llvm/trunk/lib/VMCore/AutoUpgrade.cpp<br></blockquote><blockquote type="cite"> llvm/trunk/test/CodeGen/X86/sse42.ll<br></blockquote><blockquote type="cite"> llvm/trunk/test/Transforms/InstCombine/x86-crc32-demanded.ll<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/include/llvm/IntrinsicsX86.td<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/include/llvm/IntrinsicsX86.td (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/include/llvm/IntrinsicsX86.td Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -948,19 +948,19 @@<br></blockquote><blockquote type="cite">// Miscellaneous<br></blockquote><blockquote type="cite">// CRC Instruction<br></blockquote><blockquote type="cite">let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".<br></blockquote><blockquote type="cite">- def int_x86_sse42_crc32_8 : GCCBuiltin<"__builtin_ia32_crc32qi">,<br></blockquote><blockquote type="cite">+ def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi">,<br></blockquote><blockquote type="cite"> Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i8_ty],<br></blockquote><blockquote type="cite"> [IntrNoMem]>;<br></blockquote><blockquote type="cite">- def int_x86_sse42_crc32_16 : GCCBuiltin<"__builtin_ia32_crc32hi">,<br></blockquote><blockquote type="cite">+ def int_x86_sse42_crc32_32_16 : GCCBuiltin<"__builtin_ia32_crc32hi">,<br></blockquote><blockquote type="cite"> Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i16_ty],<br></blockquote><blockquote type="cite"> [IntrNoMem]>;<br></blockquote><blockquote type="cite">- def int_x86_sse42_crc32_32 : GCCBuiltin<"__builtin_ia32_crc32si">,<br></blockquote><blockquote type="cite">+ def int_x86_sse42_crc32_32_32 : GCCBuiltin<"__builtin_ia32_crc32si">,<br></blockquote><blockquote type="cite"> Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],<br></blockquote><blockquote type="cite"> [IntrNoMem]>;<br></blockquote><blockquote type="cite">- def int_x86_sse42_crc64_8 :<br></blockquote><blockquote type="cite">+ def int_x86_sse42_crc32_64_8 :<br></blockquote><blockquote type="cite"> Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i8_ty],<br></blockquote><blockquote type="cite"> [IntrNoMem]>;<br></blockquote><blockquote type="cite">- def int_x86_sse42_crc64_64 : GCCBuiltin<"__builtin_ia32_crc32di">,<br></blockquote><blockquote type="cite">+ def int_x86_sse42_crc32_64_64 : GCCBuiltin<"__builtin_ia32_crc32di">,<br></blockquote><blockquote type="cite"> Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],<br></blockquote><blockquote type="cite"> [IntrNoMem]>;<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/Analysis/ValueTracking.cpp (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/Analysis/ValueTracking.cpp Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -680,8 +680,8 @@<br></blockquote><blockquote type="cite"> KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - LowBits);<br></blockquote><blockquote type="cite"> break;<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite">- case Intrinsic::x86_sse42_crc64_8:<br></blockquote><blockquote type="cite">- case Intrinsic::x86_sse42_crc64_64:<br></blockquote><blockquote type="cite">+ case Intrinsic::x86_sse42_crc32_64_8:<br></blockquote><blockquote type="cite">+ case Intrinsic::x86_sse42_crc32_64_64:<br></blockquote><blockquote type="cite"> KnownZero = APInt::getHighBitsSet(64, 32);<br></blockquote><blockquote type="cite"> break;<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -4935,66 +4935,66 @@<br></blockquote><blockquote type="cite">// This set of instructions are only rm, the only difference is the size<br></blockquote><blockquote type="cite">// of r and m.<br></blockquote><blockquote type="cite">let Constraints = "$src1 = $dst" in {<br></blockquote><blockquote type="cite">- def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),<br></blockquote><blockquote type="cite"> (ins GR32:$src1, i8mem:$src2),<br></blockquote><blockquote type="cite"> "crc32{b} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR32:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc32_8 GR32:$src1,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_32_8 GR32:$src1,<br></blockquote><blockquote type="cite"> (load addr:$src2)))]>;<br></blockquote><blockquote type="cite">- def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),<br></blockquote><blockquote type="cite"> (ins GR32:$src1, GR8:$src2),<br></blockquote><blockquote type="cite"> "crc32{b} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR32:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;<br></blockquote><blockquote type="cite">- def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;<br></blockquote><blockquote type="cite">+ def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),<br></blockquote><blockquote type="cite"> (ins GR32:$src1, i16mem:$src2),<br></blockquote><blockquote type="cite"> "crc32{w} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR32:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc32_16 GR32:$src1,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_32_16 GR32:$src1,<br></blockquote><blockquote type="cite"> (load addr:$src2)))]>,<br></blockquote><blockquote type="cite"> OpSize;<br></blockquote><blockquote type="cite">- def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),<br></blockquote><blockquote type="cite"> (ins GR32:$src1, GR16:$src2),<br></blockquote><blockquote type="cite"> "crc32{w} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR32:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,<br></blockquote><blockquote type="cite"> OpSize;<br></blockquote><blockquote type="cite">- def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),<br></blockquote><blockquote type="cite"> (ins GR32:$src1, i32mem:$src2),<br></blockquote><blockquote type="cite"> "crc32{l} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR32:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc32_32 GR32:$src1,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_32_32 GR32:$src1,<br></blockquote><blockquote type="cite"> (load addr:$src2)))]>;<br></blockquote><blockquote type="cite">- def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),<br></blockquote><blockquote type="cite"> (ins GR32:$src1, GR32:$src2),<br></blockquote><blockquote type="cite"> "crc32{l} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR32:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;<br></blockquote><blockquote type="cite">- def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;<br></blockquote><blockquote type="cite">+ def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),<br></blockquote><blockquote type="cite"> (ins GR64:$src1, i8mem:$src2),<br></blockquote><blockquote type="cite"> "crc32{b} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR64:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc64_8 GR64:$src1,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_64_8 GR64:$src1,<br></blockquote><blockquote type="cite"> (load addr:$src2)))]>,<br></blockquote><blockquote type="cite"> REX_W;<br></blockquote><blockquote type="cite">- def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),<br></blockquote><blockquote type="cite"> (ins GR64:$src1, GR8:$src2),<br></blockquote><blockquote type="cite"> "crc32{b} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR64:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,<br></blockquote><blockquote type="cite"> REX_W;<br></blockquote><blockquote type="cite">- def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),<br></blockquote><blockquote type="cite"> (ins GR64:$src1, i64mem:$src2),<br></blockquote><blockquote type="cite"> "crc32{q} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR64:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc64_64 GR64:$src1,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_64_64 GR64:$src1,<br></blockquote><blockquote type="cite"> (load addr:$src2)))]>,<br></blockquote><blockquote type="cite"> REX_W;<br></blockquote><blockquote type="cite">- def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),<br></blockquote><blockquote type="cite">+ def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),<br></blockquote><blockquote type="cite"> (ins GR64:$src1, GR64:$src2),<br></blockquote><blockquote type="cite"> "crc32{q} \t{$src2, $src1|$src1, $src2}",<br></blockquote><blockquote type="cite"> [(set GR64:$dst,<br></blockquote><blockquote type="cite">- (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,<br></blockquote><blockquote type="cite">+ (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,<br></blockquote><blockquote type="cite"> REX_W;<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -780,8 +780,8 @@<br></blockquote><blockquote type="cite"> // TODO: Could compute known zero/one bits based on the input.<br></blockquote><blockquote type="cite"> break;<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite">- case Intrinsic::x86_sse42_crc64_8:<br></blockquote><blockquote type="cite">- case Intrinsic::x86_sse42_crc64_64:<br></blockquote><blockquote type="cite">+ case Intrinsic::x86_sse42_crc32_64_8:<br></blockquote><blockquote type="cite">+ case Intrinsic::x86_sse42_crc32_64_64:<br></blockquote><blockquote type="cite"> KnownZero = APInt::getHighBitsSet(64, 32);<br></blockquote><blockquote type="cite"> return 0;<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -285,7 +285,33 @@<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> break;<br></blockquote><blockquote type="cite">- case 'x': <br></blockquote><blockquote type="cite">+ case 'x':<br></blockquote><blockquote type="cite">+ // This fixes the poorly named crc32 intrinsics<br></blockquote><blockquote type="cite">+ if (Name.compare(5, 13, "x86.sse42.crc", 13) == 0) {<br></blockquote><blockquote type="cite">+ const char* NewFnName = NULL;<br></blockquote><blockquote type="cite">+ if (Name.compare(18, 2, "32", 2) == 0) {<br></blockquote><blockquote type="cite">+ if (Name.compare(20, 2, ".8") == 0) {<br></blockquote><blockquote type="cite">+ NewFnName = "llvm.x86.sse42.crc32.32.8";<br></blockquote><blockquote type="cite">+ } else if (Name.compare(20, 2, ".16") == 0) {<br></blockquote><blockquote type="cite">+ NewFnName = "llvm.x86.sse42.crc32.32.16";<br></blockquote><blockquote type="cite">+ } else if (Name.compare(20, 2, ".32") == 0) {<br></blockquote><blockquote type="cite">+ NewFnName = "llvm.x86.sse42.crc32.32.32";<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ else if (Name.compare(18, 2, "64", 2) == 0) {<br></blockquote><blockquote type="cite">+ if (Name.compare(20, 2, ".8") == 0) {<br></blockquote><blockquote type="cite">+ NewFnName = "llvm.x86.sse42.crc32.64.8";<br></blockquote><blockquote type="cite">+ } else if (Name.compare(20, 2, ".64") == 0) {<br></blockquote><blockquote type="cite">+ NewFnName = "llvm.x86.sse42.crc32.64.64";<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ if (NewFnName) {<br></blockquote><blockquote type="cite">+ F->setName(NewFnName);<br></blockquote><blockquote type="cite">+ NewFn = F;<br></blockquote><blockquote type="cite">+ return true;<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite"> // This fixes all MMX shift intrinsic instructions to take a<br></blockquote><blockquote type="cite"> // x86_mmx instead of a v1i64, v2i32, v4i16, or v8i8.<br></blockquote><blockquote type="cite"> if (Name.compare(5, 8, "x86.mmx.", 8) == 0) {<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/test/CodeGen/X86/sse42.ll<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42.ll?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42.ll?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/test/CodeGen/X86/sse42.ll (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/test/CodeGen/X86/sse42.ll Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -1,38 +1,39 @@<br></blockquote><blockquote type="cite">; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32<br></blockquote><blockquote type="cite">; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind<br></blockquote><blockquote type="cite">-declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind<br></blockquote><blockquote type="cite">-declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind<br></blockquote><blockquote type="cite">+declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind<br></blockquote><blockquote type="cite">+declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind<br></blockquote><blockquote type="cite">+declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-define i32 @crc32_8(i32 %a, i8 %b) nounwind {<br></blockquote><blockquote type="cite">- %tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b)<br></blockquote><blockquote type="cite">+define i32 @crc32_32_8(i32 %a, i8 %b) nounwind {<br></blockquote><blockquote type="cite">+ %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b)<br></blockquote><blockquote type="cite"> ret i32 %tmp<br></blockquote><blockquote type="cite">-; X32: _crc32_8:<br></blockquote><blockquote type="cite">+; X32: _crc32_32_8:<br></blockquote><blockquote type="cite">; X32: crc32b 8(%esp), %eax<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-; X64: _crc32_8:<br></blockquote><blockquote type="cite">+; X64: _crc32_32_8:<br></blockquote><blockquote type="cite">; X64: crc32b %sil,<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-define i32 @crc32_16(i32 %a, i16 %b) nounwind {<br></blockquote><blockquote type="cite">- %tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b)<br></blockquote><blockquote type="cite">+define i32 @crc32_32_16(i32 %a, i16 %b) nounwind {<br></blockquote><blockquote type="cite">+ %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b)<br></blockquote><blockquote type="cite"> ret i32 %tmp<br></blockquote><blockquote type="cite">-; X32: _crc32_16:<br></blockquote><blockquote type="cite">+; X32: _crc32_32_16:<br></blockquote><blockquote type="cite">; X32: crc32w 8(%esp), %eax<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-; X64: _crc32_16:<br></blockquote><blockquote type="cite">+; X64: _crc32_32_16:<br></blockquote><blockquote type="cite">; X64: crc32w %si,<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-define i32 @crc32_32(i32 %a, i32 %b) nounwind {<br></blockquote><blockquote type="cite">- %tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b)<br></blockquote><blockquote type="cite">+define i32 @crc32_32_32(i32 %a, i32 %b) nounwind {<br></blockquote><blockquote type="cite">+ %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b)<br></blockquote><blockquote type="cite"> ret i32 %tmp<br></blockquote><blockquote type="cite">-; X32: _crc32_32:<br></blockquote><blockquote type="cite">+; X32: _crc32_32_32:<br></blockquote><blockquote type="cite">; X32: crc32l 8(%esp), %eax<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-; X64: _crc32_32:<br></blockquote><blockquote type="cite">+; X64: _crc32_32_32:<br></blockquote><blockquote type="cite">; X64: crc32l %esi,<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Added: llvm/trunk/test/CodeGen/X86/sse42_64.ll<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42_64.ll?rev=132163&view=auto">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42_64.ll?rev=132163&view=auto</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/test/CodeGen/X86/sse42_64.ll (added)<br></blockquote><blockquote type="cite">+++ llvm/trunk/test/CodeGen/X86/sse42_64.ll Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -0,0 +1,21 @@<br></blockquote><blockquote type="cite">+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind<br></blockquote><blockquote type="cite">+declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {<br></blockquote><blockquote type="cite">+ %tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)<br></blockquote><blockquote type="cite">+ ret i64 %tmp<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+; X64: _crc32_64_8:<br></blockquote><blockquote type="cite">+; X64: crc32b %sil,<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+define i64 @crc32_64_64(i64 %a, i64 %b) nounwind {<br></blockquote><blockquote type="cite">+ %tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b)<br></blockquote><blockquote type="cite">+ ret i64 %tmp<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+; X64: _crc32_64_64:<br></blockquote><blockquote type="cite">+; X64: crc32q %rsi,<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/test/Transforms/InstCombine/x86-crc32-demanded.ll<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/x86-crc32-demanded.ll?rev=132163&r1=132162&r2=132163&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/x86-crc32-demanded.ll?rev=132163&r1=132162&r2=132163&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/test/Transforms/InstCombine/x86-crc32-demanded.ll (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/test/Transforms/InstCombine/x86-crc32-demanded.ll Thu May 26 18:13:19 2011<br></blockquote><blockquote type="cite">@@ -6,12 +6,12 @@<br></blockquote><blockquote type="cite">define i64 @test() nounwind {<br></blockquote><blockquote type="cite">entry:<br></blockquote><blockquote type="cite">; CHECK: test<br></blockquote><blockquote type="cite">-; CHECK: tail call i64 @llvm.x86.sse42.crc64.64<br></blockquote><blockquote type="cite">+; CHECK: tail call i64 @llvm.x86.sse42.crc32.64.64<br></blockquote><blockquote type="cite">; CHECK-NOT: and<br></blockquote><blockquote type="cite">; CHECK: ret<br></blockquote><blockquote type="cite">- %0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind<br></blockquote><blockquote type="cite">+ %0 = tail call i64 @llvm.x86.sse42.crc32.64.64(i64 0, i64 4) nounwind<br></blockquote><blockquote type="cite"> %1 = and i64 %0, 4294967295<br></blockquote><blockquote type="cite"> ret i64 %1<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone<br></blockquote><blockquote type="cite">+declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">_______________________________________________<br></blockquote><blockquote type="cite">llvm-commits mailing list<br></blockquote><blockquote type="cite"><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br></blockquote><blockquote type="cite"><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></blockquote><br></div></blockquote></div><br></div></body></html>