<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Bruno,<div><br></div><div>While I'm (partly) responsible for the current state of things, I'd really prefer it if we could find a way to do this using AsmOperandClass and ParserMatchClass declarations in the .td file rather than hacking the ASMParser for every symbolic operand type.</div><div><br></div><div>--Owen</div><div><br><div><div>On Jan 18, 2011, at 12:45 PM, Bruno Cardoso Lopes wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: bruno<br>Date: Tue Jan 18 14:45:56 2011<br>New Revision: 123770<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=123770&view=rev">http://llvm.org/viewvc/llvm-project?rev=123770&view=rev</a><br>Log:<br>Add support for parsing and encoding ARM's official syntax for the BFI instruction<br><br>Modified:<br> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp<br> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td<br> llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp<br> llvm/trunk/test/MC/ARM/arm_instructions.s<br> llvm/trunk/test/MC/ARM/thumb2.s<br> llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp<br> llvm/trunk/utils/TableGen/EDEmitter.cpp<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Jan 18 14:45:56 2011<br>@@ -225,6 +225,8 @@<br> const { return 0; }<br> unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,<br> unsigned Op) const { return 0; }<br>+ unsigned getMsbOpValue(const MachineInstr &MI,<br>+ unsigned Op) const { return 0; }<br> uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)<br> const {return 0; }<br> uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jan 18 14:45:56 2011<br>@@ -443,6 +443,18 @@<br> let PrintMethod = "printBitfieldInvMaskImmOperand";<br> }<br><br>+/// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p<br>+def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{<br>+ return isInt<5>(N->getSExtValue());<br>+}]>;<br>+<br>+/// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p<br>+def width_imm : Operand<i32>, PatLeaf<(imm), [{<br>+ return N->getSExtValue() > 0 && N->getSExtValue() <= 32;<br>+}] > {<br>+ let EncoderMethod = "getMsbOpValue";<br>+}<br>+<br> // Define ARM specific addressing modes.<br><br><br>@@ -2463,6 +2475,25 @@<br> let Inst{3-0} = Rn;<br> }<br><br>+// GNU as only supports this form of bfi (w/ 4 arguments)<br>+let isAsmParserOnly = 1 in<br>+def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,<br>+ lsb_pos_imm:$lsb, width_imm:$width),<br>+ AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,<br>+ "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",<br>+ []>, Requires<[IsARM, HasV6T2]> {<br>+ bits<4> Rd;<br>+ bits<4> Rn;<br>+ bits<5> lsb;<br>+ bits<5> width;<br>+ let Inst{27-21} = 0b0111110;<br>+ let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15<br>+ let Inst{15-12} = Rd;<br>+ let Inst{11-7} = lsb;<br>+ let Inst{20-16} = width; // Custom encoder => lsb+width-1<br>+ let Inst{3-0} = Rn;<br>+}<br>+<br> def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,<br> "mvn", "\t$Rd, $Rm",<br> [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jan 18 14:45:56 2011<br>@@ -2152,20 +2152,39 @@<br> }<br><br> // A8.6.18 BFI - Bitfield insert (Encoding T1)<br>-let Constraints = "$src = $Rd" in<br>-def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),<br>- (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),<br>- IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",<br>- [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,<br>- bf_inv_mask_imm:$imm))]> {<br>- let Inst{31-27} = 0b11110;<br>- let Inst{25} = 1;<br>- let Inst{24-20} = 0b10110;<br>- let Inst{15} = 0;<br>+let Constraints = "$src = $Rd" in {<br>+ def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),<br>+ (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),<br>+ IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",<br>+ [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,<br>+ bf_inv_mask_imm:$imm))]> {<br>+ let Inst{31-27} = 0b11110;<br>+ let Inst{25} = 1;<br>+ let Inst{24-20} = 0b10110;<br>+ let Inst{15} = 0;<br>+<br>+ bits<10> imm;<br>+ let msb{4-0} = imm{9-5};<br>+ let lsb{4-0} = imm{4-0};<br>+ }<br><br>- bits<10> imm;<br>- let msb{4-0} = imm{9-5};<br>- let lsb{4-0} = imm{4-0};<br>+ // GNU as only supports this form of bfi (w/ 4 arguments)<br>+ let isAsmParserOnly = 1 in<br>+ def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),<br>+ (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,<br>+ width_imm:$width),<br>+ IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",<br>+ []> {<br>+ let Inst{31-27} = 0b11110;<br>+ let Inst{25} = 1;<br>+ let Inst{24-20} = 0b10110;<br>+ let Inst{15} = 0;<br>+<br>+ bits<5> lsbit;<br>+ bits<5> width;<br>+ let msb{4-0} = width; // Custom encoder => lsb+width-1<br>+ let lsb{4-0} = lsbit;<br>+ }<br> }<br><br> defm t2ORN : T2I_bin_irs<0b0011, "orn",<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 18 14:45:56 2011<br>@@ -262,6 +262,9 @@<br> unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,<br> SmallVectorImpl<MCFixup> &Fixups) const;<br><br>+ unsigned getMsbOpValue(const MCInst &MI, unsigned Op,<br>+ SmallVectorImpl<MCFixup> &Fixups) const;<br>+<br> unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,<br> SmallVectorImpl<MCFixup> &Fixups) const;<br> unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,<br>@@ -1067,6 +1070,17 @@<br> }<br><br> unsigned ARMMCCodeEmitter::<br>+getMsbOpValue(const MCInst &MI, unsigned Op,<br>+ SmallVectorImpl<MCFixup> &Fixups) const {<br>+ // MSB - 5 bits.<br>+ uint32_t lsb = MI.getOperand(Op-1).getImm();<br>+ uint32_t width = MI.getOperand(Op).getImm();<br>+ uint32_t msb = lsb+width-1;<br>+ assert (width != 0 && msb < 32 && "Illegal bit width!");<br>+ return msb;<br>+}<br>+<br>+unsigned ARMMCCodeEmitter::<br> getRegisterListOpValue(const MCInst &MI, unsigned Op,<br> SmallVectorImpl<MCFixup> &Fixups) const {<br> // VLDM/VSTM:<br><br>Modified: llvm/trunk/test/MC/ARM/arm_instructions.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)<br>+++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Jan 18 14:45:56 2011<br>@@ -124,3 +124,6 @@<br> @ may depend on flags.<br> @ CHECK-FIXME:: mlas<span class="Apple-tab-span" style="white-space:pre"> </span>r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0]<br> @ mlas r1,r2,r3,r4<br>+<br>+@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7]<br>+ bfi r0, r0, #5, #7<br><br>Modified: llvm/trunk/test/MC/ARM/thumb2.s<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/MC/ARM/thumb2.s (original)<br>+++ llvm/trunk/test/MC/ARM/thumb2.s Tue Jan 18 14:45:56 2011<br>@@ -162,3 +162,6 @@<br> ldrsb.w<span class="Apple-tab-span" style="white-space:pre"> </span>r0, [r0]<br> @ CHECK: ldrsh.w<span class="Apple-tab-span" style="white-space:pre"> </span>r0, [r0] @ encoding: [0x00,0x00,0xb0,0xf9]<br> ldrsh.w<span class="Apple-tab-span" style="white-space:pre"> </span>r0, [r0]<br>+@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x60,0xf3,0x4b,0x10]<br>+ bfi r0, r0, #5, #7<br>+<br><br>Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)<br>+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Tue Jan 18 14:45:56 2011<br>@@ -1560,6 +1560,10 @@<br> // which is a better design and less fragile than the name matchings.<br> if (Bits.allInComplete()) return false;<br><br>+ // Ignore "asm parser only" instructions.<br>+ if (Def.getValueAsBit("isAsmParserOnly"))<br>+ return false;<br>+<br> if (TN == TARGET_ARM) {<br> // FIXME: what about Int_MemBarrierV6 and Int_SyncBarrierV6?<br> if ((Name != "Int_MemBarrierV7" && Name != "Int_SyncBarrierV7") &&<br><br>Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=123770&r1=123769&r2=123770&view=diff</a><br>==============================================================================<br>--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)<br>+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Jan 18 14:45:56 2011<br>@@ -566,6 +566,8 @@<br> IMM("i32imm");<br> IMM("i32imm_hilo16");<br> IMM("bf_inv_mask_imm");<br>+ IMM("lsb_pos_imm");<br>+ IMM("width_imm");<br> IMM("jtblock_operand");<br> IMM("nohash_imm");<br> IMM("p_imm");<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>