<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><div>On Dec 9, 2010, at 12:27 PM, Owen Anderson wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: resistor<br>Date: Thu Dec 9 14:27:52 2010<br>New Revision: 121408<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121408&r1=121407&r2=121408&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121408&r1=121407&r2=121408&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Dec 9 14:27:52 2010<br>@@ -100,10 +100,10 @@<br> }<br> case ARM::fixup_arm_ldst_pcrel_12:<br> // ARM PC-relative values are offset by 8.<br>- Value -= 6;<br>+ Value -= 4;<br></div></blockquote><div><br></div>Could you put a FALLTHROUGH comment here?</div><div><br></div><div>-bw</div><div><br><blockquote type="cite"><div> case ARM::fixup_t2_ldst_pcrel_12: {<br> // Offset by 4, adjusted by two due to the half-word ordering of thumb.<br>- Value -= 2;<br>+ Value -= 4;<br> bool isAdd = true;<br> if ((int64_t)Value < 0) {<br> Value = -Value;<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121408&r1=121407&r2=121408&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121408&r1=121407&r2=121408&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Dec 9 14:27:52 2010<br>@@ -47,7 +47,8 @@<br> const static MCFixupKindInfo Infos[] = {<br> // name off bits flags<br> { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },<br>- { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel },<br>+ { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |<br>+ MCFixupKindInfo::FKF_IsAligned},<br> { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },<br> { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel },<br> { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></body></html>