<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Nov 5, 2010, at 2:39 PM, Owen Anderson wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Nov 5, 2010, at 2:35 PM, Bob Wilson wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>This looks good. You're still going to fix isNEONModifiedImm to distinguish VBIC/VORR, right?<font class="Apple-style-span"><font class="Apple-style-span" color="#144FAE"><br></font></font></div></blockquote><div><br></div><div>I'm not sure it needs to. There seem to be only two cases: all types allowed (isVMOV == true) and only i16 and i32 allows (isVMOV == false). Are there other modified immediate instructions that have some different type combination they allow?</div></div></div></blockquote><div><br></div><div>See my comments on your previous patch:</div><a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101101/111110.html">http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101101/111110.html</a></div><div><br></div><div>The encodings with cmode=1100 and 1101 are not supported for VORR and VBIC.</div><div><br><blockquote type="cite"><div style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div><div><br></div><div>--Owen</div><br><blockquote type="cite"><div>On Nov 5, 2010, at 12:27 PM, Owen Anderson wrote:<br><br><blockquote type="cite">Author: resistor<br></blockquote><blockquote type="cite">Date: Fri Nov 5 14:27:46 2010<br></blockquote><blockquote type="cite">New Revision: 118291<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=118291&view=rev">http://llvm.org/viewvc/llvm-project?rev=118291&view=rev</a><br></blockquote><blockquote type="cite">Log:<br></blockquote><blockquote type="cite">Add codegen and encoding support for the immediate form of vbic.<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified:<br></blockquote><blockquote type="cite"> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br></blockquote><blockquote type="cite"> llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br></blockquote><blockquote type="cite"> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td<br></blockquote><blockquote type="cite"> llvm/trunk/test/CodeGen/ARM/vbits.ll<br></blockquote><blockquote type="cite"> llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 14:27:46 2010<br></blockquote><blockquote type="cite">@@ -673,8 +673,10 @@<br></blockquote><blockquote type="cite"> setTargetDAGCombine(ISD::SUB);<br></blockquote><blockquote type="cite"> setTargetDAGCombine(ISD::MUL);<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">- if (Subtarget->hasV6T2Ops())<br></blockquote><blockquote type="cite">+ if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())<br></blockquote><blockquote type="cite"> setTargetDAGCombine(ISD::OR);<br></blockquote><blockquote type="cite">+ if (Subtarget->hasNEON())<br></blockquote><blockquote type="cite">+ setTargetDAGCombine(ISD::AND);<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> setStackPointerRegisterToSaveRestore(ARM::SP);<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">@@ -4443,6 +4445,36 @@<br></blockquote><blockquote type="cite"> return SDValue();<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">+static SDValue PerformANDCombine(SDNode *N,<br></blockquote><blockquote type="cite">+ TargetLowering::DAGCombinerInfo &DCI) {<br></blockquote><blockquote type="cite">+ // Attempt to use immediate-form VBIC<br></blockquote><blockquote type="cite">+ BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));<br></blockquote><blockquote type="cite">+ DebugLoc dl = N->getDebugLoc();<br></blockquote><blockquote type="cite">+ EVT VT = N->getValueType(0);<br></blockquote><blockquote type="cite">+ SelectionDAG &DAG = DCI.DAG;<br></blockquote><blockquote type="cite">+ <br></blockquote><blockquote type="cite">+ APInt SplatBits, SplatUndef;<br></blockquote><blockquote type="cite">+ unsigned SplatBitSize;<br></blockquote><blockquote type="cite">+ bool HasAnyUndefs;<br></blockquote><blockquote type="cite">+ if (BVN &&<br></blockquote><blockquote type="cite">+ BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {<br></blockquote><blockquote type="cite">+ if (SplatBitSize <= 64) {<br></blockquote><blockquote type="cite">+ EVT VbicVT;<br></blockquote><blockquote type="cite">+ SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),<br></blockquote><blockquote type="cite">+ SplatUndef.getZExtValue(), SplatBitSize,<br></blockquote><blockquote type="cite">+ DAG, VbicVT, VT.is128BitVector(), false);<br></blockquote><blockquote type="cite">+ if (Val.getNode()) {<br></blockquote><blockquote type="cite">+ SDValue Input =<br></blockquote><blockquote type="cite">+ DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0));<br></blockquote><blockquote type="cite">+ SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);<br></blockquote><blockquote type="cite">+ return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic);<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ }<br></blockquote><blockquote type="cite">+ <br></blockquote><blockquote type="cite">+ return SDValue();<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">/// PerformORCombine - Target-specific dag combine xforms for ISD::OR<br></blockquote><blockquote type="cite">static SDValue PerformORCombine(SDNode *N,<br></blockquote><blockquote type="cite"> TargetLowering::DAGCombinerInfo &DCI,<br></blockquote><blockquote type="cite">@@ -5066,6 +5098,7 @@<br></blockquote><blockquote type="cite"> case ISD::SUB: return PerformSUBCombine(N, DCI);<br></blockquote><blockquote type="cite"> case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);<br></blockquote><blockquote type="cite"> case ISD::OR: return PerformORCombine(N, DCI, Subtarget);<br></blockquote><blockquote type="cite">+ case ISD::AND: return PerformANDCombine(N, DCI);<br></blockquote><blockquote type="cite"> case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);<br></blockquote><blockquote type="cite"> case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);<br></blockquote><blockquote type="cite"> case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 14:27:46 2010<br></blockquote><blockquote type="cite">@@ -165,7 +165,9 @@<br></blockquote><blockquote type="cite"> BFI,<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> // Vector OR with immediate<br></blockquote><blockquote type="cite">- VORRIMM<br></blockquote><blockquote type="cite">+ VORRIMM,<br></blockquote><blockquote type="cite">+ // Vector AND with NOT of immediate<br></blockquote><blockquote type="cite">+ VBICIMM<br></blockquote><blockquote type="cite"> };<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Nov 5 14:27:46 2010<br></blockquote><blockquote type="cite">@@ -72,6 +72,7 @@<br></blockquote><blockquote type="cite">def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,<br></blockquote><blockquote type="cite"> SDTCisVT<2, i32>]>;<br></blockquote><blockquote type="cite">def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;<br></blockquote><blockquote type="cite">+def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">@@ -3308,13 +3309,13 @@<br></blockquote><blockquote type="cite"> let Inst{9} = SIMM{9};<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1,<br></blockquote><blockquote type="cite">+def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,<br></blockquote><blockquote type="cite"> (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),<br></blockquote><blockquote type="cite"> IIC_VMOVImm,<br></blockquote><blockquote type="cite"> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",<br></blockquote><blockquote type="cite"> [(set DPR:$Vd,<br></blockquote><blockquote type="cite"> (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {<br></blockquote><blockquote type="cite">- let Inst{11-9} = SIMM{11-9};<br></blockquote><blockquote type="cite">+ let Inst{10-9} = SIMM{10-9};<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,<br></blockquote><blockquote type="cite">@@ -3326,13 +3327,13 @@<br></blockquote><blockquote type="cite"> let Inst{9} = SIMM{9};<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">-def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1,<br></blockquote><blockquote type="cite">+def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,<br></blockquote><blockquote type="cite"> (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),<br></blockquote><blockquote type="cite"> IIC_VMOVImm,<br></blockquote><blockquote type="cite"> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",<br></blockquote><blockquote type="cite"> [(set QPR:$Vd,<br></blockquote><blockquote type="cite"> (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {<br></blockquote><blockquote type="cite">- let Inst{11-9} = SIMM{11-9};<br></blockquote><blockquote type="cite">+ let Inst{10-9} = SIMM{10-9};<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">@@ -3348,6 +3349,42 @@<br></blockquote><blockquote type="cite"> [(set QPR:$dst, (v4i32 (and QPR:$src1,<br></blockquote><blockquote type="cite"> (vnotq QPR:$src2))))]>;<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">+def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,<br></blockquote><blockquote type="cite">+ (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),<br></blockquote><blockquote type="cite">+ IIC_VMOVImm,<br></blockquote><blockquote type="cite">+ "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",<br></blockquote><blockquote type="cite">+ [(set DPR:$Vd,<br></blockquote><blockquote type="cite">+ (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {<br></blockquote><blockquote type="cite">+ let Inst{9} = SIMM{9};<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,<br></blockquote><blockquote type="cite">+ (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),<br></blockquote><blockquote type="cite">+ IIC_VMOVImm,<br></blockquote><blockquote type="cite">+ "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",<br></blockquote><blockquote type="cite">+ [(set DPR:$Vd,<br></blockquote><blockquote type="cite">+ (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {<br></blockquote><blockquote type="cite">+ let Inst{10-9} = SIMM{10-9};<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,<br></blockquote><blockquote type="cite">+ (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),<br></blockquote><blockquote type="cite">+ IIC_VMOVImm,<br></blockquote><blockquote type="cite">+ "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",<br></blockquote><blockquote type="cite">+ [(set QPR:$Vd,<br></blockquote><blockquote type="cite">+ (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {<br></blockquote><blockquote type="cite">+ let Inst{9} = SIMM{9};<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,<br></blockquote><blockquote type="cite">+ (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),<br></blockquote><blockquote type="cite">+ IIC_VMOVImm,<br></blockquote><blockquote type="cite">+ "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",<br></blockquote><blockquote type="cite">+ [(set QPR:$Vd,<br></blockquote><blockquote type="cite">+ (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {<br></blockquote><blockquote type="cite">+ let Inst{10-9} = SIMM{10-9};<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">// VORN : Vector Bitwise OR NOT<br></blockquote><blockquote type="cite">def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),<br></blockquote><blockquote type="cite"> (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/test/CodeGen/ARM/vbits.ll (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/test/CodeGen/ARM/vbits.ll Fri Nov 5 14:27:46 2010<br></blockquote><blockquote type="cite">@@ -525,3 +525,23 @@<br></blockquote><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1><br></blockquote><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>ret <16 x i8> %tmp3<br></blockquote><blockquote type="cite">}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {<br></blockquote><blockquote type="cite">+; CHECK: v_bicimm:<br></blockquote><blockquote type="cite">+; CHECK-NOT: vmov<br></blockquote><blockquote type="cite">+; CHECK-NOT vmvn<br></blockquote><blockquote type="cite">+; CHECK: vbic<br></blockquote><blockquote type="cite">+<span class="Apple-tab-span" style="white-space:pre"> </span>%tmp1 = load <8 x i8>* %A<br></blockquote><blockquote type="cite">+<span class="Apple-tab-span" style="white-space:pre"> </span>%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 ><br></blockquote><blockquote type="cite">+<span class="Apple-tab-span" style="white-space:pre"> </span>ret <8 x i8> %tmp3<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite">+<br></blockquote><blockquote type="cite">+define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {<br></blockquote><blockquote type="cite">+; CHECK: v_bicimmQ:<br></blockquote><blockquote type="cite">+; CHECK-NOT: vmov<br></blockquote><blockquote type="cite">+; CHECK-NOT: vmvn<br></blockquote><blockquote type="cite">+; CHECK: vbic<br></blockquote><blockquote type="cite">+<span class="Apple-tab-span" style="white-space:pre"> </span>%tmp1 = load <16 x i8>* %A<br></blockquote><blockquote type="cite">+<span class="Apple-tab-span" style="white-space:pre"> </span>%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 ><br></blockquote><blockquote type="cite">+<span class="Apple-tab-span" style="white-space:pre"> </span>ret <16 x i8> %tmp3<br></blockquote><blockquote type="cite">+}<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Fri Nov 5 14:27:46 2010<br></blockquote><blockquote type="cite">@@ -26,6 +26,10 @@<br></blockquote><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>vbic<span class="Apple-tab-span" style="white-space:pre"> </span>d16, d17, d16<br></blockquote><blockquote type="cite">@ CHECK: vbic<span class="Apple-tab-span" style="white-space:pre"> </span>q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2]<br></blockquote><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>vbic<span class="Apple-tab-span" style="white-space:pre"> </span>q8, q8, q9<br></blockquote><blockquote type="cite">+@ CHECK: vbic.i32<span class="Apple-tab-span" style="white-space:pre"> </span>d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3]<br></blockquote><blockquote type="cite">+ vbic.i32<span class="Apple-tab-span" style="white-space:pre"> </span>d16, #0xFF000000<br></blockquote><blockquote type="cite">+@ CHECK: vbic.i32<span class="Apple-tab-span" style="white-space:pre"> </span>q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3]<br></blockquote><blockquote type="cite">+ vbic.i32<span class="Apple-tab-span" style="white-space:pre"> </span>q8, #0xFF000000<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">@ CHECK: vorn<span class="Apple-tab-span" style="white-space:pre"> </span>d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2]<br></blockquote><blockquote type="cite"><span class="Apple-tab-span" style="white-space:pre"> </span>vorn<span class="Apple-tab-span" style="white-space:pre"> </span>d16, d17, d16<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">_______________________________________________<br></blockquote><blockquote type="cite">llvm-commits mailing list<br></blockquote><blockquote type="cite"><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br></blockquote><blockquote type="cite"><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></blockquote><br></div></blockquote></div><br></div></blockquote></div><br></body></html>