<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Sorry, I didn't notice those. Fixed in svn 117511.<div><br><div><div>On Oct 27, 2010, at 4:42 PM, Evan Cheng wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><div>Compiler warnings.</div><div>ARMISelLowering.cpp:4578:17: warning: comparison of integers of different signs: 'int' and 'unsigned int' [-Wsign-compare]</div><div> if (MaskElt < HalfElts)</div><div> ~~~~~~~ ^ ~~~~~~~~</div><div>ARMISelLowering.cpp:4580:22: warning: comparison of integers of different signs: 'int' and 'unsigned int' [-Wsign-compare]</div><div> else if (MaskElt >= NumElts && MaskElt < NumElts + HalfElts)</div><div> ~~~~~~~ ^ ~~~~~~~</div><div>ARMISelLowering.cpp:4580:44: warning: comparison of integers of different signs: 'int' and 'unsigned int' [-Wsign-compare]</div><div> else if (MaskElt >= NumElts && MaskElt < NumElts + HalfElts)</div><div><br></div><div>Evan</div><div><br></div><div><div>On Oct 27, 2010, at 1:38 PM, Bob Wilson wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Author: bwilson<br>Date: Wed Oct 27 15:38:28 2010<br>New Revision: 117482<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=117482&view=rev">http://llvm.org/viewvc/llvm-project?rev=117482&view=rev</a><br>Log:<br>SelectionDAG shuffle nodes do not allow operands with different numbers of<br>elements than the result vector type. So, when an instruction like:<br><br>%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2><br><br>is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is:<br><br>shuffle [a,b], [c,d] is changed to:<br>shuffle [a,b,u,u], [c,d,u,u]<br><br>That's probably the right thing for x86 but for NEON, we'd much rather have:<br><br>shuffle [a,b,c,d], undef<br><br>Teach the DAG combiner how to do that transformation for ARM. Radar 8597007.<br><br>Modified:<br> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br> llvm/trunk/test/CodeGen/ARM/vrev.ll<br><br>Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=117482&r1=117481&r2=117482&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=117482&r1=117481&r2=117482&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Oct 27 15:38:28 2010<br>@@ -460,6 +460,7 @@<br> setTargetDAGCombine(ISD::ANY_EXTEND);<br> setTargetDAGCombine(ISD::SELECT_CC);<br> setTargetDAGCombine(ISD::BUILD_VECTOR);<br>+ setTargetDAGCombine(ISD::VECTOR_SHUFFLE);<br> }<br><br> computeRegisterProperties();<br>@@ -4531,6 +4532,59 @@<br> return SDValue();<br> }<br><br>+/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for<br>+/// ISD::VECTOR_SHUFFLE.<br>+static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {<br>+ // The LLVM shufflevector instruction does not require the shuffle mask<br>+ // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does<br>+ // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the<br>+ // operands do not match the mask length, they are extended by concatenating<br>+ // them with undef vectors. That is probably the right thing for other<br>+ // targets, but for NEON it is better to concatenate two double-register<br>+ // size vector operands into a single quad-register size vector. Do that<br>+ // transformation here:<br>+ // shuffle(concat(v1, undef), concat(v2, undef)) -><br>+ // shuffle(concat(v1, v2), undef)<br>+ SDValue Op0 = N->getOperand(0);<br>+ SDValue Op1 = N->getOperand(1);<br>+ if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||<br>+ Op1.getOpcode() != ISD::CONCAT_VECTORS ||<br>+ Op0.getNumOperands() != 2 ||<br>+ Op1.getNumOperands() != 2)<br>+ return SDValue();<br>+ SDValue Concat0Op1 = Op0.getOperand(1);<br>+ SDValue Concat1Op1 = Op1.getOperand(1);<br>+ if (Concat0Op1.getOpcode() != ISD::UNDEF ||<br>+ Concat1Op1.getOpcode() != ISD::UNDEF)<br>+ return SDValue();<br>+ // Skip the transformation if any of the types are illegal.<br>+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>+ EVT VT = N->getValueType(0);<br>+ if (!TLI.isTypeLegal(VT) ||<br>+ !TLI.isTypeLegal(Concat0Op1.getValueType()) ||<br>+ !TLI.isTypeLegal(Concat1Op1.getValueType()))<br>+ return SDValue();<br>+<br>+ SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,<br>+ Op0.getOperand(0), Op1.getOperand(0));<br>+ // Translate the shuffle mask.<br>+ SmallVector<int, 16> NewMask;<br>+ unsigned NumElts = VT.getVectorNumElements();<br>+ unsigned HalfElts = NumElts/2;<br>+ ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);<br>+ for (unsigned n = 0; n < NumElts; ++n) {<br>+ int MaskElt = SVN->getMaskElt(n);<br>+ int NewElt = -1;<br>+ if (MaskElt < HalfElts)<br>+ NewElt = MaskElt;<br>+ else if (MaskElt >= NumElts && MaskElt < NumElts + HalfElts)<br>+ NewElt = HalfElts + MaskElt - NumElts;<br>+ NewMask.push_back(NewElt);<br>+ }<br>+ return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,<br>+ DAG.getUNDEF(VT), NewMask.data());<br>+}<br>+<br> /// PerformVDUPLANECombine - Target-specific dag combine xforms for<br> /// ARMISD::VDUPLANE.<br> static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {<br>@@ -4939,6 +4993,7 @@<br> case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);<br> case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);<br> case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);<br>+ case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);<br> case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);<br> case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);<br> case ISD::SHL:<br><br>Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=117482&r1=117481&r2=117482&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=117482&r1=117481&r2=117482&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/ARM/vrev.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM/vrev.ll Wed Oct 27 15:38:28 2010<br>@@ -129,3 +129,21 @@<br> <span class="Apple-tab-span" style="white-space:pre"> </span>%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef><br> <span class="Apple-tab-span" style="white-space:pre"> </span>ret <8 x i16> %tmp2<br> }<br>+<br>+; A vcombine feeding a VREV should not obscure things. Radar 8597007.<br>+<br>+define void @test_with_vcombine(<4 x float>* %v) nounwind {<br>+;CHECK: test_with_vcombine:<br>+;CHECK-NOT: vext<br>+;CHECK: vrev64.32<br>+ %tmp1 = load <4 x float>* %v, align 16<br>+ %tmp2 = bitcast <4 x float> %tmp1 to <2 x double><br>+ %tmp3 = extractelement <2 x double> %tmp2, i32 0<br>+ %tmp4 = bitcast double %tmp3 to <2 x float><br>+ %tmp5 = extractelement <2 x double> %tmp2, i32 1<br>+ %tmp6 = bitcast double %tmp5 to <2 x float><br>+ %tmp7 = fadd <2 x float> %tmp6, %tmp6<br>+ %tmp8 = shufflevector <2 x float> %tmp4, <2 x float> %tmp7, <4 x i32> <i32 1, i32 0, i32 3, i32 2><br>+ store <4 x float> %tmp8, <4 x float>* %v, align 16<br>+ ret void<br>+}<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></div></blockquote></div><br></div></blockquote></div><br></div></body></html>