<html><head></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">Houston, we have lift-off.<div><br></div><div><span class="Apple-style-span" style="font-family: Verdana, Cursor; font-size: 10px; font-weight: bold; "><font size="-1">(Sep 03 14:53)</font> rev=[113016] <span class="success" style="color: rgb(255, 255, 255); background-color: rgb(143, 223, 95); border-top-color: rgb(79, 133, 48); border-right-color: rgb(79, 133, 48); border-bottom-color: rgb(79, 133, 48); border-left-color: rgb(79, 133, 48); ">success</span> <a href="http://smooshlab.apple.com:8010/builders/llvm-gcc-powerpc-darwin9/builds/3868" style="color: rgb(68, 68, 68); ">#3868</a>: build successful</span><br><div><br><div><div>On Sep 3, 2010, at 3:04 PM, Dale Johannesen wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div>Jim believes this will fix the PPC buildbot. I've started a run, ETA around 5 PM (Pacific).<br><br>On Sep 3, 2010, at 2:45 PMPDT, Jim Grosbach wrote:<br><br><blockquote type="cite">Author: grosbach<br></blockquote><blockquote type="cite">Date: Fri Sep 3 16:45:15 2010<br></blockquote><blockquote type="cite">New Revision: 113016<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=113016&view=rev">http://llvm.org/viewvc/llvm-project?rev=113016&view=rev</a><br></blockquote><blockquote type="cite">Log:<br></blockquote><blockquote type="cite">previous patch was a little too tricky for its own good. Don't try to<br></blockquote><blockquote type="cite">overload UserInInstr. Explicitly check Allocatable. The early exit in the<br></blockquote><blockquote type="cite">condition will mean the performance impact of the extra test should be<br></blockquote><blockquote type="cite">minimal.<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified:<br></blockquote><blockquote type="cite"> llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br></blockquote><blockquote type="cite">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=113016&r1=113015&r2=113016&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=113016&r1=113015&r2=113016&view=diff</a><br></blockquote><blockquote type="cite">==============================================================================<br></blockquote><blockquote type="cite">--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)<br></blockquote><blockquote type="cite">+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri Sep 3 16:45:15 2010<br></blockquote><blockquote type="cite">@@ -113,9 +113,6 @@<br></blockquote><blockquote type="cite"> // Allocatable - vector of allocatable physical registers.<br></blockquote><blockquote type="cite"> BitVector Allocatable;<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">- // Reserved - vector of reserved physical registers.<br></blockquote><blockquote type="cite">- BitVector Reserved;<br></blockquote><blockquote type="cite">-<br></blockquote><blockquote type="cite"> // SkippedInstrs - Descriptors of instructions whose clobber list was<br></blockquote><blockquote type="cite"> // ignored because all registers were spilled. It is still necessary to<br></blockquote><blockquote type="cite"> // mark all the clobbered registers as used by the function.<br></blockquote><blockquote type="cite">@@ -501,7 +498,8 @@<br></blockquote><blockquote type="cite"> // First try to find a completely free register.<br></blockquote><blockquote type="cite"> for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {<br></blockquote><blockquote type="cite"> unsigned PhysReg = *I;<br></blockquote><blockquote type="cite">- if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))<br></blockquote><blockquote type="cite">+ if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) &&<br></blockquote><blockquote type="cite">+ Allocatable.test(PhysReg))<br></blockquote><blockquote type="cite"> return assignVirtToPhysReg(LRE, PhysReg);<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">@@ -510,6 +508,8 @@<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> unsigned BestReg = 0, BestCost = spillImpossible;<br></blockquote><blockquote type="cite"> for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {<br></blockquote><blockquote type="cite">+ if (!Allocatable.test(*I))<br></blockquote><blockquote type="cite">+ continue;<br></blockquote><blockquote type="cite"> unsigned Cost = calcSpillCost(*I);<br></blockquote><blockquote type="cite"> // Cost is 0 when all aliases are already disabled.<br></blockquote><blockquote type="cite"> if (Cost == 0)<br></blockquote><blockquote type="cite">@@ -712,7 +712,7 @@<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> // Restore UsedInInstr to a state usable for allocating normal virtual uses.<br></blockquote><blockquote type="cite">- UsedInInstr = Reserved;<br></blockquote><blockquote type="cite">+ UsedInInstr.reset();<br></blockquote><blockquote type="cite"> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br></blockquote><blockquote type="cite"> MachineOperand &MO = MI->getOperand(i);<br></blockquote><blockquote type="cite"> if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;<br></blockquote><blockquote type="cite">@@ -838,7 +838,7 @@<br></blockquote><blockquote type="cite"> }<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> // Track registers used by instruction.<br></blockquote><blockquote type="cite">- UsedInInstr = Reserved;<br></blockquote><blockquote type="cite">+ UsedInInstr.reset();<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> // First scan.<br></blockquote><blockquote type="cite"> // Mark physreg uses and early clobbers as used.<br></blockquote><blockquote type="cite">@@ -916,7 +916,7 @@<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> // Track registers defined by instruction - early clobbers and tied uses at<br></blockquote><blockquote type="cite"> // this point.<br></blockquote><blockquote type="cite">- UsedInInstr = Reserved;<br></blockquote><blockquote type="cite">+ UsedInInstr.reset();<br></blockquote><blockquote type="cite"> if (hasEarlyClobbers) {<br></blockquote><blockquote type="cite"> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {<br></blockquote><blockquote type="cite"> MachineOperand &MO = MI->getOperand(i);<br></blockquote><blockquote type="cite">@@ -1014,7 +1014,6 @@<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> UsedInInstr.resize(TRI->getNumRegs());<br></blockquote><blockquote type="cite"> Allocatable = TRI->getAllocatableSet(*MF);<br></blockquote><blockquote type="cite">- Reserved = TRI->getReservedRegs(*MF);<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"> // initialize the virtual->physical register map to have a 'null'<br></blockquote><blockquote type="cite"> // mapping for all virtual registers<br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite"><br></blockquote><blockquote type="cite">_______________________________________________<br></blockquote><blockquote type="cite">llvm-commits mailing list<br></blockquote><blockquote type="cite"><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br></blockquote><blockquote type="cite"><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br></blockquote><br></div></blockquote></div><br></div></div></body></html>