This appears to be causing failures on linux? See<div><a href="http://google1.osuosl.org:8011/builders/llvm-x86_64-linux/builds/186">http://google1.osuosl.org:8011/builders/llvm-x86_64-linux/builds/186</a></div><div>and</div>
<div><a href="http://google1.osuosl.org:8011/builders/llvm-i686-linux/builds/85">http://google1.osuosl.org:8011/builders/llvm-i686-linux/builds/85</a></div><div><br></div><div> - Daniel<br><br><div class="gmail_quote">On Fri, Nov 7, 2008 at 2:54 PM, Dale Johannesen <span dir="ltr"><<a href="mailto:dalej@apple.com">dalej@apple.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Author: johannes<br>
Date: Fri Nov 7 16:54:33 2008<br>
New Revision: 58871<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=58871&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=58871&view=rev</a><br>
Log:<br>
Make FP tests requiring two compares work on PPC (PR 642).<br>
This is Chris' patch from the PR, modified to realize that<br>
SETUGT/SETULT occur legitimately with integers, plus<br>
two fixes in LegalizeDAG to pass a valid result type into<br>
LegalizeSetCC. The argument of TLI.getSetCCResultType is<br>
ignored on PPC, but I think I'm following usage elsewhere.<br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=58871&r1=58870&r2=58871&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=58871&r1=58870&r2=58871&view=diff</a><br>
<br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Nov 7 16:54:33 2008<br>
@@ -2008,7 +2008,7 @@<br>
Tmp3 = Node->getOperand(3); // RHS<br>
Tmp4 = Node->getOperand(1); // CC<br>
<br>
- LegalizeSetCC(Node->getValueType(0), Tmp2, Tmp3, Tmp4);<br>
+ LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);<br>
LastCALLSEQ_END = DAG.getEntryNode();<br>
<br>
// If we didn't get both a LHS and RHS back from LegalizeSetCC,<br>
@@ -2910,7 +2910,7 @@<br>
Tmp4 = LegalizeOp(Node->getOperand(3)); // False<br>
SDValue CC = Node->getOperand(4);<br>
<br>
- LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, CC);<br>
+ LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);<br>
<br>
// If we didn't get both a LHS and RHS back from LegalizeSetCC,<br>
// the LHS is a legal SETCC itself. In this case, we need to compare<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=58871&r1=58870&r2=58871&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=58871&r1=58870&r2=58871&view=diff</a><br>
<br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Nov 7 16:54:33 2008<br>
@@ -587,28 +587,29 @@<br>
<br>
static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {<br>
switch (CC) {<br>
- default: assert(0 && "Unknown condition!"); abort();<br>
- case ISD::SETOEQ: // FIXME: This is incorrect see PR642.<br>
case ISD::SETUEQ:<br>
+ case ISD::SETONE:<br>
+ case ISD::SETOLE:<br>
+ case ISD::SETOGE:<br>
+ assert(0 && "Should be lowered by legalize!");<br>
+ default: assert(0 && "Unknown condition!"); abort();<br>
+ case ISD::SETOEQ:<br>
case ISD::SETEQ: return PPC::PRED_EQ;<br>
- case ISD::SETONE: // FIXME: This is incorrect see PR642.<br>
case ISD::SETUNE:<br>
case ISD::SETNE: return PPC::PRED_NE;<br>
- case ISD::SETOLT: // FIXME: This is incorrect see PR642.<br>
- case ISD::SETULT:<br>
+ case ISD::SETOLT:<br>
case ISD::SETLT: return PPC::PRED_LT;<br>
- case ISD::SETOLE: // FIXME: This is incorrect see PR642.<br>
case ISD::SETULE:<br>
case ISD::SETLE: return PPC::PRED_LE;<br>
- case ISD::SETOGT: // FIXME: This is incorrect see PR642.<br>
- case ISD::SETUGT:<br>
+ case ISD::SETOGT:<br>
case ISD::SETGT: return PPC::PRED_GT;<br>
- case ISD::SETOGE: // FIXME: This is incorrect see PR642.<br>
case ISD::SETUGE:<br>
case ISD::SETGE: return PPC::PRED_GE;<br>
-<br>
case ISD::SETO: return PPC::PRED_NU;<br>
case ISD::SETUO: return PPC::PRED_UN;<br>
+ // These two are invalid for floating point. Assume we have int.<br>
+ case ISD::SETULT: return PPC::PRED_LT;<br>
+ case ISD::SETUGT: return PPC::PRED_GT;<br>
}<br>
}<br>
<br>
@@ -637,12 +638,14 @@<br>
case ISD::SETUNE:<br>
case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE<br>
case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO<br>
- case ISD::SETULT: Other = 0; return 3; // SETOLT | SETUO<br>
- case ISD::SETUGT: Other = 1; return 3; // SETOGT | SETUO<br>
- case ISD::SETUEQ: Other = 2; return 3; // SETOEQ | SETUO<br>
- case ISD::SETOGE: Other = 1; return 2; // SETOGT | SETOEQ<br>
- case ISD::SETOLE: Other = 0; return 2; // SETOLT | SETOEQ<br>
- case ISD::SETONE: Other = 0; return 1; // SETOLT | SETOGT<br>
+ case ISD::SETUEQ:<br>
+ case ISD::SETOGE:<br>
+ case ISD::SETOLE:<br>
+ case ISD::SETONE:<br>
+ assert(0 && "Invalid branch code: should be expanded by legalize");<br>
+ // These are invalid for floating point. Assume integer.<br>
+ case ISD::SETULT: return 0;<br>
+ case ISD::SETUGT: return 1;<br>
}<br>
return 0;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=58871&r1=58870&r2=58871&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=58871&r1=58870&r2=58871&view=diff</a><br>
<br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 7 16:54:33 2008<br>
@@ -209,6 +209,20 @@<br>
// We want to custom lower some of our intrinsics.<br>
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);<br>
<br>
+ // Comparisons that require checking two conditions.<br>
+ setCondCodeAction(ISD::SETULT, MVT::f32, Expand);<br>
+ setCondCodeAction(ISD::SETULT, MVT::f64, Expand);<br>
+ setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);<br>
+ setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);<br>
+ setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);<br>
+ setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);<br>
+ setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);<br>
+ setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);<br>
+ setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);<br>
+ setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);<br>
+ setCondCodeAction(ISD::SETONE, MVT::f32, Expand);<br>
+ setCondCodeAction(ISD::SETONE, MVT::f64, Expand);<br>
+<br>
if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {<br>
// They also have instructions for converting between i64 and fp.<br>
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);<br>
<br>
<br>
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</blockquote></div><br></div>