<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; ">
<div></div><div>Very good progress. Thanks!</div><div><br class="webkit-block-placeholder"></div><div>Comments inline.</div><div><br class="webkit-block-placeholder"></div><div>Evan</div><div><br><br><blockquote type="cite"><div>Index: lib/Target/ARM/ARMJITInfo.cpp</div><div>===================================================================</div><div>--- lib/Target/ARM/ARMJITInfo.cpp<span class="Apple-tab-span" style="white-space:pre"> </span>(revisão 41124)</div><div>+++ lib/Target/ARM/ARMJITInfo.cpp<span class="Apple-tab-span" style="white-space:pre"> </span>(cópia de trabalho)</div><div>@@ -21,12 +21,7 @@</div><div> using namespace llvm;</div><div> </div><div> void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {</div><div>- unsigned char *OldByte = (unsigned char *)Old;</div><div>- *OldByte++ = 0xEA; // Emit B opcode.</div><div>- unsigned *OldWord = (unsigned *)OldByte;</div><div>- unsigned NewAddr = (intptr_t)New;</div><div>- unsigned OldAddr = (intptr_t)OldWord;</div><div>- *OldWord = NewAddr - OldAddr - 4; // Emit PC-relative addr of New code.</div><div>+ assert(0);</div></blockquote><div><br class="webkit-block-placeholder"></div>Please use abort() instead so it does what's expected in non-debug build.</div><div><br><blockquote type="cite"><div> }</div><div> </div><div> /// JITCompilerFunction - This contains the address of the JIT function used to</div><div>@@ -65,7 +60,7 @@</div><div> #endif</div><div> }</div><div> </div><div>-/// ARMCompilationCallbackC - This is the target-specific function invoked by the</div><div>+/// ARMCompilationCallbackC - This i s the target-specific function invoked by the</div></blockquote><div><br class="webkit-block-placeholder"></div>i s -> is :-)</div><div><br class="webkit-block-placeholder"></div><div>Also, why the name "ARMCompilationCallbackC"? Is it language specific?</div><div><br><blockquote type="cite"><div> /// function stub when we did not know the real target of a call. This function</div><div> /// must locate the start of the stub or call site and pass it into the JIT</div><div> /// compiler function.</div><div>@@ -80,18 +75,16 @@</div><div> << ": Resolving call to function: "</div><div> << TheVM->getFunctionReferencedName((void*)RetAddr) << "\n";</div><div> #endif</div><div>+ intptr_t Addr = RetAddr - 4;</div><div> </div><div>- // Sanity check to make sure this really is a branch and link instruction.</div><div>- assert(((unsigned char*)RetAddr-1)[3] == 0xEB && "Not a branch and link instr!");</div><div>+ intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)Addr);</div></blockquote><div><br class="webkit-block-placeholder"></div>Does a similar assertion makes sense here?</div><div><br><blockquote type="cite"><div> </div><div>- intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)RetAddr);</div><div>-</div><div> // Rewrite the call target... so that we don't end up here every time we</div><div> // execute the call.</div><div>- *(intptr_t *)RetAddr = (intptr_t)(NewVal-RetAddr-4);</div><div>+ *(intptr_t *)Addr = NewVal;</div><div> </div><div> // Change the return address to reexecute the branch and link instruction...</div><div>- *RetAddrLoc -= 1;</div><div>+ *RetAddrLoc -= 8;</div><div> }</div><div> </div><div> TargetJITInfo::LazyResolverFn</div><div>@@ -101,23 +94,23 @@</div><div> }</div><div> </div><div> void *ARMJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {</div><div>- unsigned addr = (intptr_t)Fn-MCE.getCurrentPCValue()-4;</div><div>+ unsigned addr = (intptr_t)Fn;</div><div> // If this is just a call to an external function, emit a branch instead of a</div><div> // call. The code is the same except for one bit of the last instruction.</div><div> if (Fn != (void*)(intptr_t)ARMCompilationCallback) {</div><div>- MCE.startFunctionStub(4, 2);</div><div>- MCE.emitByte(0xEA); // branch to the corresponding function addr </div><div>- MCE.emitByte((unsigned char)(addr >> 0));</div><div>- MCE.emitByte((unsigned char)(addr >> 8));</div><div>- MCE.emitByte((unsigned char)(addr >> 16));</div><div>- return MCE.finishFunctionStub(0);</div><div>+ // branch to the corresponding function addr </div><div>+ MCE.startFunctionStub(8, 4);</div><div>+ MCE.emitWordLE(0xE51FF004); // LDR PC, [PC,#-4]</div></blockquote><div><br class="webkit-block-placeholder"></div>This is ok.... But I would rather see you refactor getBinaryCodeForInstr() so you can "manufacture" the value by passing it ARM::LDR, ARM::PC, etc.? Do you think that's possible?</div><div><br class="webkit-block-placeholder"></div><div>Also, in Emitter::getBinaryCodeForInstr():</div><div><br class="webkit-block-placeholder"></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;">unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {<br> const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();<br> const unsigned opcode = MI.getOpcode();<br> unsigned Value = 0xE0000000;</blockquote><div><br class="webkit-block-placeholder"></div><div>Comments? What is 0xe000000?</div><div><br class="webkit-block-placeholder"></div><br><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;"> unsigned op;<br><br> switch (Desc->TSFlags & ARMII::AddrModeMask) {<br> case ARMII::AddrModeNone: {<br> switch(Desc->TSFlags & ARMII::FormMask) {<br> default: {<br> assert(0 && "Unknown instruction subtype!");<br> if(opcode == ARM::CLZ) {<br><span class="Apple-tab-span" style="white-space:pre"> </span>// set first operand <br> op = getMachineOpValue(MI,0);<br> Value |= op << 12;</blockquote><div><br class="webkit-block-placeholder"></div>Can 12 (and all the magic shift amounts in this function) be defined in ARMII enum? So you add comments there rather than in this code.<div><br class="webkit-block-placeholder"><div><br><blockquote type="cite"><div>+ MCE.emitWordLE(addr);</div><div> } else {</div><div>- MCE.startFunctionStub(5, 2);</div><div>- MCE.emitByte(0xEB); // branch and link to the corresponding function addr</div><div>+ // branch and link to the corresponding function addr</div><div>+ MCE.startFunctionStub(20, 4);</div><div>+ MCE.emitWordLE(0xE92D4800); // STMFD SP!, [R11, LR]</div><div>+ MCE.emitWordLE(0xE28FE004); // ADD LR, PC, #4</div><div>+ MCE.emitWordLE(0xE51FF004); // LDR PC, [PC,#-4]</div><div>+ MCE.emitWordLE(addr);</div><div>+ MCE.emitWordLE(0xE8BD8800); // LDMFD SP!, [R11, PC]</div></blockquote><div><br class="webkit-block-placeholder"></div>Ditto.</div><div><br><blockquote type="cite"><div> }</div><div>- MCE.emitByte((unsigned char)(addr >> 0));</div><div>- MCE.emitByte((unsigned char)(addr >> 8));</div><div>- MCE.emitByte((unsigned char)(addr >> 16));</div><div> </div><div> return MCE.finishFunctionStub(0);</div><div> }</div><div>@@ -133,14 +126,22 @@</div><div> switch ((ARM::RelocationType)MR->getRelocationType()) {</div><div> case ARM::reloc_arm_relative: {</div><div> // PC relative relocation</div><div>- *((unsigned*)RelocPos) += (unsigned)ResultPtr;</div><div>+ ResultPtr = ResultPtr-(intptr_t)RelocPos-8;</div><div>+ if (ResultPtr >= 0)</div><div>+ *((unsigned*)RelocPos) |= 1 << 23;</div><div>+ else {</div><div>+ ResultPtr *= -1;</div><div>+ *((unsigned*)RelocPos) &= 0xFF7FFFFF;</div></blockquote><div><br class="webkit-block-placeholder"></div>Please explain what's going on here? :-)</div><div><br><blockquote type="cite"><div>+ }</div><div>+ *((unsigned*)RelocPos) |= (unsigned)ResultPtr;</div><div>+ *((unsigned*)RelocPos) |= 0xF << 16;</div><div> break;</div><div> }</div><div>- case ARM::reloc_arm_absolute:</div><div>- break;</div><div> case ARM::reloc_arm_branch: {</div><div> // relocation to b and bl instructions</div><div>- ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;</div><div>+ ResultPtr = ResultPtr-(intptr_t)RelocPos-8;</div><div>+ ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2;</div><div>+ //assert(ResultPtr >= -33554432 && ResultPtr <= 33554428);</div><div> *((unsigned*)RelocPos) |= ResultPtr;</div><div> break;</div><div> }</div><div>Index: lib/Target/ARM/ARMInstrInfo.td</div><div>===================================================================</div><div>--- lib/Target/ARM/ARMInstrInfo.td<span class="Apple-tab-span" style="white-space:pre"> </span>(revisão 41124)</div><div>+++ lib/Target/ARM/ARMInstrInfo.td<span class="Apple-tab-span" style="white-space:pre"> </span>(cópia de trabalho)</div><div>@@ -342,33 +342,38 @@</div><div> </div><div> def Pseudo : Format<1>;</div><div> def MulFrm : Format<2>;</div><div>-def Branch : Format<3>;</div><div>-def BranchMisc : Format<4>;</div><div>+def MulSMLAW : Format<3>;</div><div>+def MulSMULW : Format<4>;</div><div>+def MulSMLA : Format<5>;</div><div>+def MulSMUL : Format<6>;</div><div>+def Branch : Format<7>;</div><div>+def BranchMisc : Format<8>;</div><div> </div><div>-def DPRdIm : Format<5>;</div><div>-def DPRdReg : Format<6>;</div><div>-def DPRdSoReg : Format<7>;</div><div>-def DPRdMisc : Format<8>;</div><div>-def DPRnIm : Format<9>;</div><div>-def DPRnReg : Format<10>;</div><div>-def DPRnSoReg : Format<11>;</div><div>-def DPRIm : Format<12>;</div><div>-def DPRReg : Format<13>;</div><div>-def DPRSoReg : Format<14>;</div><div>-def DPRImS : Format<15>;</div><div>-def DPRRegS : Format<16>;</div><div>-def DPRSoRegS : Format<17>;</div><div>+def DPRdIm : Format<9>;</div><div>+def DPRdReg : Format<10>;</div><div>+def DPRdSoReg : Format<11>;</div><div>+def DPRdMisc : Format<12>;</div><div>+def DPRnIm : Format<13>;</div><div>+def DPRnReg : Format<14>;</div><div>+def DPRnSoReg : Format<15>;</div><div>+def DPRIm : Format<16>;</div><div>+def DPRReg : Format<17>;</div><div>+def DPRSoReg : Format<18>;</div><div>+def DPRImS : Format<19>;</div><div>+def DPRRegS : Format<20>;</div><div>+def DPRSoRegS : Format<21>;</div><div> </div><div>-def LdFrm : Format<18>;</div><div>-def StFrm : Format<19>;</div><div>+def LdFrm : Format<22>;</div><div>+def StFrm : Format<23>;</div><div> </div><div>-def ArithMisc : Format<20>;</div><div>-def ThumbFrm : Format<21>;</div><div>-def VFPFrm : Format<22>;</div><div>+def ArithMisc : Format<24>;</div><div>+def ThumbFrm : Format<25>;</div><div>+def VFPFrm : Format<26>;</div><div> </div><div> </div><div> </div><div> //===----------------------------------------------------------------------===//</div><div>+</div><div> // ARM Instruction templates.</div><div> //</div><div> </div><div>@@ -815,7 +820,7 @@</div><div> [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;</div><div> </div><div> // Load doubleword</div><div>-def LDRD : AI3<0x0, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,</div><div>+def LDRD : AI3<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdFrm,</div><div> "ldr", "d $dst, $addr",</div><div> []>, Requires<[IsARM, HasV5T]>;</div><div> </div><div>@@ -877,7 +882,7 @@</div><div> [(truncstorei8 GPR:$src, addrmode2:$addr)]>;</div><div> </div><div> // Store doubleword</div><div>-def STRD : AI3<0x0, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,</div><div>+def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,</div><div> "str", "d $src, $addr",</div><div> []>, Requires<[IsARM, HasV5T]>;</div><div> </div><div>@@ -1125,76 +1130,86 @@</div><div> [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,</div><div> Requires<[IsARM, HasV6]>;</div><div> </div><div>-multiclass AI_smul<bits<4> opcod, string opc, PatFrag opnode> {</div><div>- def BB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,</div><div>+multiclass AI_smul<string opc, PatFrag opnode> {</div><div>+ def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,</div><div> !strconcat(opc, "bb"), " $dst, $a, $b",</div><div> [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),</div><div> (sext_inreg GPR:$b, i16)))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def BT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,</div><div>+</div><div>+ def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,</div><div> !strconcat(opc, "bt"), " $dst, $a, $b",</div><div> [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),</div><div> (sra GPR:$b, 16)))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def TB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,</div><div>+</div><div>+ def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,</div><div> !strconcat(opc, "tb"), " $dst, $a, $b",</div><div> [(set GPR:$dst, (opnode (sra GPR:$a, 16),</div><div> (sext_inreg GPR:$b, i16)))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def TT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,</div><div>+</div><div>+ def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,</div><div> !strconcat(opc, "tt"), " $dst, $a, $b",</div><div> [(set GPR:$dst, (opnode (sra GPR:$a, 16),</div><div> (sra GPR:$b, 16)))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def WB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,</div><div>+</div><div>+ def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,</div><div> !strconcat(opc, "wb"), " $dst, $a, $b",</div><div> [(set GPR:$dst, (sra (opnode GPR:$a,</div><div> (sext_inreg GPR:$b, i16)), 16))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def WT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,</div><div>+</div><div>+ def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMULW,</div><div> !strconcat(opc, "wt"), " $dst, $a, $b",</div><div> [(set GPR:$dst, (sra (opnode GPR:$a,</div><div> (sra GPR:$b, 16)), 16))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div> }</div><div> </div><div>-multiclass AI_smla<bits<4> opcod, string opc, PatFrag opnode> {</div><div>- def BB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,</div><div>+</div><div>+multiclass AI_smla<string opc, PatFrag opnode> {</div><div>+ def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,</div><div> !strconcat(opc, "bb"), " $dst, $a, $b, $acc",</div><div> [(set GPR:$dst, (add GPR:$acc,</div><div> (opnode (sext_inreg GPR:$a, i16),</div><div> (sext_inreg GPR:$b, i16))))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def BT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,</div><div>+</div><div>+ def BT : AI<0xC, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,</div><div> !strconcat(opc, "bt"), " $dst, $a, $b, $acc",</div><div> [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),</div><div> (sra GPR:$b, 16))))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def TB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,</div><div>+</div><div>+ def TB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,</div><div> !strconcat(opc, "tb"), " $dst, $a, $b, $acc",</div><div> [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),</div><div> (sext_inreg GPR:$b, i16))))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def TT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,</div><div>+</div><div>+ def TT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,</div><div> !strconcat(opc, "tt"), " $dst, $a, $b, $acc",</div><div> [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),</div><div> (sra GPR:$b, 16))))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div> </div><div>- def WB : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,</div><div>+ def WB : AI<0xA, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,</div><div> !strconcat(opc, "wb"), " $dst, $a, $b, $acc",</div><div> [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,</div><div> (sext_inreg GPR:$b, i16)), 16)))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div>- def WT : AI<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulFrm,</div><div>+</div><div>+ def WT : AI<0xE, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLAW,</div><div> !strconcat(opc, "wt"), " $dst, $a, $b, $acc",</div><div> [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,</div><div> (sra GPR:$b, 16)), 16)))]>,</div><div> Requires<[IsARM, HasV5TE]>;</div><div> }</div><div> </div><div>-defm SMUL : AI_smul<0x0, "smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;</div><div>-defm SMLA : AI_smla<0x0, "smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;</div><div>+defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;</div><div>+defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;</div><div> </div><div> // TODO: Halfword multiple accumulate long: SMLAL<x><y></div><div> // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD</div><div>Index: lib/Target/ARM/ARMCodeEmitter.cpp</div><div>===================================================================</div><div>--- lib/Target/ARM/ARMCodeEmitter.cpp<span class="Apple-tab-span" style="white-space:pre"> </span>(revisão 41124)</div><div>+++ lib/Target/ARM/ARMCodeEmitter.cpp<span class="Apple-tab-span" style="white-space:pre"> </span>(cópia de trabalho)</div><div>@@ -54,9 +54,9 @@</div><div> }</div><div> </div><div> void emitInstruction(const MachineInstr &MI);</div><div>- unsigned getBinaryCodeForInstr(const MachineInstr &MI);</div><div> int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);</div><div> unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);</div><div>+ unsigned getBinaryCodeForInstr(const MachineInstr &MI);</div><div> </div><div> void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);</div><div> void emitExternalSymbolAddress(const char *ES, unsigned Reloc);</div><div>@@ -64,6 +64,7 @@</div><div> int Disp = 0, unsigned PCAdj = 0 );</div><div> void emitJumpTableAddress(unsigned JTI, unsigned Reloc,</div><div> unsigned PCAdj = 0);</div><div>+ void emitGlobalConstant(const Constant *CV);</div><div> </div><div> private:</div><div> int getShiftOp(const MachineOperand &MO);</div><div>@@ -137,7 +138,7 @@</div><div> MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {</div><div> </div><div> if (MO.isGlobalAddress()) {</div><div>- emitGlobalAddressForCall(MO.getGlobal(), true);</div><div>+ emitGlobalAddressForCall(MO.getGlobal(), false);</div><div> } else if (MO.isExternalSymbol()) {</div><div> emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);</div><div> } else if (MO.isConstantPoolIndex()) {</div><div>@@ -186,8 +187,6 @@</div><div> Reloc, JTI, PCAdj));</div><div> }</div><div> </div><div>-</div><div>-</div><div> void Emitter::emitInstruction(const MachineInstr &MI) {</div><div> NumEmitted++; // Keep track of the # of mi's emitted</div><div> MCE.emitWordLE(getBinaryCodeForInstr(MI));</div><div>@@ -215,6 +214,37 @@</div><div> }</div><div> break;</div><div> }</div><div>+ case ARMII::MulSMLAW:</div><div>+ case ARMII::MulSMULW:</div><div>+ Value |= 1 << 21;</div><div>+ case ARMII::MulSMLA:</div><div>+ case ARMII::MulSMUL: {</div><div>+ Value |= 1 << 24;</div><div>+</div><div>+ unsigned char BaseOpcode = getBaseOpcodeFor(Desc);</div><div>+ Value |= BaseOpcode << 4;</div><div>+</div><div>+ unsigned Format = (Desc->TSFlags & ARMII::FormMask);</div><div>+</div><div>+ if (Format == ARMII::MulSMUL)</div><div>+ Value |= 1 << 22;</div><div>+</div><div>+ op = getMachineOpValue(MI,0);</div><div>+ Value |= op << 16;</div><div>+</div><div>+ op = getMachineOpValue(MI,1);</div><div>+ Value |= op;</div><div>+</div><div>+ op = getMachineOpValue(MI,2);</div><div>+ Value |= op << 8;</div><div>+</div><div>+ if (Format != ARMII::MulSMULW && Format != ARMII::MulSMUL) {</div><div>+ op = getMachineOpValue(MI,3);</div><div>+ Value |= op << 12;</div><div>+ }</div><div>+</div><div>+ break;</div><div>+ }</div><div> case ARMII::MulFrm: {</div><div> Value |= 9 << 4;</div><div> </div><div>@@ -460,7 +490,7 @@</div><div> Value |= 1 << 24;</div><div> </div><div> unsigned Format = (Desc->TSFlags & ARMII::FormMask);</div><div>- if (Format == ARMII::LdFrm)</div><div>+ if (Format == ARMII::LdFrm && opcode != ARM::LDRD)</div></blockquote><div><br class="webkit-block-placeholder"></div>Instead of special casing it for LDRD, perhaps add a LB (L bit) class and attach to the other instructions that need it? See X86InstrFormats.td for examples (e.g. TB). I'd like to see PUWLSH bits modeled more clearly.</div><div><br class="webkit-block-placeholder"></div><div><br><blockquote type="cite"><div> Value |= 1 << 20;</div><div> </div><div> unsigned char BaseOpcode = getBaseOpcodeFor(Desc);</div><div>Index: lib/Target/ARM/ARMInstrInfo.h</div><div>===================================================================</div><div>--- lib/Target/ARM/ARMInstrInfo.h<span class="Apple-tab-span" style="white-space:pre"> </span>(revisão 41124)</div><div>+++ lib/Target/ARM/ARMInstrInfo.h<span class="Apple-tab-span" style="white-space:pre"> </span>(cópia de trabalho)</div><div>@@ -73,43 +73,46 @@</div><div> </div><div> // Multiply instructions</div><div> MulFrm = 2 << FormShift,</div><div>+ MulSMLAW = 3 << FormShift,</div><div>+ MulSMULW = 4 << FormShift,</div><div>+ MulSMLA = 5 << FormShift,</div><div>+ MulSMUL = 6 << FormShift,</div><div> </div><div> // Branch instructions</div><div>- Branch = 3 << FormShift,</div><div>- BranchMisc = 4 << FormShift,</div><div>+ Branch = 7 << FormShift,</div><div>+ BranchMisc = 8 << FormShift,</div><div> </div><div> // Data Processing instructions</div><div>- DPRdIm = 5 << FormShift,</div><div>- DPRdReg = 6 << FormShift,</div><div>- DPRdSoReg = 7 << FormShift,</div><div>- DPRdMisc = 8 << FormShift,</div><div>+ DPRdIm = 9 << FormShift,</div><div>+ DPRdReg = 10 << FormShift,</div><div>+ DPRdSoReg = 11 << FormShift,</div><div>+ DPRdMisc = 12 << FormShift,</div><div> </div><div>- DPRnIm = 9 << FormShift,</div><div>- DPRnReg = 10 << FormShift,</div><div>- DPRnSoReg = 11 << FormShift,</div><div>+ DPRnIm = 13 << FormShift,</div><div>+ DPRnReg = 14 << FormShift,</div><div>+ DPRnSoReg = 15 << FormShift,</div><div> </div><div>- DPRIm = 12 << FormShift,</div><div>- DPRReg = 13 << FormShift,</div><div>- DPRSoReg = 14 << FormShift,</div><div>+ DPRIm = 16 << FormShift,</div><div>+ DPRReg = 17 << FormShift,</div><div>+ DPRSoReg = 18 << FormShift,</div><div> </div><div>- DPRImS = 15 << FormShift,</div><div>- DPRRegS = 16 << FormShift,</div><div>- DPRSoRegS = 17 << FormShift,</div><div>+ DPRImS = 19 << FormShift,</div><div>+ DPRRegS = 20 << FormShift,</div><div>+ DPRSoRegS = 21 << FormShift,</div><div> </div><div> // Load and Store</div><div>- LdFrm = 18 << FormShift,</div><div>- StFrm = 19 << FormShift,</div><div>+ LdFrm = 22 << FormShift,</div><div>+ StFrm = 23 << FormShift,</div><div> </div><div> // Miscellaneous arithmetic instructions</div><div>- ArithMisc = 20 << FormShift,</div><div>+ ArithMisc = 24 << FormShift,</div><div> </div><div> // Thumb format</div><div>- ThumbFrm = 21 << FormShift,</div><div>+ ThumbFrm = 25 << FormShift,</div><div> </div><div> // VFP format</div><div>- VPFFrm = 22 << FormShift</div><div>+ VPFFrm = 26 << FormShift</div><div> </div><div>-</div><div> };</div><div> }</div><div> </div><div>Index: lib/Target/ARM/ARMRelocations.h</div><div>===================================================================</div><div>--- lib/Target/ARM/ARMRelocations.h<span class="Apple-tab-span" style="white-space:pre"> </span>(revisão 41124)</div><div>+++ lib/Target/ARM/ARMRelocations.h<span class="Apple-tab-span" style="white-space:pre"> </span>(cópia de trabalho)</div><div>@@ -21,8 +21,6 @@</div><div> enum RelocationType {</div><div> reloc_arm_relative,</div><div> </div><div>- reloc_arm_absolute,</div><div>-</div><div> reloc_arm_branch</div><div> };</div><div> }</div></blockquote><div><br class="webkit-block-placeholder"></div><div><div>On Aug 16, 2007, at 2:07 PM, Raul Fernandes Herbster wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Multiply instructions are being generated. ARM/JIT runs an application with no calls to local functions, but library functions calls are supported. I hope fix such problem soon. Please, send me any feedback.<br><br>Thanks in advance, Raul. <br clear="all"><br>-- <br>Raul Fernandes Herbster<br>Embedded and Pervasive Computing Laboratory - <a href="http://embedded.dee.ufcg.edu.br">embedded.dee.ufcg.edu.br</a><br>Electrical Engineering Department - DEE - <a href="http://www.dee.ufcg.edu.br"> www.dee.ufcg.edu.br</a><br>Electrical Engineering and Informatics Center - CEEI<br>Federal University of Campina Grande - UFCG - <a href="http://www.ufcg.edu.br">www.ufcg.edu.br</a><br>Caixa Postal 10105<br>58109-970 Campina Grande - PB - Brasil <span><patch></span>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></blockquote></div><br></div></div></body></html>