[llvm] [SelectionDAG]: Have isKnownNeverZero treat SRL like division if all else fails (PR #89523)

[Simon Pilgrim via llvm-commits]

================
@@ -5443,10 +5443,19 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
     if (ValKnown.isNegative())
       return true;
     // If max shift cnt of known ones is non-zero, result is non-zero.
-    APInt MaxCnt = computeKnownBits(Op.getOperand(1), Depth + 1).getMaxValue();
+    const KnownBits Shift = computeKnownBits(Op.getOperand(1), Depth + 1);
+    APInt MaxCnt = Shift.getMaxValue();
     if (MaxCnt.ult(ValKnown.getBitWidth()) &&
         !ValKnown.One.lshr(MaxCnt).isZero())
       return true;
----------------
RKSimon wrote:

Split this so the code below can all assume MaxCnt < BW:
```c
if (MaxCnt.uge(ValKnown.getBitWidth())
  return false;
if (!ValKnown.One.lshr(MaxCnt).isZero())
  return true;
```

https://github.com/llvm/llvm-project/pull/89523