[llvm] [Attributor] Fix Load/Store offsets in case of multiple access bins when an allocation size is changed. (PR #72029)
Vidhush Singhal via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 20 10:58:09 PDT 2024
https://github.com/vidsinghal updated https://github.com/llvm/llvm-project/pull/72029
>From d64f2884917f227f9f6799550fe42d6b8e334040 Mon Sep 17 00:00:00 2001
From: vidsinghal <vidush.sl at gmail.com>
Date: Sun, 5 Nov 2023 22:30:42 -0500
Subject: [PATCH 1/3] [Attributor] Fix Load/Store Offsets if multiple bins are
present for a pointer allocation.
---
llvm/include/llvm/Transforms/IPO/Attributor.h | 5 +
.../Transforms/IPO/AttributorAttributes.cpp | 185 ++++++--
.../2008-02-01-ReturnAttrs.ll | 16 +-
.../ArgumentPromotion/X86/attributes.ll | 48 +-
.../X86/min-legal-vector-width.ll | 208 ++++-----
.../Attributor/ArgumentPromotion/alignment.ll | 6 +-
.../Attributor/ArgumentPromotion/alloca-as.ll | 10 +-
.../Attributor/ArgumentPromotion/array.ll | 21 +-
.../Attributor/ArgumentPromotion/attrs.ll | 20 +-
.../Attributor/ArgumentPromotion/basictest.ll | 2 +-
.../Attributor/ArgumentPromotion/byval-2.ll | 20 +-
.../Attributor/ArgumentPromotion/byval.ll | 30 +-
.../ArgumentPromotion/control-flow2.ll | 2 +-
.../Attributor/ArgumentPromotion/crash.ll | 2 +
.../Attributor/ArgumentPromotion/fp80.ll | 6 +-
.../live_called_from_dead.ll | 10 +-
.../live_called_from_dead_2.ll | 12 +-
.../pr33641_remove_arg_dbgvalue.ll | 2 +-
.../Attributor/ArgumentPromotion/profile.ll | 6 +-
.../Attributor/ArgumentPromotion/sret.ll | 5 +-
.../IPConstantProp/openmp_parallel_for.ll | 70 +--
.../IPConstantProp/return-argument.ll | 4 +-
llvm/test/Transforms/Attributor/align.ll | 16 +-
llvm/test/Transforms/Attributor/allocator.ll | 184 +++++---
.../Attributor/call-simplify-pointer-info.ll | 72 ++-
llvm/test/Transforms/Attributor/callbacks.ll | 70 +--
.../Transforms/Attributor/heap_to_stack.ll | 10 +-
.../Attributor/heap_to_stack_gpu.ll | 10 +-
.../Transforms/Attributor/internal-noalias.ll | 14 +-
llvm/test/Transforms/Attributor/noalias.ll | 38 +-
.../test/Transforms/Attributor/nocapture-2.ll | 52 ++-
llvm/test/Transforms/Attributor/nofpclass.ll | 84 +++-
llvm/test/Transforms/Attributor/norecurse.ll | 6 +-
.../Transforms/Attributor/openmp_parallel.ll | 12 +-
.../Transforms/Attributor/pointer-info.ll | 8 +-
.../Attributor/value-simplify-assume.ll | 220 ++++-----
.../Attributor/value-simplify-dominance.ll | 24 +-
.../Attributor/value-simplify-gpu.ll | 6 +-
.../Attributor/value-simplify-local-remote.ll | 16 +-
.../Transforms/Attributor/value-simplify.ll | 30 +-
.../Transforms/OpenMP/parallel_deletion.ll | 67 ++-
.../OpenMP/parallel_region_merging.ll | 422 ++++++++++--------
42 files changed, 1235 insertions(+), 816 deletions(-)
diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h
index 30c51250af61ca..fb96e52121f82b 100644
--- a/llvm/include/llvm/Transforms/IPO/Attributor.h
+++ b/llvm/include/llvm/Transforms/IPO/Attributor.h
@@ -6122,6 +6122,8 @@ struct AAPointerInfo : public AbstractAttribute {
virtual const_bin_iterator begin() const = 0;
virtual const_bin_iterator end() const = 0;
virtual int64_t numOffsetBins() const = 0;
+ virtual void dumpState(raw_ostream &O) const = 0;
+ virtual const Access &getBinAccess(unsigned Index) const = 0;
/// Call \p CB on all accesses that might interfere with \p Range and return
/// true if all such accesses were known and the callback returned true for
@@ -6293,6 +6295,9 @@ struct AAAllocationInfo : public StateWrapper<BooleanState, AbstractAttribute> {
virtual std::optional<TypeSize> getAllocatedSize() const = 0;
+ using NewOffsetsTy = DenseMap<AA::RangeTy, AA::RangeTy>;
+ virtual const NewOffsetsTy &getNewOffsets() const = 0;
+
/// See AbstractAttribute::getName()
const std::string getName() const override { return "AAAllocationInfo"; }
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 41b66aafe7d343..25b24d154f5525 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -1083,6 +1083,10 @@ struct AAPointerInfoImpl
return State::numOffsetBins();
}
+ virtual const Access &getBinAccess(unsigned Index) const override {
+ return getAccess(Index);
+ }
+
bool forallInterferingAccesses(
AA::RangeTy Range,
function_ref<bool(const AAPointerInfo::Access &, bool)> CB)
@@ -1429,7 +1433,7 @@ struct AAPointerInfoImpl
void trackPointerInfoStatistics(const IRPosition &IRP) const {}
/// Dump the state into \p O.
- void dumpState(raw_ostream &O) {
+ virtual void dumpState(raw_ostream &O) const override {
for (auto &It : OffsetBins) {
O << "[" << It.first.Offset << "-" << It.first.Offset + It.first.Size
<< "] : " << It.getSecond().size() << "\n";
@@ -12686,6 +12690,11 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
return AssumedAllocatedSize;
}
+ const NewOffsetsTy &getNewOffsets() const override {
+ assert(isValidState() && "the AA is invalid");
+ return NewComputedOffsets;
+ }
+
std::optional<TypeSize> findInitialAllocationSize(Instruction *I,
const DataLayout &DL) {
@@ -12735,37 +12744,42 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
if (*AllocationSize == 0)
return indicatePessimisticFixpoint();
- int64_t BinSize = PI->numOffsetBins();
-
- // TODO: implement for multiple bins
- if (BinSize > 1)
- return indicatePessimisticFixpoint();
+ int64_t NumBins = PI->numOffsetBins();
- if (BinSize == 0) {
+ if (NumBins == 0) {
auto NewAllocationSize = std::optional<TypeSize>(TypeSize(0, false));
if (!changeAllocationSize(NewAllocationSize))
return ChangeStatus::UNCHANGED;
return ChangeStatus::CHANGED;
}
- // TODO: refactor this to be part of multiple bin case
- const auto &It = PI->begin();
+ // For each access bin
+ // Compute its new start Offset and store the results in a new map
+ // (NewOffsetBins).
+ int64_t PrevBinEndOffset = 0;
+ bool ChangedOffsets = false;
+ for (AAPointerInfo::OffsetBinsTy::const_iterator It = PI->begin();
+ It != PI->end(); It++) {
+ const AA::RangeTy &OldRange = It->getFirst();
+ int64_t NewStartOffset = PrevBinEndOffset;
+ int64_t NewEndOffset = NewStartOffset + OldRange.Size;
+ PrevBinEndOffset = NewEndOffset;
- // TODO: handle if Offset is not zero
- if (It->first.Offset != 0)
- return indicatePessimisticFixpoint();
-
- uint64_t SizeOfBin = It->first.Offset + It->first.Size;
-
- if (SizeOfBin >= *AllocationSize)
- return indicatePessimisticFixpoint();
+ ChangedOffsets |= setNewOffsets(OldRange, OldRange.Offset, NewStartOffset,
+ OldRange.Size);
+ }
+ // Set the new size of the allocation, the new size of the Allocation should
+ // be the size of NewEndOffset * 8, in bits.
auto NewAllocationSize =
- std::optional<TypeSize>(TypeSize(SizeOfBin * 8, false));
+ std::optional<TypeSize>(TypeSize(PrevBinEndOffset * 8, false));
if (!changeAllocationSize(NewAllocationSize))
return ChangeStatus::UNCHANGED;
+ if (!ChangedOffsets)
+ return ChangeStatus::UNCHANGED;
+
return ChangeStatus::CHANGED;
}
@@ -12775,18 +12789,18 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
assert(isValidState() &&
"Manifest should only be called if the state is valid.");
- Instruction *I = getIRPosition().getCtxI();
+ bool Changed = false;
+ const IRPosition &IRP = getIRPosition();
+ Instruction *I = IRP.getCtxI();
auto FixedAllocatedSizeInBits = getAllocatedSize()->getFixedValue();
unsigned long NumBytesToAllocate = (FixedAllocatedSizeInBits + 7) / 8;
-
switch (I->getOpcode()) {
// TODO: add case for malloc like calls
case Instruction::Alloca: {
AllocaInst *AI = cast<AllocaInst>(I);
-
Type *CharType = Type::getInt8Ty(I->getContext());
auto *NumBytesToValue =
@@ -12798,16 +12812,102 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
new AllocaInst(CharType, AI->getAddressSpace(), NumBytesToValue,
AI->getAlign(), AI->getName(), insertPt);
- if (A.changeAfterManifest(IRPosition::inst(*AI), *NewAllocaInst))
- return ChangeStatus::CHANGED;
-
+ Changed |= A.changeAfterManifest(IRPosition::inst(*AI), *NewAllocaInst);
break;
}
default:
break;
}
- return ChangeStatus::UNCHANGED;
+ const AAPointerInfo *PI =
+ A.getOrCreateAAFor<AAPointerInfo>(IRP, *this, DepClassTy::REQUIRED);
+
+ if (!PI)
+ return ChangeStatus::UNCHANGED;
+
+ if (!PI->getState().isValidState())
+ return ChangeStatus::UNCHANGED;
+
+ const auto &NewOffsetsMap = getNewOffsets();
+ for (AAPointerInfo::OffsetBinsTy::const_iterator It = PI->begin();
+ It != PI->end(); It++) {
+
+ const auto &OldOffsetRange = It->getFirst();
+
+ // If the OldOffsetRange is not in the map, offsets for that bin did not
+ // change We should just continue and skip changing the offsets in that
+ // case
+ if (!NewOffsetsMap.contains(OldOffsetRange))
+ continue;
+
+ const auto &NewOffsetRange = NewOffsetsMap.lookup(OldOffsetRange);
+ for (const auto AccIndex : It->getSecond()) {
+
+ const auto &AccessInstruction = PI->getBinAccess(AccIndex);
+ auto *LocalInst = AccessInstruction.getLocalInst();
+
+ switch (LocalInst->getOpcode()) {
+ case Instruction::Load: {
+ LoadInst *OldLoadInst = cast<LoadInst>(LocalInst);
+ Value *PointerOperand = OldLoadInst->getPointerOperand();
+
+ // We need to shift the old start offset by the difference between the
+ // Old offset and the New offset.
+ Value *ShiftValueForPointerOperand = ConstantInt::get(
+ OldLoadInst->getContext(),
+ APInt(32, (OldOffsetRange.Offset - NewOffsetRange.Offset)));
+ // Cast ptr to 32 bit integer
+ CastInst *PtrOperandToInt = PtrToIntInst::CreatePointerCast(
+ PointerOperand, Type::getInt32Ty(OldLoadInst->getContext()), "",
+ OldLoadInst);
+ // Subtract shift amount from old offset
+ BinaryOperator *NewPointerOperandInt = BinaryOperator::Create(
+ Instruction::Sub, PtrOperandToInt, ShiftValueForPointerOperand,
+ "", OldLoadInst);
+ // Convert Int to ptr.
+ CastInst *IntToPtr = new IntToPtrInst(
+ NewPointerOperandInt, OldLoadInst->getPointerOperandType(), "",
+ OldLoadInst);
+ LoadInst *NewLoadInst =
+ new LoadInst(OldLoadInst->getType(), IntToPtr,
+ OldLoadInst->getName(), OldLoadInst);
+ Changed |= A.changeAfterManifest(IRPosition::inst(*OldLoadInst),
+ *NewLoadInst);
+ break;
+ }
+ case Instruction::Store: {
+ StoreInst *OldStoreInst = cast<StoreInst>(LocalInst);
+ Value *PointerOperand = OldStoreInst->getPointerOperand();
+
+ Value *ShiftValueForPointerOperand = ConstantInt::get(
+ OldStoreInst->getContext(),
+ APInt(32, (OldOffsetRange.Offset - NewOffsetRange.Offset)));
+
+ // Cast ptr to 32 bit integer
+ CastInst *PtrOperandToInt = PtrToIntInst::CreatePointerCast(
+ PointerOperand, Type::getInt32Ty(OldStoreInst->getContext()), "",
+ OldStoreInst);
+ // Subtract shift amount from old offset
+ BinaryOperator *NewPointerOperandInt = BinaryOperator::Create(
+ Instruction::Sub, PtrOperandToInt, ShiftValueForPointerOperand,
+ "", OldStoreInst);
+ // Convert Int to ptr.
+ CastInst *IntToPtr = new IntToPtrInst(
+ NewPointerOperandInt, OldStoreInst->getPointerOperandType(), "",
+ OldStoreInst);
+ StoreInst *NewStoreInst = new StoreInst(
+ OldStoreInst->getValueOperand(), IntToPtr, OldStoreInst);
+ Changed |= A.changeAfterManifest(IRPosition::inst(*OldStoreInst),
+ *NewStoreInst);
+ break;
+ }
+ }
+ }
+ }
+
+ if (!Changed)
+ return ChangeStatus::UNCHANGED;
+ return ChangeStatus::CHANGED;
}
/// See AbstractAttribute::getAsStr().
@@ -12821,8 +12921,28 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
")";
}
+ void dumpNewOffsetBins(raw_ostream &O) {
+
+ O << "Printing Map from [OldOffsetsRange] : [NewOffsetsRange] if the "
+ "offsets changed."
+ << "\n";
+ const auto &NewOffsetsMap = getNewOffsets();
+ for (auto It = NewOffsetsMap.begin(); It != NewOffsetsMap.end(); It++) {
+
+ const auto &OldRange = It->getFirst();
+ const auto &NewRange = It->getSecond();
+
+ O << "[" << OldRange.Offset << "," << OldRange.Offset + OldRange.Size
+ << "] : ";
+ O << "[" << NewRange.Offset << "," << NewRange.Offset + NewRange.Size
+ << "]";
+ O << "\n";
+ }
+ }
+
private:
std::optional<TypeSize> AssumedAllocatedSize = HasNoAllocationSize;
+ NewOffsetsTy NewComputedOffsets;
// Maintain the computed allocation size of the object.
// Returns (bool) weather the size of the allocation was modified or not.
@@ -12834,6 +12954,21 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
}
return false;
}
+
+ // Maps an old byte range to its new Offset range in the new allocation.
+ // Returns (bool) weather the old byte range's offsets changed or not.
+ bool setNewOffsets(const AA::RangeTy &OldRange, int64_t OldOffset,
+ int64_t NewComputedOffset, int64_t Size) {
+
+ if (OldOffset == NewComputedOffset)
+ return false;
+
+ AA::RangeTy &NewRange = NewComputedOffsets.getOrInsertDefault(OldRange);
+ NewRange.Offset = NewComputedOffset;
+ NewRange.Size = Size;
+
+ return true;
+ }
};
struct AAAllocationInfoFloating : AAAllocationInfoImpl {
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
index 8254ab6230440f..e6062da1d1457b 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
@@ -9,8 +9,8 @@ define internal i32 @deref(ptr %x) nounwind {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: [[X_PRIV:%.*]] = alloca i32, align 4
; CGSCC-NEXT: store i32 [[TMP0]], ptr [[X_PRIV]], align 4
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = load i32, ptr [[X_PRIV]], align 4
-; CGSCC-NEXT: ret i32 [[TRUETMP2]]
+; CGSCC-NEXT: [[TMP2:%.*]] = load i32, ptr [[X_PRIV]], align 4
+; CGSCC-NEXT: ret i32 [[TMP2]]
;
entry:
%tmp2 = load i32, ptr %x, align 4
@@ -22,18 +22,18 @@ define i32 @f(i32 %x) {
; TUNIT-LABEL: define {{[^@]+}}@f
; TUNIT-SAME: (i32 returned [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4
+; TUNIT-NEXT: [[X_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store i32 [[X]], ptr [[X_ADDR1]], align 4
; TUNIT-NEXT: ret i32 [[X]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@f
; CGSCC-SAME: (i32 [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
-; CGSCC-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4
-; CGSCC-NEXT: [[TRUETMP1:%.*]] = call i32 @deref(i32 [[X]]) #[[ATTR2:[0-9]+]]
-; CGSCC-NEXT: ret i32 [[TRUETMP1]]
+; CGSCC-NEXT: [[X_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: store i32 [[X]], ptr [[X_ADDR1]], align 4
+; CGSCC-NEXT: [[TMP1:%.*]] = call i32 @deref(i32 [[X]]) #[[ATTR2:[0-9]+]]
+; CGSCC-NEXT: ret i32 [[TMP1]]
;
entry:
%x_addr = alloca i32
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll
index 71e8bd11e9c769..7dfe6ef96a691c 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll
@@ -26,12 +26,12 @@ define void @no_promote(ptr %arg) #1 {
; TUNIT-LABEL: define {{[^@]+}}@no_promote
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <4 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
-; TUNIT-NEXT: call fastcc void @no_promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TRUETMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <4 x i64>, ptr [[TRUETMP2]], align 32
-; TUNIT-NEXT: store <4 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 32, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 32, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
+; TUNIT-NEXT: call fastcc void @no_promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP22]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP1]]) #[[ATTR4:[0-9]+]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP22]], align 32
+; TUNIT-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(argmem: readwrite) uwtable
@@ -39,11 +39,11 @@ define void @no_promote(ptr %arg) #1 {
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
; CGSCC-NEXT: bb:
; CGSCC-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <4 x i64>, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3:[0-9]+]]
-; CGSCC-NEXT: call fastcc void @no_promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TRUETMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <4 x i64>, ptr [[TRUETMP2]], align 32
-; CGSCC-NEXT: store <4 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: call fastcc void @no_promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 32 dereferenceable(32) [[TMP]]) #[[ATTR4:[0-9]+]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
+; CGSCC-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -78,26 +78,26 @@ define void @promote(ptr %arg) #0 {
; TUNIT-LABEL: define {{[^@]+}}@promote
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <4 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[TMP]], align 32
-; TUNIT-NEXT: call fastcc void @promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TRUETMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <4 x i64>, ptr [[TRUETMP2]], align 32
-; TUNIT-NEXT: store <4 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 32, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 32, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[TMP1]], align 32
+; TUNIT-NEXT: call fastcc void @promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP22]], <4 x i64> [[TMP0]]) #[[ATTR4]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP22]], align 32
+; TUNIT-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@promote
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(32) [[ARG:%.*]]) #[[ATTR0]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <4 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <4 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[TMP]], align 32
-; CGSCC-NEXT: call fastcc void @promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TRUETMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <4 x i64>, ptr [[TRUETMP2]], align 32
-; CGSCC-NEXT: store <4 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 32, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <4 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR3]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr [[TMP1]], align 32
+; CGSCC-NEXT: call fastcc void @promote_avx2(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(32) [[TMP2]], <4 x i64> [[TMP0]]) #[[ATTR4]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
+; CGSCC-NEXT: store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll
index 321714849c8555..2b755b53604f4d 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll
@@ -31,26 +31,26 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %arg)
; TUNIT-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5:[0-9]+]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6:[0-9]+]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5:[0-9]+]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], <8 x i64> [[TMP0]]) #[[ATTR6:[0-9]+]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR0]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5:[0-9]+]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6:[0-9]+]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5:[0-9]+]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) #[[ATTR6:[0-9]+]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -88,26 +88,26 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %arg)
; TUNIT-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR1]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -145,26 +145,26 @@ define void @avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %arg)
; TUNIT-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR0]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR0]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -202,26 +202,26 @@ define void @avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %arg)
; TUNIT-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR1]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -257,12 +257,12 @@ define void @avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %arg)
; TUNIT-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR2:[0-9]+]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP1]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
@@ -270,11 +270,11 @@ define void @avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %arg)
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR2:[0-9]+]] {
; CGSCC-NEXT: bb:
; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -310,12 +310,12 @@ define void @avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %arg)
; TUNIT-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR1]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP1]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
@@ -323,11 +323,11 @@ define void @avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %arg)
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR1]] {
; CGSCC-NEXT: bb:
; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(64) [[TMP]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -365,26 +365,26 @@ define void @avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %arg) #4 {
; TUNIT-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR3]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; TUNIT-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; TUNIT-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR3]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; CGSCC-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; CGSCC-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
@@ -422,26 +422,26 @@ define void @avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %arg) #3 {
; TUNIT-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256
; TUNIT-SAME: (ptr nocapture nofree writeonly [[ARG:%.*]]) #[[ATTR3]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; TUNIT-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; TUNIT-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; TUNIT-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; TUNIT-NEXT: [[TMP22:%.*]] = alloca i8, i32 64, align 32
+; TUNIT-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 32 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; TUNIT-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; TUNIT-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP22]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; TUNIT-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP22]], align 64
+; TUNIT-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: inlinehint mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) uwtable
; CGSCC-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull writeonly align 2 dereferenceable(64) [[ARG:%.*]]) #[[ATTR3]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: [[TRUETMP2:%.*]] = alloca <8 x i64>, align 32
-; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
-; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP]], align 64
-; CGSCC-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TRUETMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
-; CGSCC-NEXT: [[TRUETMP4:%.*]] = load <8 x i64>, ptr [[TRUETMP2]], align 64
-; CGSCC-NEXT: store <8 x i64> [[TRUETMP4]], ptr [[ARG]], align 2
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 96, align 32
+; CGSCC-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32
+; CGSCC-NEXT: call void @llvm.memset.p0.i64(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP1]], i8 noundef 0, i64 noundef 32, i1 noundef false) #[[ATTR5]]
+; CGSCC-NEXT: [[TMP0:%.*]] = load <8 x i64>, ptr [[TMP1]], align 64
+; CGSCC-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr noalias nocapture nofree noundef nonnull writeonly align 64 dereferenceable(64) [[TMP2]], <8 x i64> [[TMP0]]) #[[ATTR6]]
+; CGSCC-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 64
+; CGSCC-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2
; CGSCC-NEXT: ret void
;
bb:
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
index 54a5b8c5640779..541c3ddafa9534 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
@@ -9,8 +9,8 @@
define void @f() {
; TUNIT-LABEL: define {{[^@]+}}@f() {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[A:%.*]] = alloca i32, align 1
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 1
+; TUNIT-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 1
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[A1]], align 1
; TUNIT-NEXT: call void @g(i32 [[TMP0]])
; TUNIT-NEXT: ret void
;
@@ -92,7 +92,7 @@ define i32 @callercaller() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@callercaller
; TUNIT-SAME: () #[[ATTR1:[0-9]+]] {
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: ret i32 3
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll
index 88483f0b468963..18c4d77cc62ab1 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/alloca-as.ll
@@ -10,17 +10,17 @@ define i32 @bar(i32 %arg) {
; TUNIT-LABEL: define {{[^@]+}}@bar
; TUNIT-SAME: (i32 [[ARG:%.*]]) {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store i32 [[ARG]], ptr [[STACK]], align 4
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[STACK]], align 4
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store i32 [[ARG]], ptr [[STACK1]], align 4
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[STACK1]], align 4
; TUNIT-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[TMP0]])
; TUNIT-NEXT: ret i32 [[CALL]]
;
; CGSCC-LABEL: define {{[^@]+}}@bar
; CGSCC-SAME: (i32 [[ARG:%.*]]) {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i32, align 4
-; CGSCC-NEXT: store i32 [[ARG]], ptr [[STACK]], align 4
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: store i32 [[ARG]], ptr [[STACK1]], align 4
; CGSCC-NEXT: [[CALL:%.*]] = call i32 @foo(i32 [[ARG]])
; CGSCC-NEXT: ret i32 [[CALL]]
;
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll
index a52bbfbe1a346b..d5d18eaa4f7980 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll
@@ -9,17 +9,26 @@ declare void @use(ptr nocapture readonly %arg)
define void @caller() {
; TUNIT-LABEL: define {{[^@]+}}@caller() {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[LEFT:%.*]] = alloca [3 x i32], align 4
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[LEFT]], align 4
-; TUNIT-NEXT: [[LEFT_B4:%.*]] = getelementptr i8, ptr [[LEFT]], i64 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[LEFT_B4]], align 4
-; TUNIT-NEXT: [[LEFT_B8:%.*]] = getelementptr i8, ptr [[LEFT]], i64 8
-; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[LEFT_B8]], align 4
+; TUNIT-NEXT: [[LEFT1:%.*]] = alloca i8, i32 2147483647, align 4
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[LEFT1]], align 4
+; TUNIT-NEXT: [[LEFT1_0_1:%.*]] = getelementptr [3 x i32], ptr [[LEFT1]], i64 0, i64 1
+; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[LEFT1_0_1]], align 4
+; TUNIT-NEXT: [[LEFT1_0_2:%.*]] = getelementptr [3 x i32], ptr [[LEFT1]], i64 0, i64 2
+; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[LEFT1_0_2]], align 4
; TUNIT-NEXT: call void @callee(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define {{[^@]+}}@caller() {
; CGSCC-NEXT: entry:
+; CGSCC-NEXT: [[LEFT1:%.*]] = alloca i8, i32 12, align 4
+; CGSCC-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[LEFT1]] to i32
+; CGSCC-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], -4
+; CGSCC-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; CGSCC-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+; CGSCC-NEXT: [[TMP4:%.*]] = ptrtoint ptr undef to i32
+; CGSCC-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], 4
+; CGSCC-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
+; CGSCC-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
; CGSCC-NEXT: call void @callee(i32 undef, i32 undef, i32 undef)
; CGSCC-NEXT: ret void
;
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
index 877071c1a3fec0..b1d35eea7b9f1b 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
@@ -15,8 +15,8 @@ define internal i32 @f(ptr byval(%struct.ss) %b, ptr byval(i32) %X, i32 %i) noun
; CHECK-NEXT: store i32 [[TMP2]], ptr [[X_PRIV]], align 4
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 8
@@ -44,12 +44,12 @@ define i32 @test(ptr %X) {
; TUNIT-LABEL: define {{[^@]+}}@test
; TUNIT-SAME: (ptr nocapture nofree nonnull readonly [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
-; TUNIT-NEXT: store i32 1, ptr [[S]], align 8
-; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S]], i32 0, i32 1
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S]], align 8
-; TUNIT-NEXT: [[S_B4:%.*]] = getelementptr i8, ptr [[S]], i64 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S_B4]], align 8
+; TUNIT-NEXT: [[S1:%.*]] = alloca i8, i32 12, align 8
+; TUNIT-NEXT: store i32 1, ptr [[S1]], align 8
+; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S1]], align 8
+; TUNIT-NEXT: [[S1_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
+; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_0_1]], align 8
; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
; TUNIT-NEXT: [[C:%.*]] = call i32 @f(i32 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret i32 [[C]]
@@ -58,8 +58,8 @@ define i32 @test(ptr %X) {
; CGSCC-LABEL: define {{[^@]+}}@test
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
-; CGSCC-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S]], i32 0, i32 1
+; CGSCC-NEXT: [[S1:%.*]] = alloca i8, i32 12, align 8
+; CGSCC-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
; CGSCC-NEXT: [[TMP0:%.*]] = load i32, ptr [[X]], align 4
; CGSCC-NEXT: [[C:%.*]] = call i32 @f(i32 noundef 1, i64 noundef 2, i32 [[TMP0]]) #[[ATTR2:[0-9]+]]
; CGSCC-NEXT: ret i32 [[C]]
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll
index 7f8aeb59fd1513..e6b21b9f4ab044 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll
@@ -39,7 +39,7 @@ define i32 @callercaller() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@callercaller
; TUNIT-SAME: () #[[ATTR0:[0-9]+]] {
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: ret i32 3
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
index b76254f6609046..1d68cae96237da 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
@@ -13,8 +13,8 @@ define internal void @f(ptr byval(%struct.ss) %b, ptr byval(i32) %X) nounwind
; CHECK-NEXT: store i32 [[TMP2]], ptr [[X_PRIV]], align 4
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 8
@@ -36,12 +36,12 @@ define i32 @test(ptr %X) {
; TUNIT-LABEL: define {{[^@]+}}@test
; TUNIT-SAME: (ptr nocapture nofree nonnull readonly [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
-; TUNIT-NEXT: store i32 1, ptr [[S]], align 8
-; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S]], i32 0, i32 1
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S]], align 8
-; TUNIT-NEXT: [[S_B4:%.*]] = getelementptr i8, ptr [[S]], i64 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S_B4]], align 8
+; TUNIT-NEXT: [[S1:%.*]] = alloca i8, i32 12, align 8
+; TUNIT-NEXT: store i32 1, ptr [[S1]], align 8
+; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S1]], align 8
+; TUNIT-NEXT: [[S1_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
+; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_0_1]], align 8
; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
; TUNIT-NEXT: call void @f(i32 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret i32 0
@@ -50,8 +50,8 @@ define i32 @test(ptr %X) {
; CGSCC-LABEL: define {{[^@]+}}@test
; CGSCC-SAME: (ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[X:%.*]]) #[[ATTR1:[0-9]+]] {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
-; CGSCC-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S]], i32 0, i32 1
+; CGSCC-NEXT: [[S1:%.*]] = alloca i8, i32 12, align 8
+; CGSCC-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
; CGSCC-NEXT: ret i32 0
;
entry:
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
index 77667875256f3c..99121f876a2268 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
@@ -13,8 +13,8 @@ define internal i32 @f(ptr byval(%struct.ss) %b) nounwind {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 8
@@ -35,8 +35,8 @@ define internal i32 @g(ptr byval(%struct.ss) align 32 %b) nounwind {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 32
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 32
@@ -55,16 +55,16 @@ define i32 @main() nounwind {
; TUNIT-LABEL: define {{[^@]+}}@main
; TUNIT-SAME: () #[[ATTR0]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
-; TUNIT-NEXT: store i32 1, ptr [[S]], align 32
-; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S]], i32 0, i32 1
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S]], align 8
-; TUNIT-NEXT: [[S_B4:%.*]] = getelementptr i8, ptr [[S]], i64 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S_B4]], align 8
+; TUNIT-NEXT: [[S1:%.*]] = alloca i8, i32 12, align 4
+; TUNIT-NEXT: store i32 1, ptr [[S1]], align 32
+; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S1]], align 8
+; TUNIT-NEXT: [[S1_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
+; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_0_1]], align 8
; TUNIT-NEXT: [[C0:%.*]] = call i32 @f(i32 [[TMP0]], i64 [[TMP1]]) #[[ATTR1:[0-9]+]]
-; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[S]], align 32
-; TUNIT-NEXT: [[S_B41:%.*]] = getelementptr i8, ptr [[S]], i64 4
-; TUNIT-NEXT: [[TMP3:%.*]] = load i64, ptr [[S_B41]], align 32
+; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[S1]], align 32
+; TUNIT-NEXT: [[S1_0_12:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
+; TUNIT-NEXT: [[TMP3:%.*]] = load i64, ptr [[S1_0_12]], align 32
; TUNIT-NEXT: [[C1:%.*]] = call i32 @g(i32 [[TMP2]], i64 [[TMP3]]) #[[ATTR1]]
; TUNIT-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]]
; TUNIT-NEXT: ret i32 [[A]]
@@ -73,8 +73,8 @@ define i32 @main() nounwind {
; CGSCC-LABEL: define {{[^@]+}}@main
; CGSCC-SAME: () #[[ATTR1:[0-9]+]] {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[S:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
-; CGSCC-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S]], i32 0, i32 1
+; CGSCC-NEXT: [[S2:%.*]] = alloca i8, i32 12, align 4
+; CGSCC-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S2]], i32 0, i32 1
; CGSCC-NEXT: [[C0:%.*]] = call i32 @f(i32 noundef 1, i64 noundef 2) #[[ATTR2:[0-9]+]]
; CGSCC-NEXT: [[C1:%.*]] = call i32 @g(i32 noundef 1, i64 noundef 2) #[[ATTR2]]
; CGSCC-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]]
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll
index ebeb24d374728f..08bb7c68ca1c1b 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll
@@ -31,7 +31,7 @@ define i32 @foo() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@foo
; TUNIT-SAME: () #[[ATTR0:[0-9]+]] {
-; TUNIT-NEXT: [[A:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: ret i32 17
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll
index 595cb37c6c93ec..2ad8ef403d88cf 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/crash.ll
@@ -100,6 +100,8 @@ define i32 @test_inf_promote_caller(i32 %arg) {
; TUNIT-LABEL: define {{[^@]+}}@test_inf_promote_caller
; TUNIT-SAME: (i32 [[ARG:%.*]]) #[[ATTR1:[0-9]+]] {
; TUNIT-NEXT: bb:
+; TUNIT-NEXT: [[TMP3:%.*]] = alloca i8, i32 8, align 8
+; TUNIT-NEXT: [[TMP14:%.*]] = alloca i8, i32 8, align 8
; TUNIT-NEXT: ret i32 0
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
index 274181fa8b9efb..6e35843bb570f6 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
@@ -82,9 +82,9 @@ define internal i64 @CaptureAStruct(ptr byval(%struct.Foo) %a) {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: [[A_PRIV:%.*]] = alloca [[STRUCT_FOO:%.*]], align 8
; CGSCC-NEXT: store i32 [[TMP0]], ptr [[A_PRIV]], align 4
-; CGSCC-NEXT: [[A_PRIV_B8:%.*]] = getelementptr i8, ptr [[A_PRIV]], i64 8
-; CGSCC-NEXT: store i64 [[TMP1]], ptr [[A_PRIV_B8]], align 8
-; CGSCC-NEXT: [[A_PTR:%.*]] = alloca ptr, align 8
+; CGSCC-NEXT: [[A_PRIV_0_1:%.*]] = getelementptr [[STRUCT_FOO]], ptr [[A_PRIV]], i64 0, i32 1
+; CGSCC-NEXT: store i64 [[TMP1]], ptr [[A_PRIV_0_1]], align 8
+; CGSCC-NEXT: [[A_PTR1:%.*]] = alloca i8, i32 8, align 8
; CGSCC-NEXT: br label [[LOOP:%.*]]
; CGSCC: loop:
; CGSCC-NEXT: [[PHI:%.*]] = phi ptr [ null, [[ENTRY:%.*]] ], [ [[A_PRIV]], [[LOOP]] ]
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll
index 2df81d6cb1832d..b3704c203d8968 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll
@@ -36,9 +36,9 @@ define internal i32 @caller(ptr %B) {
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@caller
; CGSCC-SAME: () #[[ATTR0]] {
-; CGSCC-NEXT: [[A:%.*]] = alloca i32, align 4
-; CGSCC-NEXT: [[A2:%.*]] = alloca i8, i32 0, align 4
-; CGSCC-NEXT: [[A1:%.*]] = alloca i8, i32 0, align 4
+; CGSCC-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: [[A12:%.*]] = alloca i8, i32 0, align 4
+; CGSCC-NEXT: [[A11:%.*]] = alloca i8, i32 0, align 4
; CGSCC-NEXT: ret i32 0
;
%A = alloca i32
@@ -51,13 +51,13 @@ define i32 @callercaller() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@callercaller
; TUNIT-SAME: () #[[ATTR0:[0-9]+]] {
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: ret i32 0
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@callercaller
; CGSCC-SAME: () #[[ATTR1:[0-9]+]] {
-; CGSCC-NEXT: [[B:%.*]] = alloca i32, align 4
+; CGSCC-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
; CGSCC-NEXT: [[X:%.*]] = call noundef i32 @caller() #[[ATTR2:[0-9]+]]
; CGSCC-NEXT: ret i32 [[X]]
;
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll
index 7c28de24beea27..716e5f426bbc85 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll
@@ -46,16 +46,16 @@ define internal i32 @caller(ptr %B) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write)
; TUNIT-LABEL: define {{[^@]+}}@caller
; TUNIT-SAME: (ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0]] {
-; TUNIT-NEXT: [[A:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: [[C:%.*]] = call i32 @test(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret i32 undef
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: write)
; CGSCC-LABEL: define {{[^@]+}}@caller
; CGSCC-SAME: (ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0]] {
-; CGSCC-NEXT: [[A:%.*]] = alloca i32, align 4
-; CGSCC-NEXT: [[A2:%.*]] = alloca i8, i32 0, align 4
-; CGSCC-NEXT: [[A1:%.*]] = alloca i8, i32 0, align 4
+; CGSCC-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: [[A13:%.*]] = alloca i8, i32 0, align 4
+; CGSCC-NEXT: [[A12:%.*]] = alloca i8, i32 0, align 4
; CGSCC-NEXT: [[C:%.*]] = call i32 @test(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B]]) #[[ATTR2:[0-9]+]]
; CGSCC-NEXT: ret i32 0
;
@@ -69,8 +69,8 @@ define i32 @callercaller() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@callercaller
; TUNIT-SAME: () #[[ATTR1:[0-9]+]] {
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: [[X:%.*]] = call i32 @caller(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B]]) #[[ATTR2]]
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: [[X:%.*]] = call i32 @caller(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B1]]) #[[ATTR2]]
; TUNIT-NEXT: ret i32 0
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll
index e0777f9ecee8be..24770196ebbaa3 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll
@@ -18,7 +18,7 @@ define void @foo() {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define {{[^@]+}}@foo
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[TMP:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, i32 8, align 8
; CHECK-NEXT: ret void
;
%tmp = alloca %fun_t
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll
index b6968897603b1f..4f1b5e601e68b9 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll
@@ -7,9 +7,9 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
define void @caller() #0 {
; TUNIT-LABEL: define {{[^@]+}}@caller() {
-; TUNIT-NEXT: [[X:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store i32 42, ptr [[X]], align 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 4
+; TUNIT-NEXT: [[X1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store i32 42, ptr [[X1]], align 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[X1]], align 4
; TUNIT-NEXT: call void @promote_i32_ptr(i32 [[TMP1]]), !prof [[PROF0:![0-9]+]]
; TUNIT-NEXT: ret void
;
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll
index cb5b01750aaf07..39de5947d34115 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/sret.ll
@@ -36,8 +36,9 @@ define void @f() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@f
; TUNIT-SAME: () #[[ATTR1:[0-9]+]] {
-; TUNIT-NEXT: [[R:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: call void @add(ptr noalias nocapture nofree nonnull readnone align 8 dereferenceable(8) undef, ptr noalias nocapture nofree noundef nonnull writeonly sret(i32) align 4 dereferenceable(4) [[R]]) #[[ATTR2:[0-9]+]]
+; TUNIT-NEXT: [[R1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: [[PAIR2:%.*]] = alloca i8, i32 8, align 8
+; TUNIT-NEXT: call void @add(ptr noalias nocapture nofree nonnull readnone align 8 dereferenceable(8) undef, ptr noalias nocapture nofree noundef nonnull writeonly sret(i32) align 4 dereferenceable(4) [[R1]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll b/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll
index 932dcb5f2a91ef..8993b164905276 100644
--- a/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll
+++ b/llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll
@@ -34,8 +34,8 @@ define dso_local void @foo(i32 %N) {
; TUNIT-LABEL: define {{[^@]+}}@foo
; TUNIT-SAME: (i32 [[N:%.*]]) {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: [[P:%.*]] = alloca float, align 4
+; TUNIT-NEXT: [[N_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: [[P2:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 3, ptr noundef nonnull @.omp_outlined., ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(4) undef, ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(4) undef, i64 undef)
; TUNIT-NEXT: ret void
;
@@ -64,44 +64,44 @@ define internal void @.omp_outlined.(ptr noalias %.global_tid., ptr noalias %.bo
; TUNIT-LABEL: define {{[^@]+}}@.omp_outlined.
; TUNIT-SAME: (ptr noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], ptr noalias nocapture nofree noundef nonnull readnone align 4 dereferenceable(4) [[N:%.*]], ptr noalias nocapture nofree noundef nonnull readnone align 4 dereferenceable(4) [[P:%.*]], i64 [[Q:%.*]]) {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8
+; TUNIT-NEXT: [[Q_ADDR1:%.*]] = alloca i8, i32 8, align 8
; TUNIT-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
; TUNIT-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
; TUNIT-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
; TUNIT-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store i64 4617315517961601024, ptr [[Q_ADDR]], align 8
+; TUNIT-NEXT: store i64 4617315517961601024, ptr [[Q_ADDR1]], align 8
; TUNIT-NEXT: br label [[OMP_PRECOND_THEN:%.*]]
; TUNIT: omp.precond.then:
; TUNIT-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
; TUNIT-NEXT: store i32 4, ptr [[DOTOMP_UB]], align 4
; TUNIT-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
; TUNIT-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-; TUNIT-NEXT: [[TRUETMP5:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
-; TUNIT-NEXT: call void @__kmpc_for_static_init_4(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TRUETMP5]], i32 noundef 34, ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_IS_LAST]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_LB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_UB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_STRIDE]], i32 noundef 1, i32 noundef 1)
-; TUNIT-NEXT: [[TRUETMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-; TUNIT-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TRUETMP6]], 4
+; TUNIT-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
+; TUNIT-NEXT: call void @__kmpc_for_static_init_4(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TMP5]], i32 noundef 34, ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_IS_LAST]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_LB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_UB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_STRIDE]], i32 noundef 1, i32 noundef 1)
+; TUNIT-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+; TUNIT-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP6]], 4
; TUNIT-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
; TUNIT: cond.true:
; TUNIT-NEXT: br label [[COND_END:%.*]]
; TUNIT: cond.false:
-; TUNIT-NEXT: [[TRUETMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+; TUNIT-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
; TUNIT-NEXT: br label [[COND_END]]
; TUNIT: cond.end:
-; TUNIT-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TRUETMP7]], [[COND_FALSE]] ]
+; TUNIT-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
; TUNIT-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-; TUNIT-NEXT: [[TRUETMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+; TUNIT-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
; TUNIT-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
; TUNIT: omp.inner.for.cond:
-; TUNIT-NEXT: [[DOTOMP_IV_0:%.*]] = phi i32 [ [[TRUETMP8]], [[COND_END]] ], [ [[ADD11:%.*]], [[OMP_INNER_FOR_INC:%.*]] ]
-; TUNIT-NEXT: [[TRUETMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-; TUNIT-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[DOTOMP_IV_0]], [[TRUETMP9]]
+; TUNIT-NEXT: [[DOTOMP_IV_0:%.*]] = phi i32 [ [[TMP8]], [[COND_END]] ], [ [[ADD11:%.*]], [[OMP_INNER_FOR_INC:%.*]] ]
+; TUNIT-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+; TUNIT-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[DOTOMP_IV_0]], [[TMP9]]
; TUNIT-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], label [[OMP_INNER_FOR_BODY:%.*]]
; TUNIT: omp.inner.for.cond.cleanup:
; TUNIT-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
; TUNIT: omp.inner.for.body:
; TUNIT-NEXT: [[ADD10:%.*]] = add nsw i32 [[DOTOMP_IV_0]], 2
-; TUNIT-NEXT: [[TRUETMP11:%.*]] = load double, ptr [[Q_ADDR]], align 8
-; TUNIT-NEXT: call void @bar(i32 [[ADD10]], float nofpclass(nan inf zero sub nnorm) 3.000000e+00, double [[TRUETMP11]])
+; TUNIT-NEXT: [[TMP11:%.*]] = load double, ptr [[Q_ADDR1]], align 8
+; TUNIT-NEXT: call void @bar(i32 [[ADD10]], float nofpclass(nan inf zero sub nnorm) 3.000000e+00, double [[TMP11]])
; TUNIT-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
; TUNIT: omp.body.continue:
; TUNIT-NEXT: br label [[OMP_INNER_FOR_INC]]
@@ -111,8 +111,8 @@ define internal void @.omp_outlined.(ptr noalias %.global_tid., ptr noalias %.bo
; TUNIT: omp.inner.for.end:
; TUNIT-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
; TUNIT: omp.loop.exit:
-; TUNIT-NEXT: [[TRUETMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
-; TUNIT-NEXT: call void @__kmpc_for_static_fini(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TRUETMP12]])
+; TUNIT-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
+; TUNIT-NEXT: call void @__kmpc_for_static_fini(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TMP12]])
; TUNIT-NEXT: br label [[OMP_PRECOND_END:%.*]]
; TUNIT: omp.precond.end:
; TUNIT-NEXT: ret void
@@ -120,12 +120,12 @@ define internal void @.omp_outlined.(ptr noalias %.global_tid., ptr noalias %.bo
; CGSCC-LABEL: define {{[^@]+}}@.omp_outlined.
; CGSCC-SAME: (ptr noalias nocapture nofree readonly [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[N:%.*]], ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[P:%.*]], i64 [[Q:%.*]]) {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[Q_ADDR:%.*]] = alloca i64, align 8
+; CGSCC-NEXT: [[Q_ADDR1:%.*]] = alloca i8, i32 8, align 8
; CGSCC-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
; CGSCC-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
; CGSCC-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
; CGSCC-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-; CGSCC-NEXT: store i64 4617315517961601024, ptr [[Q_ADDR]], align 8
+; CGSCC-NEXT: store i64 4617315517961601024, ptr [[Q_ADDR1]], align 8
; CGSCC-NEXT: [[TMP:%.*]] = load i32, ptr [[N]], align 4
; CGSCC-NEXT: [[SUB3:%.*]] = add nsw i32 [[TMP]], -3
; CGSCC-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP]], 2
@@ -135,33 +135,33 @@ define internal void @.omp_outlined.(ptr noalias %.global_tid., ptr noalias %.bo
; CGSCC-NEXT: store i32 [[SUB3]], ptr [[DOTOMP_UB]], align 4
; CGSCC-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
; CGSCC-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-; CGSCC-NEXT: [[TRUETMP5:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
-; CGSCC-NEXT: call void @__kmpc_for_static_init_4(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TRUETMP5]], i32 noundef 34, ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_IS_LAST]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_LB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_UB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_STRIDE]], i32 noundef 1, i32 noundef 1)
-; CGSCC-NEXT: [[TRUETMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-; CGSCC-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TRUETMP6]], [[SUB3]]
+; CGSCC-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
+; CGSCC-NEXT: call void @__kmpc_for_static_init_4(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TMP5]], i32 noundef 34, ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_IS_LAST]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_LB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_UB]], ptr noundef nonnull align 4 dereferenceable(4) [[DOTOMP_STRIDE]], i32 noundef 1, i32 noundef 1)
+; CGSCC-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+; CGSCC-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP6]], [[SUB3]]
; CGSCC-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
; CGSCC: cond.true:
; CGSCC-NEXT: br label [[COND_END:%.*]]
; CGSCC: cond.false:
-; CGSCC-NEXT: [[TRUETMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+; CGSCC-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
; CGSCC-NEXT: br label [[COND_END]]
; CGSCC: cond.end:
-; CGSCC-NEXT: [[COND:%.*]] = phi i32 [ [[SUB3]], [[COND_TRUE]] ], [ [[TRUETMP7]], [[COND_FALSE]] ]
+; CGSCC-NEXT: [[COND:%.*]] = phi i32 [ [[SUB3]], [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
; CGSCC-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-; CGSCC-NEXT: [[TRUETMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+; CGSCC-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
; CGSCC-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
; CGSCC: omp.inner.for.cond:
-; CGSCC-NEXT: [[DOTOMP_IV_0:%.*]] = phi i32 [ [[TRUETMP8]], [[COND_END]] ], [ [[ADD11:%.*]], [[OMP_INNER_FOR_INC:%.*]] ]
-; CGSCC-NEXT: [[TRUETMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-; CGSCC-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[DOTOMP_IV_0]], [[TRUETMP9]]
+; CGSCC-NEXT: [[DOTOMP_IV_0:%.*]] = phi i32 [ [[TMP8]], [[COND_END]] ], [ [[ADD11:%.*]], [[OMP_INNER_FOR_INC:%.*]] ]
+; CGSCC-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+; CGSCC-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[DOTOMP_IV_0]], [[TMP9]]
; CGSCC-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], label [[OMP_INNER_FOR_BODY:%.*]]
; CGSCC: omp.inner.for.cond.cleanup:
; CGSCC-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
; CGSCC: omp.inner.for.body:
; CGSCC-NEXT: [[ADD10:%.*]] = add nsw i32 [[DOTOMP_IV_0]], 2
-; CGSCC-NEXT: [[TRUETMP10:%.*]] = load float, ptr [[P]], align 4
-; CGSCC-NEXT: [[TRUETMP11:%.*]] = load double, ptr [[Q_ADDR]], align 8
-; CGSCC-NEXT: call void @bar(i32 [[ADD10]], float [[TRUETMP10]], double [[TRUETMP11]])
+; CGSCC-NEXT: [[TMP10:%.*]] = load float, ptr [[P]], align 4
+; CGSCC-NEXT: [[TMP11:%.*]] = load double, ptr [[Q_ADDR1]], align 8
+; CGSCC-NEXT: call void @bar(i32 [[ADD10]], float [[TMP10]], double [[TMP11]])
; CGSCC-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
; CGSCC: omp.body.continue:
; CGSCC-NEXT: br label [[OMP_INNER_FOR_INC]]
@@ -171,8 +171,8 @@ define internal void @.omp_outlined.(ptr noalias %.global_tid., ptr noalias %.bo
; CGSCC: omp.inner.for.end:
; CGSCC-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
; CGSCC: omp.loop.exit:
-; CGSCC-NEXT: [[TRUETMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
-; CGSCC-NEXT: call void @__kmpc_for_static_fini(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TRUETMP12]])
+; CGSCC-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
+; CGSCC-NEXT: call void @__kmpc_for_static_fini(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 [[TMP12]])
; CGSCC-NEXT: br label [[OMP_PRECOND_END]]
; CGSCC: omp.precond.end:
; CGSCC-NEXT: ret void
diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll
index 15a1ed0e62763e..10fa92d17eb3bc 100644
--- a/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll
+++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll
@@ -62,8 +62,8 @@ define void @caller(i1 %C) personality ptr @__gxx_personality_v0 {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@caller
; TUNIT-SAME: (i1 [[C:%.*]]) #[[ATTR1:[0-9]+]] personality ptr @__gxx_personality_v0 {
-; TUNIT-NEXT: [[Q:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: [[W:%.*]] = call align 4 ptr @incdec(i1 noundef [[C]], ptr noalias nofree noundef nonnull writeonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[Q]]) #[[ATTR2:[0-9]+]]
+; TUNIT-NEXT: [[Q1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: [[W:%.*]] = call align 4 ptr @incdec(i1 noundef [[C]], ptr noalias nofree noundef nonnull writeonly align 4 dereferenceable(4) "no-capture-maybe-returned" [[Q1]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: br label [[OK:%.*]]
; TUNIT: OK:
; TUNIT-NEXT: br label [[RET:%.*]]
diff --git a/llvm/test/Transforms/Attributor/align.ll b/llvm/test/Transforms/Attributor/align.ll
index 9880e53fd43a59..4480dd6d714276 100644
--- a/llvm/test/Transforms/Attributor/align.ll
+++ b/llvm/test/Transforms/Attributor/align.ll
@@ -1039,35 +1039,35 @@ define internal ptr @aligned_8_return(ptr %a, i1 %c1, i1 %c2) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@aligned_8_return
; TUNIT-SAME: (ptr noalias nofree readnone align 16 "no-capture-maybe-returned" [[A:%.*]], i1 noundef [[C1:%.*]], i1 [[C2:%.*]]) #[[ATTR10]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca ptr, align 8
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 8, align 8
; TUNIT-NEXT: br i1 [[C1]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
; TUNIT-NEXT: [[GEP:%.*]] = getelementptr i8, ptr @G, i32 8
; TUNIT-NEXT: [[SEL:%.*]] = select i1 [[C2]], ptr [[A]], ptr [[GEP]]
-; TUNIT-NEXT: store ptr [[SEL]], ptr [[STACK]], align 8
+; TUNIT-NEXT: store ptr [[SEL]], ptr [[STACK1]], align 8
; TUNIT-NEXT: br label [[END:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store ptr @G, ptr [[STACK]], align 8
+; TUNIT-NEXT: store ptr @G, ptr [[STACK1]], align 8
; TUNIT-NEXT: br label [[END]]
; TUNIT: end:
-; TUNIT-NEXT: [[L:%.*]] = load ptr, ptr [[STACK]], align 8
+; TUNIT-NEXT: [[L:%.*]] = load ptr, ptr [[STACK1]], align 8
; TUNIT-NEXT: ret ptr [[L]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@aligned_8_return
; CGSCC-SAME: (ptr noalias nofree readnone align 16 "no-capture-maybe-returned" [[A:%.*]], i1 noundef [[C1:%.*]], i1 [[C2:%.*]]) #[[ATTR11]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca ptr, align 8
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 8, align 8
; CGSCC-NEXT: br i1 [[C1]], label [[T:%.*]], label [[F:%.*]]
; CGSCC: t:
; CGSCC-NEXT: [[GEP:%.*]] = getelementptr i8, ptr @G, i32 8
; CGSCC-NEXT: [[SEL:%.*]] = select i1 [[C2]], ptr [[A]], ptr [[GEP]]
-; CGSCC-NEXT: store ptr [[SEL]], ptr [[STACK]], align 8
+; CGSCC-NEXT: store ptr [[SEL]], ptr [[STACK1]], align 8
; CGSCC-NEXT: br label [[END:%.*]]
; CGSCC: f:
-; CGSCC-NEXT: store ptr @G, ptr [[STACK]], align 8
+; CGSCC-NEXT: store ptr @G, ptr [[STACK1]], align 8
; CGSCC-NEXT: br label [[END]]
; CGSCC: end:
-; CGSCC-NEXT: [[L:%.*]] = load ptr, ptr [[STACK]], align 8
+; CGSCC-NEXT: [[L:%.*]] = load ptr, ptr [[STACK1]], align 8
; CGSCC-NEXT: ret ptr [[L]]
;
%stack = alloca ptr
diff --git a/llvm/test/Transforms/Attributor/allocator.ll b/llvm/test/Transforms/Attributor/allocator.ll
index 7072fd5b9e78d3..6c8d3d6553f41e 100644
--- a/llvm/test/Transforms/Attributor/allocator.ll
+++ b/llvm/test/Transforms/Attributor/allocator.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 2
-; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,TUNIT
-; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC
+; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -debug-only=attributor -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,TUNIT
+; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -debug-only=attributor -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC
%struct.Foo = type { i32, i32, i8 }
@@ -49,11 +49,11 @@ define dso_local void @positive_malloc_1(ptr noundef %val) #0 {
; CHECK-LABEL: define dso_local void @positive_malloc_1
; CHECK-SAME: (ptr nocapture nofree noundef readonly [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR]], align 8
+; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR1]], align 8
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 12)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F2]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 10
; CHECK-NEXT: store i32 [[ADD]], ptr [[CALL]], align 4
@@ -86,11 +86,11 @@ define dso_local void @positive_malloc_2(ptr noundef %val) #0 {
; CHECK-LABEL: define dso_local void @positive_malloc_2
; CHECK-SAME: (ptr nocapture nofree noundef readonly [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR]], align 8
+; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: [[F3:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR1]], align 8
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 60)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F3]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[CALL]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 4
@@ -125,19 +125,19 @@ define dso_local ptr @negative_test_escaping_pointer(i32 noundef %val) #0 {
; CHECK-LABEL: define dso_local ptr @negative_test_escaping_pointer
; CHECK-SAME: (i32 noundef [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4
-; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR]], align 4
+; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR1]], align 4
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 16)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
-; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F2]], align 8
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F2]], align 8
; CHECK-NEXT: store i32 2, ptr [[TMP0]], align 8
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 10, [[VAL]]
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[F]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[F2]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
; CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], [[ADD]]
; CHECK-NEXT: store i32 [[ADD2]], ptr [[TMP1]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[F]], align 8
+; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[F2]], align 8
; CHECK-NEXT: ret ptr [[TMP3]]
;
entry:
@@ -164,30 +164,38 @@ entry:
;TODO: The allocation can be reduced here.
;However, the offsets (load/store etc.) Need to be changed.
; Function Attrs: noinline nounwind uwtable
-define dso_local { i64, ptr } @positive_test_not_a_single_start_offset(i32 noundef %val) #0 {
-; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
-; CHECK-LABEL: define dso_local { i64, ptr } @positive_test_not_a_single_start_offset
-; CHECK-SAME: (i32 noundef [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
+define dso_local void @positive_test_not_a_single_start_offset(i32 noundef %val) #0 {
+; CHECK-LABEL: define dso_local void @positive_test_not_a_single_start_offset
+; CHECK-SAME: (i32 noundef [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RETVAL:%.*]] = alloca [[STRUCT_FOO:%.*]], align 8
-; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4
-; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR]], align 4
-; CHECK-NEXT: store i32 2, ptr [[RETVAL]], align 8
-; CHECK-NEXT: [[FIELD3:%.*]] = getelementptr inbounds [[STRUCT_FOO]], ptr [[RETVAL]], i32 0, i32 2
-; CHECK-NEXT: store ptr [[VAL_ADDR]], ptr [[FIELD3]], align 8
-; CHECK-NEXT: [[TMP0:%.*]] = load { i64, ptr }, ptr [[RETVAL]], align 8
-; CHECK-NEXT: ret { i64, ptr } [[TMP0]]
+; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 5, align 4
+; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR1]], align 4
+; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 2, [[VAL]]
+; CHECK-NEXT: store i32 [[MUL]], ptr [[F2]], align 4
+; CHECK-NEXT: [[CALL:%.*]] = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(17) @.str, i32 noundef [[MUL]])
+; CHECK-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[F2]], i32 0, i32 2
+; CHECK-NEXT: [[CALL3:%.*]] = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(17) @.str, i32 noundef 67)
+; CHECK-NEXT: ret void
;
entry:
- %retval = alloca %struct.Foo, align 8
%val.addr = alloca i32, align 4
+ %f = alloca %struct.Foo, align 4
store i32 %val, ptr %val.addr, align 4
- %field1 = getelementptr inbounds %struct.Foo, ptr %retval, i32 0, i32 0
- store i32 2, ptr %field1, align 8
- %field3 = getelementptr inbounds %struct.Foo, ptr %retval, i32 0, i32 2
- store ptr %val.addr, ptr %field3, align 8
- %0 = load { i64, ptr }, ptr %retval, align 8
- ret { i64, ptr } %0
+ %0 = load i32, ptr %val.addr, align 4
+ %mul = mul nsw i32 2, %0
+ %a = getelementptr inbounds %struct.Foo, ptr %f, i32 0, i32 0
+ store i32 %mul, ptr %a, align 4
+ %a1 = getelementptr inbounds %struct.Foo, ptr %f, i32 0, i32 0
+ %1 = load i32, ptr %a1, align 4
+ %call = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %1)
+ %c = getelementptr inbounds %struct.Foo, ptr %f, i32 0, i32 2
+ store i8 67, ptr %c, align 4
+ %c2 = getelementptr inbounds %struct.Foo, ptr %f, i32 0, i32 2
+ %2 = load i8, ptr %c2, align 4
+ %conv = sext i8 %2 to i32
+ %call3 = call i32 (ptr, ...) @printf(ptr noundef @.str, i32 noundef %conv)
+ ret void
}
; Function Attrs: noinline nounwind uwtable
@@ -231,15 +239,15 @@ define dso_local void @baz(ptr noundef %val, i32 noundef %arrayLength) #0 {
; CHECK-LABEL: define dso_local void @baz
; CHECK-SAME: (ptr nocapture nofree noundef readonly [[VAL:%.*]], i32 noundef [[ARRAYLENGTH:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: [[ARRAYLENGTH_ADDR:%.*]] = alloca i32, align 4
-; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR]], align 8
-; CHECK-NEXT: store i32 [[ARRAYLENGTH]], ptr [[ARRAYLENGTH_ADDR]], align 4
+; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: [[ARRAYLENGTH_ADDR2:%.*]] = alloca i8, i32 4, align 4
+; CHECK-NEXT: [[F3:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR1]], align 8
+; CHECK-NEXT: store i32 [[ARRAYLENGTH]], ptr [[ARRAYLENGTH_ADDR2]], align 4
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[ARRAYLENGTH]] to i64
; CHECK-NEXT: [[MUL:%.*]] = mul i64 4, [[CONV]]
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef [[MUL]])
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F3]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[CALL]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 4
@@ -275,37 +283,37 @@ entry:
define dso_local void @positive_test_reduce_array_allocation_2() #0 {
; CHECK-LABEL: define dso_local void @positive_test_reduce_array_allocation_2() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ARRAY:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[ARRAY1:%.*]] = alloca i8, i32 8, align 8
+; CHECK-NEXT: [[I2:%.*]] = alloca i8, i32 4, align 4
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 40000)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[ARRAY]], align 8
-; CHECK-NEXT: store i32 0, ptr [[I]], align 4
+; CHECK-NEXT: store ptr [[CALL]], ptr [[ARRAY1]], align 8
+; CHECK-NEXT: store i32 0, ptr [[I2]], align 4
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10000
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I2]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[CALL]], i64 [[IDXPROM]]
; CHECK-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: br label [[FOR_INC:%.*]]
; CHECK: for.inc:
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 2
-; CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+; CHECK-NEXT: store i32 [[ADD]], ptr [[I2]], align 4
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
-; CHECK-NEXT: store i32 0, ptr [[I]], align 4
+; CHECK-NEXT: store i32 0, ptr [[I2]], align 4
; CHECK-NEXT: br label [[FOR_COND1:%.*]]
; CHECK: for.cond1:
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP4]], 10000
; CHECK-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END9:%.*]]
; CHECK: for.body3:
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP5]] to i64
; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[CALL]], i64 [[IDXPROM4]]
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4
@@ -313,28 +321,28 @@ define dso_local void @positive_test_reduce_array_allocation_2() #0 {
; CHECK-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX5]], align 4
; CHECK-NEXT: br label [[FOR_INC7:%.*]]
; CHECK: for.inc7:
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP7]], 2
-; CHECK-NEXT: store i32 [[ADD8]], ptr [[I]], align 4
+; CHECK-NEXT: store i32 [[ADD8]], ptr [[I2]], align 4
; CHECK-NEXT: br label [[FOR_COND1]]
; CHECK: for.end9:
-; CHECK-NEXT: store i32 0, ptr [[I]], align 4
+; CHECK-NEXT: store i32 0, ptr [[I2]], align 4
; CHECK-NEXT: br label [[FOR_COND10:%.*]]
; CHECK: for.cond10:
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[CMP11:%.*]] = icmp slt i32 [[TMP8]], 10000
; CHECK-NEXT: br i1 [[CMP11]], label [[FOR_BODY12:%.*]], label [[FOR_END18:%.*]]
; CHECK: for.body12:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP9]] to i64
; CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, ptr [[CALL]], i64 [[IDXPROM13]]
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4
; CHECK-NEXT: [[CALL15:%.*]] = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(17) @.str, i32 noundef [[TMP10]])
; CHECK-NEXT: br label [[FOR_INC16:%.*]]
; CHECK: for.inc16:
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP11]], 2
-; CHECK-NEXT: store i32 [[ADD17]], ptr [[I]], align 4
+; CHECK-NEXT: store i32 [[ADD17]], ptr [[I2]], align 4
; CHECK-NEXT: br label [[FOR_COND10]]
; CHECK: for.end18:
; CHECK-NEXT: ret void
@@ -499,6 +507,58 @@ entry:
ret void
}
+define dso_local void @alloca_array_multi_offset(){
+; CHECK: Function Attrs: nofree norecurse nosync nounwind memory(none)
+; CHECK-LABEL: define dso_local void @alloca_array_multi_offset
+; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[I2:%.*]] = alloca i8, i32 4, align 4
+; CHECK-NEXT: store i32 0, ptr [[I2]], align 4
+; CHECK-NEXT: br label [[FOR_COND:%.*]]
+; CHECK: for.cond:
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I2]], align 4
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: br label [[FOR_INC:%.*]]
+; CHECK: for.inc:
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I2]], align 4
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 2
+; CHECK-NEXT: store i32 [[ADD]], ptr [[I2]], align 4
+; CHECK-NEXT: br label [[FOR_COND]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
+entry:
+ %arr = alloca i8, i32 10, align 4
+ %i = alloca i32, align 4
+ store i32 0, ptr %i, align 4
+ br label %for.cond
+
+for.cond:
+ %0 = load i32, ptr %i, align 4
+ %cmp = icmp slt i32 %0, 10
+ br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+ %1 = load i32, ptr %i, align 4
+ %2 = load ptr, ptr %arr, align 8
+ %3 = load i32, ptr %i, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %2, i32 %3
+ store i32 %1, ptr %arrayidx, align 4
+ br label %for.inc
+
+for.inc:
+ %4 = load i32, ptr %i, align 4
+ %add = add nsw i32 %4, 2
+ store i32 %add, ptr %i, align 4
+ br label %for.cond
+
+for.end:
+ ret void
+
+}
+
declare external void @external_call(ptr)
@@ -511,7 +571,7 @@ declare i32 @printf(ptr noundef, ...) #1
; Function Attrs: nounwind allocsize(0)
declare noalias ptr @malloc(i64 noundef) #1
;.
-; CHECK: attributes #[[ATTR0]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }
+; CHECK: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind memory(none) }
;.
; CHECK: [[META0:![0-9]+]] = !{!1}
; CHECK: [[META1:![0-9]+]] = !{i64 2, i64 3, i1 false}
diff --git a/llvm/test/Transforms/Attributor/call-simplify-pointer-info.ll b/llvm/test/Transforms/Attributor/call-simplify-pointer-info.ll
index 5bb795911ce408..b145c3b7201868 100644
--- a/llvm/test/Transforms/Attributor/call-simplify-pointer-info.ll
+++ b/llvm/test/Transforms/Attributor/call-simplify-pointer-info.ll
@@ -36,8 +36,12 @@ define i8 @call_simplifiable_1() {
; TUNIT-LABEL: define {{[^@]+}}@call_simplifiable_1
; TUNIT-SAME: () #[[ATTR0:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[BYTES:%.*]] = alloca [1024 x i8], align 16
-; TUNIT-NEXT: [[I0:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 2
+; TUNIT-NEXT: [[BYTES1:%.*]] = alloca i8, align 16
+; TUNIT-NEXT: [[I0:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 2
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[I0]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 2
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i8 2, ptr [[TMP2]], align 1
; TUNIT-NEXT: ret i8 2
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
@@ -93,9 +97,17 @@ define i8 @call_simplifiable_2() {
; TUNIT-LABEL: define {{[^@]+}}@call_simplifiable_2
; TUNIT-SAME: () #[[ATTR0]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[BYTES:%.*]] = alloca [1024 x i8], align 16
-; TUNIT-NEXT: [[I0:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 2
-; TUNIT-NEXT: [[I1:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 3
+; TUNIT-NEXT: [[BYTES1:%.*]] = alloca i8, i32 2, align 16
+; TUNIT-NEXT: [[I0:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 2
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[I0]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 2
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i8 2, ptr [[TMP2]], align 1
+; TUNIT-NEXT: [[I1:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 3
+; TUNIT-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[I1]] to i32
+; TUNIT-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 2
+; TUNIT-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr
+; TUNIT-NEXT: store i8 3, ptr [[TMP5]], align 1
; TUNIT-NEXT: ret i8 4
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
@@ -125,8 +137,12 @@ define i8 @call_simplifiable_3() {
; TUNIT-LABEL: define {{[^@]+}}@call_simplifiable_3
; TUNIT-SAME: () #[[ATTR0]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[BYTES:%.*]] = alloca [1024 x i8], align 16
-; TUNIT-NEXT: [[I2:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 2
+; TUNIT-NEXT: [[BYTES1:%.*]] = alloca i8, align 16
+; TUNIT-NEXT: [[I2:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 2
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[I2]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 2
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i8 2, ptr [[TMP2]], align 1
; TUNIT-NEXT: ret i8 2
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
@@ -198,12 +214,24 @@ define i8 @call_partially_simplifiable_1() {
; TUNIT-LABEL: define {{[^@]+}}@call_partially_simplifiable_1
; TUNIT-SAME: () #[[ATTR0]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[BYTES:%.*]] = alloca [1024 x i8], align 16
-; TUNIT-NEXT: [[I2:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 2
+; TUNIT-NEXT: [[BYTES1:%.*]] = alloca i8, i32 3, align 16
+; TUNIT-NEXT: [[I2:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 2
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[I2]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 2
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i8 2, ptr [[TMP2]], align 1
; TUNIT-NEXT: store i8 2, ptr [[I2]], align 2
-; TUNIT-NEXT: [[I3:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 3
+; TUNIT-NEXT: [[I3:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 3
+; TUNIT-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[I3]] to i32
+; TUNIT-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 1
+; TUNIT-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr
+; TUNIT-NEXT: store i8 3, ptr [[TMP5]], align 1
; TUNIT-NEXT: store i8 3, ptr [[I3]], align 1
-; TUNIT-NEXT: [[I4:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 4
+; TUNIT-NEXT: [[I4:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 4
+; TUNIT-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[I4]] to i32
+; TUNIT-NEXT: [[TMP7:%.*]] = sub i32 [[TMP6]], 3
+; TUNIT-NEXT: [[TMP8:%.*]] = inttoptr i32 [[TMP7]] to ptr
+; TUNIT-NEXT: store i8 4, ptr [[TMP8]], align 1
; TUNIT-NEXT: [[R:%.*]] = call i8 @sum_two_different_loads(ptr nocapture nofree noundef nonnull readonly align 2 dereferenceable(1022) [[I2]], ptr nocapture nofree noundef nonnull readonly dereferenceable(1021) [[I3]]) #[[ATTR3]]
; TUNIT-NEXT: ret i8 [[R]]
;
@@ -239,13 +267,25 @@ define i8 @call_partially_simplifiable_2(i1 %cond) {
; TUNIT-LABEL: define {{[^@]+}}@call_partially_simplifiable_2
; TUNIT-SAME: (i1 [[COND:%.*]]) #[[ATTR2:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[BYTES:%.*]] = alloca [1024 x i8], align 16
-; TUNIT-NEXT: [[I51:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 51
-; TUNIT-NEXT: [[I52:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 52
+; TUNIT-NEXT: [[BYTES1:%.*]] = alloca i8, i32 4, align 16
+; TUNIT-NEXT: [[I51:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 51
+; TUNIT-NEXT: [[I52:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 52
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[I52]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], 52
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i8 2, ptr [[TMP2]], align 1
; TUNIT-NEXT: store i8 2, ptr [[I52]], align 4
-; TUNIT-NEXT: [[I53:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 53
+; TUNIT-NEXT: [[I53:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 53
+; TUNIT-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[I53]] to i32
+; TUNIT-NEXT: [[TMP4:%.*]] = sub i32 [[TMP3]], 50
+; TUNIT-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr
+; TUNIT-NEXT: store i8 3, ptr [[TMP5]], align 1
; TUNIT-NEXT: store i8 3, ptr [[I53]], align 1
-; TUNIT-NEXT: [[I54:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES]], i64 0, i64 54
+; TUNIT-NEXT: [[I54:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BYTES1]], i64 0, i64 54
+; TUNIT-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[I54]] to i32
+; TUNIT-NEXT: [[TMP7:%.*]] = sub i32 [[TMP6]], 53
+; TUNIT-NEXT: [[TMP8:%.*]] = inttoptr i32 [[TMP7]] to ptr
+; TUNIT-NEXT: store i8 4, ptr [[TMP8]], align 1
; TUNIT-NEXT: [[SEL:%.*]] = select i1 [[COND]], ptr [[I51]], ptr [[I52]]
; TUNIT-NEXT: [[R:%.*]] = call i8 @sum_two_different_loads(ptr nocapture nofree nonnull readonly dereferenceable(972) [[SEL]], ptr nocapture nofree noundef nonnull readonly dereferenceable(971) [[I53]]) #[[ATTR3]]
; TUNIT-NEXT: ret i8 [[R]]
diff --git a/llvm/test/Transforms/Attributor/callbacks.ll b/llvm/test/Transforms/Attributor/callbacks.ll
index 6ace218afcf36b..66140cc429afa9 100644
--- a/llvm/test/Transforms/Attributor/callbacks.ll
+++ b/llvm/test/Transforms/Attributor/callbacks.ll
@@ -18,11 +18,11 @@ define void @t0_caller(ptr %a) {
; TUNIT-SAME: (ptr align 256 [[A:%.*]]) {
; TUNIT-NEXT: entry:
; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 32
-; TUNIT-NEXT: [[C:%.*]] = alloca ptr, align 64
+; TUNIT-NEXT: [[C1:%.*]] = alloca i8, i32 8, align 64
; TUNIT-NEXT: [[PTR:%.*]] = alloca i32, align 128
; TUNIT-NEXT: store i32 42, ptr [[B]], align 32
-; TUNIT-NEXT: store ptr [[B]], ptr [[C]], align 64
-; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t0_callback_broker(ptr noundef align 4294967296 null, ptr noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr noundef nonnull @t0_callback_callee, ptr align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; TUNIT-NEXT: store ptr [[B]], ptr [[C1]], align 64
+; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t0_callback_broker(ptr noundef align 4294967296 null, ptr noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr noundef nonnull @t0_callback_callee, ptr align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C1]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define {{[^@]+}}@t0_caller
@@ -90,12 +90,16 @@ define void @t1_caller(ptr noalias %a) {
; TUNIT-LABEL: define {{[^@]+}}@t1_caller
; TUNIT-SAME: (ptr noalias nocapture align 256 [[A:%.*]]) {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 32
-; TUNIT-NEXT: [[C:%.*]] = alloca ptr, align 64
-; TUNIT-NEXT: [[PTR:%.*]] = alloca i32, align 128
-; TUNIT-NEXT: store i32 42, ptr [[B]], align 32
-; TUNIT-NEXT: store ptr [[B]], ptr [[C]], align 64
-; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t1_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t1_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 -2147483645, align 32
+; TUNIT-NEXT: [[C2:%.*]] = alloca i8, i32 8, align 64
+; TUNIT-NEXT: [[PTR3:%.*]] = alloca i8, i32 2147483647, align 128
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[B1]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], -2147483647
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i32 42, ptr [[TMP2]], align 4
+; TUNIT-NEXT: store i32 42, ptr [[B1]], align 32
+; TUNIT-NEXT: store ptr [[B1]], ptr [[C2]], align 64
+; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t1_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR3]], ptr nocapture noundef nonnull @t1_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C2]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define {{[^@]+}}@t1_caller
@@ -103,10 +107,10 @@ define void @t1_caller(ptr noalias %a) {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: [[B:%.*]] = alloca i32, align 32
; CGSCC-NEXT: [[C:%.*]] = alloca ptr, align 64
-; CGSCC-NEXT: [[PTR:%.*]] = alloca i32, align 128
+; CGSCC-NEXT: [[PTR1:%.*]] = alloca i8, i32 2147483647, align 128
; CGSCC-NEXT: store i32 42, ptr [[B]], align 32
; CGSCC-NEXT: store ptr [[B]], ptr [[C]], align 64
-; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t1_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t1_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t1_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR1]], ptr nocapture noundef nonnull @t1_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
; CGSCC-NEXT: ret void
;
entry:
@@ -163,12 +167,16 @@ define void @t2_caller(ptr noalias %a) {
; TUNIT-LABEL: define {{[^@]+}}@t2_caller
; TUNIT-SAME: (ptr noalias nocapture align 256 [[A:%.*]]) {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 32
-; TUNIT-NEXT: [[C:%.*]] = alloca ptr, align 64
-; TUNIT-NEXT: [[PTR:%.*]] = alloca i32, align 128
-; TUNIT-NEXT: store i32 42, ptr [[B]], align 32
-; TUNIT-NEXT: store ptr [[B]], ptr [[C]], align 64
-; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t2_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t2_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 -2147483645, align 32
+; TUNIT-NEXT: [[C2:%.*]] = alloca i8, i32 8, align 64
+; TUNIT-NEXT: [[PTR3:%.*]] = alloca i8, i32 2147483647, align 128
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[B1]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], -2147483647
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i32 42, ptr [[TMP2]], align 4
+; TUNIT-NEXT: store i32 42, ptr [[B1]], align 32
+; TUNIT-NEXT: store ptr [[B1]], ptr [[C2]], align 64
+; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t2_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR3]], ptr nocapture noundef nonnull @t2_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C2]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define {{[^@]+}}@t2_caller
@@ -176,10 +184,10 @@ define void @t2_caller(ptr noalias %a) {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: [[B:%.*]] = alloca i32, align 32
; CGSCC-NEXT: [[C:%.*]] = alloca ptr, align 64
-; CGSCC-NEXT: [[PTR:%.*]] = alloca i32, align 128
+; CGSCC-NEXT: [[PTR1:%.*]] = alloca i8, i32 2147483647, align 128
; CGSCC-NEXT: store i32 42, ptr [[B]], align 32
; CGSCC-NEXT: store ptr [[B]], ptr [[C]], align 64
-; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t2_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t2_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t2_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR1]], ptr nocapture noundef nonnull @t2_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
; CGSCC-NEXT: ret void
;
entry:
@@ -236,13 +244,17 @@ define void @t3_caller(ptr noalias %a) {
; TUNIT-LABEL: define {{[^@]+}}@t3_caller
; TUNIT-SAME: (ptr noalias nocapture align 256 [[A:%.*]]) {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 32
-; TUNIT-NEXT: [[C:%.*]] = alloca ptr, align 64
-; TUNIT-NEXT: [[PTR:%.*]] = alloca i32, align 128
-; TUNIT-NEXT: store i32 42, ptr [[B]], align 32
-; TUNIT-NEXT: store ptr [[B]], ptr [[C]], align 64
-; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
-; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 -2147483645, align 32
+; TUNIT-NEXT: [[C2:%.*]] = alloca i8, i32 8, align 64
+; TUNIT-NEXT: [[PTR3:%.*]] = alloca i8, i32 2147483647, align 128
+; TUNIT-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[B1]] to i32
+; TUNIT-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], -2147483647
+; TUNIT-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
+; TUNIT-NEXT: store i32 42, ptr [[TMP2]], align 4
+; TUNIT-NEXT: store i32 42, ptr [[B1]], align 32
+; TUNIT-NEXT: store ptr [[B1]], ptr [[C2]], align 64
+; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR3]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C2]])
+; TUNIT-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR3]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 undef, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C2]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define {{[^@]+}}@t3_caller
@@ -250,11 +262,11 @@ define void @t3_caller(ptr noalias %a) {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: [[B:%.*]] = alloca i32, align 32
; CGSCC-NEXT: [[C:%.*]] = alloca ptr, align 64
-; CGSCC-NEXT: [[PTR:%.*]] = alloca i32, align 128
+; CGSCC-NEXT: [[PTR1:%.*]] = alloca i8, i32 2147483647, align 128
; CGSCC-NEXT: store i32 42, ptr [[B]], align 32
; CGSCC-NEXT: store ptr [[B]], ptr [[C]], align 64
-; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
-; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR1]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
+; CGSCC-NEXT: call void (ptr, ptr, ptr, ...) @t3_callback_broker(ptr noundef align 4294967296 null, ptr noalias nocapture noundef nonnull align 128 dereferenceable(4) [[PTR1]], ptr nocapture noundef nonnull @t3_callback_callee, ptr nocapture align 256 [[A]], i64 noundef 99, ptr noalias nocapture nofree noundef nonnull readonly align 64 dereferenceable(8) [[C]])
; CGSCC-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/Attributor/heap_to_stack.ll b/llvm/test/Transforms/Attributor/heap_to_stack.ll
index 4f267a7abe305e..c64dce6e449479 100644
--- a/llvm/test/Transforms/Attributor/heap_to_stack.ll
+++ b/llvm/test/Transforms/Attributor/heap_to_stack.ll
@@ -501,15 +501,15 @@ define i32 @malloc_in_loop(i32 %arg) {
; CHECK-LABEL: define {{[^@]+}}@malloc_in_loop
; CHECK-SAME: (i32 [[ARG:%.*]]) {
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[I2:%.*]] = alloca i8, i32 4, align 4
; CHECK-NEXT: [[I1:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: [[I11:%.*]] = alloca i8, i32 0, align 8
-; CHECK-NEXT: store i32 [[ARG]], ptr [[I]], align 4
+; CHECK-NEXT: [[I13:%.*]] = alloca i8, i32 0, align 8
+; CHECK-NEXT: store i32 [[ARG]], ptr [[I2]], align 4
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[I3:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[I3:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[I4:%.*]] = add nsw i32 [[I3]], -1
-; CHECK-NEXT: store i32 [[I4]], ptr [[I]], align 4
+; CHECK-NEXT: store i32 [[I4]], ptr [[I2]], align 4
; CHECK-NEXT: [[I5:%.*]] = icmp sgt i32 [[I4]], 0
; CHECK-NEXT: br i1 [[I5]], label [[BB6:%.*]], label [[BB9:%.*]]
; CHECK: bb6:
diff --git a/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll b/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
index 476e65b4e46538..e2885c1ffd3a9a 100644
--- a/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
+++ b/llvm/test/Transforms/Attributor/heap_to_stack_gpu.ll
@@ -451,15 +451,15 @@ define i32 @malloc_in_loop(i32 %arg) {
; CHECK-LABEL: define {{[^@]+}}@malloc_in_loop
; CHECK-SAME: (i32 [[ARG:%.*]]) {
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[I2:%.*]] = alloca i8, i32 4, align 4
; CHECK-NEXT: [[I1:%.*]] = alloca ptr, align 8
-; CHECK-NEXT: [[I11:%.*]] = alloca i8, i32 0, align 8
-; CHECK-NEXT: store i32 [[ARG]], ptr [[I]], align 4
+; CHECK-NEXT: [[I13:%.*]] = alloca i8, i32 0, align 8
+; CHECK-NEXT: store i32 [[ARG]], ptr [[I2]], align 4
; CHECK-NEXT: br label [[BB2:%.*]]
; CHECK: bb2:
-; CHECK-NEXT: [[I3:%.*]] = load i32, ptr [[I]], align 4
+; CHECK-NEXT: [[I3:%.*]] = load i32, ptr [[I2]], align 4
; CHECK-NEXT: [[I4:%.*]] = add nsw i32 [[I3]], -1
-; CHECK-NEXT: store i32 [[I4]], ptr [[I]], align 4
+; CHECK-NEXT: store i32 [[I4]], ptr [[I2]], align 4
; CHECK-NEXT: [[I5:%.*]] = icmp sgt i32 [[I4]], 0
; CHECK-NEXT: br i1 [[I5]], label [[BB6:%.*]], label [[BB9:%.*]]
; CHECK: bb6:
diff --git a/llvm/test/Transforms/Attributor/internal-noalias.ll b/llvm/test/Transforms/Attributor/internal-noalias.ll
index 0dba6853e0c8fc..62048de8d0c1de 100644
--- a/llvm/test/Transforms/Attributor/internal-noalias.ll
+++ b/llvm/test/Transforms/Attributor/internal-noalias.ll
@@ -92,10 +92,10 @@ define dso_local i32 @visible_local(ptr %A) #0 {
; TUNIT-LABEL: define {{[^@]+}}@visible_local
; TUNIT-SAME: (ptr nocapture nofree readonly [[A:%.*]]) #[[ATTR1:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store i32 5, ptr [[B]], align 4
-; TUNIT-NEXT: [[CALL1:%.*]] = call i32 @noalias_args(ptr nocapture nofree noundef readonly align 4 [[A]], ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[B]]) #[[ATTR4]]
-; TUNIT-NEXT: [[CALL2:%.*]] = call i32 @noalias_args_argmem(ptr nocapture nofree noundef readonly align 4 [[A]], ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[B]]) #[[ATTR4]]
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store i32 5, ptr [[B1]], align 4
+; TUNIT-NEXT: [[CALL1:%.*]] = call i32 @noalias_args(ptr nocapture nofree noundef readonly align 4 [[A]], ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[B1]]) #[[ATTR4]]
+; TUNIT-NEXT: [[CALL2:%.*]] = call i32 @noalias_args_argmem(ptr nocapture nofree noundef readonly align 4 [[A]], ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[B1]]) #[[ATTR4]]
; TUNIT-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL1]], [[CALL2]]
; TUNIT-NEXT: ret i32 [[ADD]]
;
@@ -142,7 +142,7 @@ define i32 @visible_local_2() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@visible_local_2
; TUNIT-SAME: () #[[ATTR2:[0-9]+]] {
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: ret i32 10
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
@@ -179,8 +179,8 @@ define i32 @visible_local_3() {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@visible_local_3
; TUNIT-SAME: () #[[ATTR2]] {
-; TUNIT-NEXT: [[B:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: [[CALL:%.*]] = call i32 @noalias_args_argmem_rn(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B]]) #[[ATTR5:[0-9]+]]
+; TUNIT-NEXT: [[B1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: [[CALL:%.*]] = call i32 @noalias_args_argmem_rn(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[B1]]) #[[ATTR5:[0-9]+]]
; TUNIT-NEXT: ret i32 5
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
diff --git a/llvm/test/Transforms/Attributor/noalias.ll b/llvm/test/Transforms/Attributor/noalias.ll
index 00ca83d0c5d688..71710c10947bcd 100644
--- a/llvm/test/Transforms/Attributor/noalias.ll
+++ b/llvm/test/Transforms/Attributor/noalias.ll
@@ -189,21 +189,37 @@ define ptr @test6() nounwind uwtable ssp {
; TUNIT: Function Attrs: nounwind ssp uwtable
; TUNIT-LABEL: define {{[^@]+}}@test6
; TUNIT-SAME: () #[[ATTR3:[0-9]+]] {
-; TUNIT-NEXT: [[X:%.*]] = alloca [2 x i8], align 1
-; TUNIT-NEXT: store i8 97, ptr [[X]], align 1
-; TUNIT-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8], ptr [[X]], i64 0, i64 1
+; TUNIT-NEXT: [[X1:%.*]] = alloca i8, i32 -2147483647, align 1
+; TUNIT-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[X1]] to i32
+; TUNIT-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], -2147483647
+; TUNIT-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; TUNIT-NEXT: store i8 97, ptr [[TMP3]], align 1
+; TUNIT-NEXT: store i8 97, ptr [[X1]], align 1
+; TUNIT-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8], ptr [[X1]], i64 0, i64 1
+; TUNIT-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i32
+; TUNIT-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], -2147483647
+; TUNIT-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
+; TUNIT-NEXT: store i8 0, ptr [[TMP6]], align 1
; TUNIT-NEXT: store i8 0, ptr [[ARRAYIDX1]], align 1
-; TUNIT-NEXT: [[CALL:%.*]] = call noalias ptr @strdup(ptr noalias nocapture noundef nonnull dereferenceable(2) [[X]]) #[[ATTR2]]
+; TUNIT-NEXT: [[CALL:%.*]] = call noalias ptr @strdup(ptr noalias nocapture noundef nonnull dereferenceable(2) [[X1]]) #[[ATTR2]]
; TUNIT-NEXT: ret ptr [[CALL]]
;
; CGSCC: Function Attrs: nounwind ssp uwtable
; CGSCC-LABEL: define {{[^@]+}}@test6
; CGSCC-SAME: () #[[ATTR4:[0-9]+]] {
-; CGSCC-NEXT: [[X:%.*]] = alloca [2 x i8], align 1
-; CGSCC-NEXT: store i8 97, ptr [[X]], align 1
-; CGSCC-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8], ptr [[X]], i64 0, i64 1
+; CGSCC-NEXT: [[X1:%.*]] = alloca i8, i32 -2147483647, align 1
+; CGSCC-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[X1]] to i32
+; CGSCC-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], -2147483647
+; CGSCC-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; CGSCC-NEXT: store i8 97, ptr [[TMP3]], align 1
+; CGSCC-NEXT: store i8 97, ptr [[X1]], align 1
+; CGSCC-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x i8], ptr [[X1]], i64 0, i64 1
+; CGSCC-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i32
+; CGSCC-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], -2147483647
+; CGSCC-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
+; CGSCC-NEXT: store i8 0, ptr [[TMP6]], align 1
; CGSCC-NEXT: store i8 0, ptr [[ARRAYIDX1]], align 1
-; CGSCC-NEXT: [[CALL:%.*]] = call noalias ptr @strdup(ptr noalias nocapture noundef nonnull dereferenceable(2) [[X]]) #[[ATTR3]]
+; CGSCC-NEXT: [[CALL:%.*]] = call noalias ptr @strdup(ptr noalias nocapture noundef nonnull dereferenceable(2) [[X1]]) #[[ATTR3]]
; CGSCC-NEXT: ret ptr [[CALL]]
;
%x = alloca [2 x i8], align 1
@@ -399,10 +415,10 @@ declare void @use_nocapture(ptr nocapture)
declare void @use(ptr)
define void @test12_1() {
; CHECK-LABEL: define {{[^@]+}}@test12_1() {
-; CHECK-NEXT: [[A:%.*]] = alloca i8, align 4
+; CHECK-NEXT: [[A1:%.*]] = alloca i8, i32 2147483647, align 4
; CHECK-NEXT: [[B:%.*]] = tail call noalias ptr @malloc(i64 noundef 4)
-; CHECK-NEXT: tail call void @use_nocapture(ptr noalias nocapture noundef nonnull align 4 dereferenceable(1) [[A]])
-; CHECK-NEXT: tail call void @use_nocapture(ptr noalias nocapture noundef nonnull align 4 dereferenceable(1) [[A]])
+; CHECK-NEXT: tail call void @use_nocapture(ptr noalias nocapture noundef nonnull align 4 dereferenceable(1) [[A1]])
+; CHECK-NEXT: tail call void @use_nocapture(ptr noalias nocapture noundef nonnull align 4 dereferenceable(1) [[A1]])
; CHECK-NEXT: tail call void @use_nocapture(ptr noalias nocapture [[B]])
; CHECK-NEXT: tail call void @use_nocapture(ptr noalias nocapture [[B]])
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/Attributor/nocapture-2.ll b/llvm/test/Transforms/Attributor/nocapture-2.ll
index 1e5e9da19909f6..96fd887f75fac9 100644
--- a/llvm/test/Transforms/Attributor/nocapture-2.ll
+++ b/llvm/test/Transforms/Attributor/nocapture-2.ll
@@ -46,21 +46,21 @@ define i32 @is_null_control(ptr %p) #0 {
; CHECK-LABEL: define i32 @is_null_control
; CHECK-SAME: (ptr nofree [[P:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[RETVAL1:%.*]] = alloca i8, i32 4, align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[P]], null
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4
+; CHECK-NEXT: store i32 1, ptr [[RETVAL1]], align 4
; CHECK-NEXT: br label [[RETURN:%.*]]
; CHECK: if.end:
; CHECK-NEXT: br label [[IF_END3:%.*]]
; CHECK: if.then2:
; CHECK-NEXT: unreachable
; CHECK: if.end3:
-; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
+; CHECK-NEXT: store i32 0, ptr [[RETVAL1]], align 4
; CHECK-NEXT: br label [[RETURN]]
; CHECK: return:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[RETVAL1]], align 4
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
@@ -737,15 +737,15 @@ define ptr @b64613_a(ptr noundef %p) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define noundef ptr @b64613_a
; TUNIT-SAME: (ptr nofree noundef readnone returned "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR11:[0-9]+]] {
-; TUNIT-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 1
-; TUNIT-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 1
+; TUNIT-NEXT: [[P_ADDR1:%.*]] = alloca i8, i32 8, align 1
+; TUNIT-NEXT: store ptr [[P]], ptr [[P_ADDR1]], align 1
; TUNIT-NEXT: ret ptr [[P]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define noundef ptr @b64613_a
; CGSCC-SAME: (ptr nofree noundef readnone returned "no-capture-maybe-returned" [[P:%.*]]) #[[ATTR12:[0-9]+]] {
-; CGSCC-NEXT: [[P_ADDR:%.*]] = alloca ptr, align 1
-; CGSCC-NEXT: store ptr [[P]], ptr [[P_ADDR]], align 1
+; CGSCC-NEXT: [[P_ADDR1:%.*]] = alloca i8, i32 8, align 1
+; CGSCC-NEXT: store ptr [[P]], ptr [[P_ADDR1]], align 1
; CGSCC-NEXT: ret ptr [[P]]
;
%p.addr = alloca ptr, align 1
@@ -757,19 +757,27 @@ define ptr @b64613_b(ptr noundef %p, i32 %i) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define ptr @b64613_b
; TUNIT-SAME: (ptr nofree noundef [[P:%.*]], i32 [[I:%.*]]) #[[ATTR11]] {
-; TUNIT-NEXT: [[P_ADDR:%.*]] = alloca <2 x ptr>, align 1
-; TUNIT-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR]], i32 [[I]]
+; TUNIT-NEXT: [[P_ADDR1:%.*]] = alloca i8, i32 16, align 1
+; TUNIT-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR1]], i32 [[I]]
+; TUNIT-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[G]] to i32
+; TUNIT-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 2147483639
+; TUNIT-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; TUNIT-NEXT: store ptr [[P]], ptr [[TMP3]], align 8
; TUNIT-NEXT: store ptr [[P]], ptr [[G]], align 1
-; TUNIT-NEXT: [[R:%.*]] = load ptr, ptr [[P_ADDR]], align 1
+; TUNIT-NEXT: [[R:%.*]] = load ptr, ptr [[P_ADDR1]], align 1
; TUNIT-NEXT: ret ptr [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define ptr @b64613_b
; CGSCC-SAME: (ptr nofree noundef [[P:%.*]], i32 [[I:%.*]]) #[[ATTR12]] {
-; CGSCC-NEXT: [[P_ADDR:%.*]] = alloca <2 x ptr>, align 1
-; CGSCC-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR]], i32 [[I]]
+; CGSCC-NEXT: [[P_ADDR1:%.*]] = alloca i8, i32 16, align 1
+; CGSCC-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR1]], i32 [[I]]
+; CGSCC-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[G]] to i32
+; CGSCC-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 2147483639
+; CGSCC-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; CGSCC-NEXT: store ptr [[P]], ptr [[TMP3]], align 8
; CGSCC-NEXT: store ptr [[P]], ptr [[G]], align 1
-; CGSCC-NEXT: [[R:%.*]] = load ptr, ptr [[P_ADDR]], align 1
+; CGSCC-NEXT: [[R:%.*]] = load ptr, ptr [[P_ADDR1]], align 1
; CGSCC-NEXT: ret ptr [[R]]
;
%p.addr = alloca <2 x ptr>, align 1
@@ -782,16 +790,24 @@ define void @b64613_positive(ptr noundef %p, i32 %i) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define void @b64613_positive
; TUNIT-SAME: (ptr nocapture nofree noundef [[P:%.*]], i32 [[I:%.*]]) #[[ATTR11]] {
-; TUNIT-NEXT: [[P_ADDR:%.*]] = alloca <2 x ptr>, align 1
-; TUNIT-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR]], i32 [[I]]
+; TUNIT-NEXT: [[P_ADDR1:%.*]] = alloca i8, i32 16, align 1
+; TUNIT-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR1]], i32 [[I]]
+; TUNIT-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[G]] to i32
+; TUNIT-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 2147483639
+; TUNIT-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; TUNIT-NEXT: store ptr [[P]], ptr [[TMP3]], align 8
; TUNIT-NEXT: store ptr [[P]], ptr [[G]], align 1
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define void @b64613_positive
; CGSCC-SAME: (ptr nocapture nofree noundef [[P:%.*]], i32 [[I:%.*]]) #[[ATTR13:[0-9]+]] {
-; CGSCC-NEXT: [[P_ADDR:%.*]] = alloca <2 x ptr>, align 1
-; CGSCC-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR]], i32 [[I]]
+; CGSCC-NEXT: [[P_ADDR1:%.*]] = alloca i8, i32 16, align 1
+; CGSCC-NEXT: [[G:%.*]] = getelementptr i8, ptr [[P_ADDR1]], i32 [[I]]
+; CGSCC-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[G]] to i32
+; CGSCC-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 2147483639
+; CGSCC-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP2]] to ptr
+; CGSCC-NEXT: store ptr [[P]], ptr [[TMP3]], align 8
; CGSCC-NEXT: store ptr [[P]], ptr [[G]], align 1
; CGSCC-NEXT: ret void
;
diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll
index d2d11e0276c4dc..b495fc73918a3b 100644
--- a/llvm/test/Transforms/Attributor/nofpclass.ll
+++ b/llvm/test/Transforms/Attributor/nofpclass.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --version 2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --check-globals --version 2
; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,TUNIT
; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC
@@ -687,9 +687,9 @@ define float @pass_nofpclass_inf_through_memory(float nofpclass(inf) %arg) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define float @pass_nofpclass_inf_through_memory
; TUNIT-SAME: (float nofpclass(inf) [[ARG:%.*]]) #[[ATTR3]] {
-; TUNIT-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; TUNIT-NEXT: store float [[ARG]], ptr [[ALLOCA]], align 4
-; TUNIT-NEXT: [[RET:%.*]] = call float @returned_load(ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[ALLOCA]]) #[[ATTR21:[0-9]+]]
+; TUNIT-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store float [[ARG]], ptr [[ALLOCA1]], align 4
+; TUNIT-NEXT: [[RET:%.*]] = call float @returned_load(ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[ALLOCA1]]) #[[ATTR21:[0-9]+]]
; TUNIT-NEXT: ret float [[RET]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
@@ -2520,15 +2520,15 @@ define float @call_through_memory0(float nofpclass(nan) %val) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define nofpclass(nan) float @call_through_memory0
; TUNIT-SAME: (float returned nofpclass(nan) [[VAL:%.*]]) #[[ATTR3]] {
-; TUNIT-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; TUNIT-NEXT: store float [[VAL]], ptr [[ALLOCA]], align 4
+; TUNIT-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store float [[VAL]], ptr [[ALLOCA1]], align 4
; TUNIT-NEXT: ret float [[VAL]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define float @call_through_memory0
; CGSCC-SAME: (float nofpclass(nan) [[VAL:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; CGSCC-NEXT: store float [[VAL]], ptr [[ALLOCA]], align 4
+; CGSCC-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: store float [[VAL]], ptr [[ALLOCA1]], align 4
; CGSCC-NEXT: [[THROUGH_MEMORY:%.*]] = call float @through_memory0(float nofpclass(nan) [[VAL]]) #[[ATTR19]]
; CGSCC-NEXT: ret float [[THROUGH_MEMORY]]
;
@@ -2542,17 +2542,17 @@ define float @call_through_memory1(float nofpclass(nan) %val) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define float @call_through_memory1
; TUNIT-SAME: (float nofpclass(nan) [[VAL:%.*]]) #[[ATTR3]] {
-; TUNIT-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; TUNIT-NEXT: store float [[VAL]], ptr [[ALLOCA]], align 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load float, ptr [[ALLOCA]], align 4
+; TUNIT-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store float [[VAL]], ptr [[ALLOCA1]], align 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load float, ptr [[ALLOCA1]], align 4
; TUNIT-NEXT: [[THROUGH_MEMORY:%.*]] = call float @through_memory1(float [[TMP1]]) #[[ATTR21]]
; TUNIT-NEXT: ret float [[THROUGH_MEMORY]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define float @call_through_memory1
; CGSCC-SAME: (float nofpclass(nan) [[VAL:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; CGSCC-NEXT: store float [[VAL]], ptr [[ALLOCA]], align 4
+; CGSCC-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: store float [[VAL]], ptr [[ALLOCA1]], align 4
; CGSCC-NEXT: [[THROUGH_MEMORY:%.*]] = call float @through_memory1(float nofpclass(nan) [[VAL]]) #[[ATTR19]]
; CGSCC-NEXT: ret float [[THROUGH_MEMORY]]
;
@@ -2565,16 +2565,16 @@ define float @call_through_memory1(float nofpclass(nan) %val) {
define float @call_through_memory2(float nofpclass(nan) %val) {
; TUNIT-LABEL: define float @call_through_memory2
; TUNIT-SAME: (float nofpclass(nan) [[VAL:%.*]]) {
-; TUNIT-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; TUNIT-NEXT: store float [[VAL]], ptr [[ALLOCA]], align 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load float, ptr [[ALLOCA]], align 4
+; TUNIT-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store float [[VAL]], ptr [[ALLOCA1]], align 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load float, ptr [[ALLOCA1]], align 4
; TUNIT-NEXT: [[THROUGH_MEMORY:%.*]] = call float @through_memory2(float [[TMP1]])
; TUNIT-NEXT: ret float [[THROUGH_MEMORY]]
;
; CGSCC-LABEL: define float @call_through_memory2
; CGSCC-SAME: (float nofpclass(nan) [[VAL:%.*]]) {
-; CGSCC-NEXT: [[ALLOCA:%.*]] = alloca float, align 4
-; CGSCC-NEXT: store float [[VAL]], ptr [[ALLOCA]], align 4
+; CGSCC-NEXT: [[ALLOCA1:%.*]] = alloca i8, i32 4, align 4
+; CGSCC-NEXT: store float [[VAL]], ptr [[ALLOCA1]], align 4
; CGSCC-NEXT: [[THROUGH_MEMORY:%.*]] = call float @through_memory2(float nofpclass(nan) [[VAL]])
; CGSCC-NEXT: ret float [[THROUGH_MEMORY]]
;
@@ -2689,3 +2689,51 @@ attributes #2 = { "denormal-fp-math"="ieee,preserve-sign" }
attributes #3 = { "denormal-fp-math"="positive-zero,positive-zero" }
attributes #4 = { "denormal-fp-math"="positive-zero,ieee" }
attributes #5 = { "denormal-fp-math"="ieee,positive-zero" }
+;.
+; TUNIT: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
+; TUNIT: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; TUNIT: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
+; TUNIT: attributes #[[ATTR3]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }
+; TUNIT: attributes #[[ATTR4]] = { mustprogress nofree nosync nounwind willreturn memory(none) }
+; TUNIT: attributes #[[ATTR5]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) }
+; TUNIT: attributes #[[ATTR6]] = { mustprogress nofree norecurse nounwind willreturn memory(argmem: readwrite) }
+; TUNIT: attributes #[[ATTR7]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) }
+; TUNIT: attributes #[[ATTR8]] = { mustprogress nofree norecurse nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
+; TUNIT: attributes #[[ATTR9]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="positive-zero,positive-zero" }
+; TUNIT: attributes #[[ATTR10]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="preserve-sign,preserve-sign" }
+; TUNIT: attributes #[[ATTR11]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="ieee,preserve-sign" }
+; TUNIT: attributes #[[ATTR12]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="positive-zero,ieee" }
+; TUNIT: attributes #[[ATTR13]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="preserve-sign,ieee" }
+; TUNIT: attributes #[[ATTR14]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="ieee,positive-zero" }
+; TUNIT: attributes #[[ATTR15]] = { memory(readwrite, argmem: none) }
+; TUNIT: attributes #[[ATTR16]] = { norecurse }
+; TUNIT: attributes #[[ATTR17]] = { nounwind willreturn }
+; TUNIT: attributes #[[ATTR18]] = { nofree willreturn memory(write) }
+; TUNIT: attributes #[[ATTR19]] = { nofree nosync nounwind willreturn memory(none) }
+; TUNIT: attributes #[[ATTR20]] = { nofree willreturn }
+; TUNIT: attributes #[[ATTR21]] = { nofree nosync nounwind willreturn memory(read) }
+; TUNIT: attributes #[[ATTR22]] = { nofree nosync willreturn }
+;.
+; CGSCC: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
+; CGSCC: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; CGSCC: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
+; CGSCC: attributes #[[ATTR3]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }
+; CGSCC: attributes #[[ATTR4]] = { mustprogress nofree nosync nounwind willreturn memory(none) }
+; CGSCC: attributes #[[ATTR5]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) }
+; CGSCC: attributes #[[ATTR6]] = { mustprogress nofree norecurse nounwind willreturn memory(argmem: readwrite) }
+; CGSCC: attributes #[[ATTR7]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) }
+; CGSCC: attributes #[[ATTR8]] = { mustprogress nofree norecurse nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
+; CGSCC: attributes #[[ATTR9]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="positive-zero,positive-zero" }
+; CGSCC: attributes #[[ATTR10]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="preserve-sign,preserve-sign" }
+; CGSCC: attributes #[[ATTR11]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="ieee,preserve-sign" }
+; CGSCC: attributes #[[ATTR12]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="positive-zero,ieee" }
+; CGSCC: attributes #[[ATTR13]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="preserve-sign,ieee" }
+; CGSCC: attributes #[[ATTR14]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "denormal-fp-math"="ieee,positive-zero" }
+; CGSCC: attributes #[[ATTR15]] = { memory(readwrite, argmem: none) }
+; CGSCC: attributes #[[ATTR16]] = { norecurse }
+; CGSCC: attributes #[[ATTR17]] = { nounwind willreturn }
+; CGSCC: attributes #[[ATTR18]] = { nofree willreturn memory(write) }
+; CGSCC: attributes #[[ATTR19]] = { nofree nosync willreturn }
+; CGSCC: attributes #[[ATTR20]] = { nofree willreturn }
+; CGSCC: attributes #[[ATTR21]] = { nofree willreturn memory(read) }
+;.
diff --git a/llvm/test/Transforms/Attributor/norecurse.ll b/llvm/test/Transforms/Attributor/norecurse.ll
index b0034e465018ed..ce4a411a6c65f0 100644
--- a/llvm/test/Transforms/Attributor/norecurse.ll
+++ b/llvm/test/Transforms/Attributor/norecurse.ll
@@ -161,8 +161,8 @@ define void @f(i32 %x) {
; TUNIT-LABEL: define {{[^@]+}}@f
; TUNIT-SAME: (i32 [[X:%.*]]) #[[ATTR1]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store i32 [[X]], ptr [[X_ADDR]], align 4
+; TUNIT-NEXT: [[X_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store i32 [[X]], ptr [[X_ADDR1]], align 4
; TUNIT-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[X]], 0
; TUNIT-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; TUNIT: if.then:
@@ -174,7 +174,7 @@ define void @f(i32 %x) {
; CGSCC-LABEL: define {{[^@]+}}@f
; CGSCC-SAME: (i32 [[X:%.*]]) #[[ATTR0]] {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
+; CGSCC-NEXT: [[X_ADDR12:%.*]] = alloca i8, i32 4, align 4
; CGSCC-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[X]], 0
; CGSCC-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CGSCC: if.then:
diff --git a/llvm/test/Transforms/Attributor/openmp_parallel.ll b/llvm/test/Transforms/Attributor/openmp_parallel.ll
index f4867ad60ae519..4a82ee7c2b5dab 100644
--- a/llvm/test/Transforms/Attributor/openmp_parallel.ll
+++ b/llvm/test/Transforms/Attributor/openmp_parallel.ll
@@ -23,12 +23,12 @@ define dso_local void @func(ptr nocapture %a, ptr %b, i32 %N) local_unnamed_addr
; TUNIT-LABEL: define {{[^@]+}}@func
; TUNIT-SAME: (ptr nocapture nofree writeonly [[A:%.*]], ptr nocapture nofree readonly [[B:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
-; TUNIT-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
-; TUNIT-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
-; TUNIT-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
-; TUNIT-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB2]], i32 noundef 3, ptr noundef nonnull @.omp_outlined., ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(4) undef, ptr noalias nocapture nofree noundef nonnull readonly align 8 dereferenceable(8) [[A_ADDR]], ptr noalias nocapture nofree noundef nonnull readonly align 8 dereferenceable(8) [[B_ADDR]])
+; TUNIT-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 8, align 8
+; TUNIT-NEXT: [[B_ADDR2:%.*]] = alloca i8, i32 8, align 8
+; TUNIT-NEXT: [[N_ADDR3:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: store ptr [[A]], ptr [[A_ADDR1]], align 8
+; TUNIT-NEXT: store ptr [[B]], ptr [[B_ADDR2]], align 8
+; TUNIT-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB2]], i32 noundef 3, ptr noundef nonnull @.omp_outlined., ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(4) undef, ptr noalias nocapture nofree noundef nonnull readonly align 8 dereferenceable(8) [[A_ADDR1]], ptr noalias nocapture nofree noundef nonnull readonly align 8 dereferenceable(8) [[B_ADDR2]])
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: nounwind uwtable
diff --git a/llvm/test/Transforms/Attributor/pointer-info.ll b/llvm/test/Transforms/Attributor/pointer-info.ll
index 6afdbdaee317c5..9406c7b2efc48a 100644
--- a/llvm/test/Transforms/Attributor/pointer-info.ll
+++ b/llvm/test/Transforms/Attributor/pointer-info.ll
@@ -10,10 +10,14 @@ define void @foo(ptr %ptr) {
; TUNIT-LABEL: define {{[^@]+}}@foo
; TUNIT-SAME: (ptr nocapture nofree readnone [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[TMP0:%.*]] = alloca [[STRUCT_TEST_A:%.*]], align 8
+; TUNIT-NEXT: [[TMP0:%.*]] = alloca i8, i32 8, align 8
; TUNIT-NEXT: br label [[CALL_BR:%.*]]
; TUNIT: call.br:
-; TUNIT-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_TEST_A]], ptr [[TMP0]], i64 0, i32 2
+; TUNIT-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_TEST_A:%.*]], ptr [[TMP0]], i64 0, i32 2
+; TUNIT-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[TMP1]] to i32
+; TUNIT-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], 16
+; TUNIT-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
+; TUNIT-NEXT: store ptr [[PTR]], ptr [[TMP4]], align 8
; TUNIT-NEXT: tail call void @bar(ptr noalias nocapture nofree noundef nonnull readonly byval([[STRUCT_TEST_A]]) align 8 dereferenceable(24) [[TMP0]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret void
;
diff --git a/llvm/test/Transforms/Attributor/value-simplify-assume.ll b/llvm/test/Transforms/Attributor/value-simplify-assume.ll
index 0ccad5cf21e271..c58fff733890e3 100644
--- a/llvm/test/Transforms/Attributor/value-simplify-assume.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify-assume.ll
@@ -120,19 +120,19 @@ define i1 @keep_assume_4c_nr() norecurse {
; TUNIT: Function Attrs: norecurse
; TUNIT-LABEL: define {{[^@]+}}@keep_assume_4c_nr
; TUNIT-SAME: () #[[ATTR2]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR7]]
-; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; TUNIT-NEXT: ret i1 true
;
; CGSCC: Function Attrs: norecurse
; CGSCC-LABEL: define {{[^@]+}}@keep_assume_4c_nr
; CGSCC-SAME: () #[[ATTR2]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 true, ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; CGSCC-NEXT: store i1 true, ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR8]]
-; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; CGSCC-NEXT: ret i1 true
;
%stack = alloca i1
@@ -166,16 +166,16 @@ define i1 @drop_assume_1_nr(i1 %arg) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@drop_assume_1_nr
; TUNIT-SAME: (i1 returned [[ARG:%.*]]) #[[ATTR4:[0-9]+]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR7]]
; TUNIT-NEXT: ret i1 [[ARG]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CGSCC-LABEL: define {{[^@]+}}@drop_assume_1_nr
; CGSCC-SAME: (i1 returned [[ARG:%.*]]) #[[ATTR4:[0-9]+]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR8]]
; CGSCC-NEXT: ret i1 [[ARG]]
;
@@ -244,19 +244,19 @@ define i1 @keep_assume_4_nr(i1 %arg) norecurse {
; TUNIT: Function Attrs: norecurse
; TUNIT-LABEL: define {{[^@]+}}@keep_assume_4_nr
; TUNIT-SAME: (i1 returned [[ARG:%.*]]) #[[ATTR2]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR7]]
-; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; TUNIT-NEXT: ret i1 [[ARG]]
;
; CGSCC: Function Attrs: norecurse
; CGSCC-LABEL: define {{[^@]+}}@keep_assume_4_nr
; CGSCC-SAME: (i1 returned [[ARG:%.*]]) #[[ATTR2]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR8]]
-; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; CGSCC-NEXT: ret i1 [[ARG]]
;
%stack = alloca i1
@@ -271,8 +271,8 @@ define i1 @assume_1_nr(i1 %arg, i1 %cond) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_1_nr
; TUNIT-SAME: (i1 returned [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR7]]
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
@@ -285,8 +285,8 @@ define i1 @assume_1_nr(i1 %arg, i1 %cond) norecurse {
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CGSCC-LABEL: define {{[^@]+}}@assume_1_nr
; CGSCC-SAME: (i1 returned [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR8]]
; CGSCC-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; CGSCC: t:
@@ -342,32 +342,32 @@ define i1 @assume_2_nr(i1 %arg, i1 %cond) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_2_nr
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR7]]
; TUNIT-NEXT: ret i1 [[L]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CGSCC-LABEL: define {{[^@]+}}@assume_2_nr
; CGSCC-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; CGSCC-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; CGSCC: t:
-; CGSCC-NEXT: store i1 true, ptr [[STACK]], align 1
+; CGSCC-NEXT: store i1 true, ptr [[STACK1]], align 1
; CGSCC-NEXT: br label [[M:%.*]]
; CGSCC: f:
-; CGSCC-NEXT: store i1 false, ptr [[STACK]], align 1
+; CGSCC-NEXT: store i1 false, ptr [[STACK1]], align 1
; CGSCC-NEXT: br label [[M]]
; CGSCC: m:
-; CGSCC-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; CGSCC-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR8]]
; CGSCC-NEXT: ret i1 [[L]]
;
@@ -390,14 +390,14 @@ define void @assume_2b_nr(i1 %arg, i1 %cond) norecurse {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CHECK-LABEL: define {{[^@]+}}@assume_2b_nr
; CHECK-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; CHECK-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; CHECK-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; CHECK-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; CHECK: t:
; CHECK-NEXT: br label [[M:%.*]]
; CHECK: f:
; CHECK-NEXT: br label [[M]]
; CHECK: m:
-; CHECK-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; CHECK-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; CHECK-NEXT: ret void
;
%stack = alloca i1
@@ -419,16 +419,16 @@ define i1 @assume_3_nr(i1 %arg, i1 %cond) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_3_nr
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8:[0-9]+]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8:[0-9]+]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -469,18 +469,18 @@ define i1 @assume_4_nr(i1 %arg, i1 %cond) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_4_nr
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR7]]
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -521,22 +521,22 @@ define i1 @assume_5_nr(i1 %arg, i1 %cond) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_5_nr
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L2]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L3]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L4]]) #[[ATTR9:[0-9]+]]
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -589,23 +589,23 @@ define i1 @assume_5c_nr(i1 %cond) norecurse {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_5c_nr
; TUNIT-SAME: (i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR7]]
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L2]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L3]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L4]]) #[[ATTR9]]
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -741,19 +741,19 @@ define i1 @keep_assume_3c() {
define i1 @keep_assume_4c() {
;
; TUNIT-LABEL: define {{[^@]+}}@keep_assume_4c() {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L4]]) #[[ATTR7]]
-; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; TUNIT-NEXT: ret i1 [[L4]]
;
; CGSCC-LABEL: define {{[^@]+}}@keep_assume_4c() {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 true, ptr [[STACK]], align 1
-; CGSCC-NEXT: [[L4:%.*]] = load i1, ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; CGSCC-NEXT: store i1 true, ptr [[STACK1]], align 1
+; CGSCC-NEXT: [[L4:%.*]] = load i1, ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[L4]]) #[[ATTR8]]
-; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; CGSCC-NEXT: ret i1 [[L4]]
;
%stack = alloca i1
@@ -786,16 +786,16 @@ define i1 @drop_assume_1(i1 %arg) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@drop_assume_1
; TUNIT-SAME: (i1 returned [[ARG:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR7]]
; TUNIT-NEXT: ret i1 [[ARG]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CGSCC-LABEL: define {{[^@]+}}@drop_assume_1
; CGSCC-SAME: (i1 returned [[ARG:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR8]]
; CGSCC-NEXT: ret i1 [[ARG]]
;
@@ -860,20 +860,20 @@ define i1 @keep_assume_4(i1 %arg) {
;
; TUNIT-LABEL: define {{[^@]+}}@keep_assume_4
; TUNIT-SAME: (i1 [[ARG:%.*]]) {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR7]]
-; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; TUNIT-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; TUNIT-NEXT: ret i1 [[L]]
;
; CGSCC-LABEL: define {{[^@]+}}@keep_assume_4
; CGSCC-SAME: (i1 [[ARG:%.*]]) {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
-; CGSCC-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 -2147483648, align 1
+; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
+; CGSCC-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR8]]
-; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK]])
+; CGSCC-NEXT: call void @useI1p(ptr noalias nocapture noundef nonnull dereferenceable(1) [[STACK1]])
; CGSCC-NEXT: ret i1 [[L]]
;
%stack = alloca i1
@@ -888,8 +888,8 @@ define i1 @assume_1(i1 %arg, i1 %cond) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_1
; TUNIT-SAME: (i1 returned [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; TUNIT-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR7]]
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
@@ -902,8 +902,8 @@ define i1 @assume_1(i1 %arg, i1 %cond) {
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CGSCC-LABEL: define {{[^@]+}}@assume_1
; CGSCC-SAME: (i1 returned [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
-; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK]], align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, align 1
+; CGSCC-NEXT: store i1 [[ARG]], ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[ARG]]) #[[ATTR8]]
; CGSCC-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; CGSCC: t:
@@ -959,32 +959,32 @@ define i1 @assume_2(i1 %arg, i1 %cond) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_2
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR7]]
; TUNIT-NEXT: ret i1 [[L]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CGSCC-LABEL: define {{[^@]+}}@assume_2
; CGSCC-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; CGSCC-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; CGSCC: t:
-; CGSCC-NEXT: store i1 true, ptr [[STACK]], align 1
+; CGSCC-NEXT: store i1 true, ptr [[STACK1]], align 1
; CGSCC-NEXT: br label [[M:%.*]]
; CGSCC: f:
-; CGSCC-NEXT: store i1 false, ptr [[STACK]], align 1
+; CGSCC-NEXT: store i1 false, ptr [[STACK1]], align 1
; CGSCC-NEXT: br label [[M]]
; CGSCC: m:
-; CGSCC-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; CGSCC-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; CGSCC-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR8]]
; CGSCC-NEXT: ret i1 [[L]]
;
@@ -1007,14 +1007,14 @@ define void @assume_2b(i1 %arg, i1 %cond) {
; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; CHECK-LABEL: define {{[^@]+}}@assume_2b
; CHECK-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; CHECK-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; CHECK-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; CHECK-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; CHECK: t:
; CHECK-NEXT: br label [[M:%.*]]
; CHECK: f:
; CHECK-NEXT: br label [[M]]
; CHECK: m:
-; CHECK-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; CHECK-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; CHECK-NEXT: ret void
;
%stack = alloca i1
@@ -1036,16 +1036,16 @@ define i1 @assume_3(i1 %arg, i1 %cond) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_3
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -1086,18 +1086,18 @@ define i1 @assume_4(i1 %arg, i1 %cond) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_4
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L]]) #[[ATTR7]]
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -1138,22 +1138,22 @@ define i1 @assume_5(i1 %arg, i1 %cond) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_5
; TUNIT-SAME: (i1 [[ARG:%.*]], i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L2]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L3]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L4]]) #[[ATTR9]]
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
@@ -1206,23 +1206,23 @@ define i1 @assume_5c(i1 %cond) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(inaccessiblemem: readwrite)
; TUNIT-LABEL: define {{[^@]+}}@assume_5c
; TUNIT-SAME: (i1 noundef [[COND:%.*]]) #[[ATTR4]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i1, align 1
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef true) #[[ATTR7]]
; TUNIT-NEXT: br i1 [[COND]], label [[T:%.*]], label [[F:%.*]]
; TUNIT: t:
-; TUNIT-NEXT: store i1 true, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 true, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L2:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L2]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M:%.*]]
; TUNIT: f:
-; TUNIT-NEXT: store i1 false, ptr [[STACK]], align 1
-; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: store i1 false, ptr [[STACK1]], align 1
+; TUNIT-NEXT: [[L3:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L3]]) #[[ATTR7]]
; TUNIT-NEXT: br label [[M]]
; TUNIT: m:
-; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK]], align 1
+; TUNIT-NEXT: [[L4:%.*]] = load i1, ptr [[STACK1]], align 1
; TUNIT-NEXT: call void @llvm.assume(i1 noundef [[L4]]) #[[ATTR9]]
-; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK]]) #[[ATTR8]]
+; TUNIT-NEXT: [[R:%.*]] = call i1 @readI1p(ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[STACK1]]) #[[ATTR8]]
; TUNIT-NEXT: ret i1 [[R]]
;
; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(inaccessiblemem: readwrite)
diff --git a/llvm/test/Transforms/Attributor/value-simplify-dominance.ll b/llvm/test/Transforms/Attributor/value-simplify-dominance.ll
index 7c266ba70a1f98..a2d8bef8de9fb0 100644
--- a/llvm/test/Transforms/Attributor/value-simplify-dominance.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify-dominance.ll
@@ -8,7 +8,7 @@ define i32 @many_writes_nosycn(i1 %c0, i1 %c1, i1 %c2) nosync {
; CHECK: Function Attrs: norecurse nosync
; CHECK-LABEL: define {{[^@]+}}@many_writes_nosycn
; CHECK-SAME: (i1 [[C0:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: [[P:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[P1:%.*]] = alloca i8, i32 4, align 4
; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: br i1 [[C0]], label [[T0:%.*]], label [[F0:%.*]]
; CHECK: t0:
@@ -19,19 +19,19 @@ define i32 @many_writes_nosycn(i1 %c0, i1 %c1, i1 %c2) nosync {
; CHECK-NEXT: br i1 [[C2]], label [[F1:%.*]], label [[M1]]
; CHECK: t1:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: store i32 7, ptr [[P]], align 4
+; CHECK-NEXT: store i32 7, ptr [[P1]], align 4
; CHECK-NEXT: br label [[M2:%.*]]
; CHECK: f1:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: store i32 9, ptr [[P]], align 4
+; CHECK-NEXT: store i32 9, ptr [[P1]], align 4
; CHECK-NEXT: br label [[M2]]
; CHECK: m1:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: store i32 11, ptr [[P]], align 4
+; CHECK-NEXT: store i32 11, ptr [[P1]], align 4
; CHECK-NEXT: br label [[M2]]
; CHECK: m2:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
+; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P1]], align 4
; CHECK-NEXT: ret i32 [[L]]
;
%p = alloca i32
@@ -74,7 +74,7 @@ define i32 @many_writes(i1 %c0, i1 %c1, i1 %c2) {
; CHECK: Function Attrs: norecurse
; CHECK-LABEL: define {{[^@]+}}@many_writes
; CHECK-SAME: (i1 [[C0:%.*]], i1 [[C1:%.*]], i1 [[C2:%.*]]) #[[ATTR2:[0-9]+]] {
-; CHECK-NEXT: [[P:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[P1:%.*]] = alloca i8, i32 4, align 4
; CHECK-NEXT: call void @unknown()
; CHECK-NEXT: br i1 [[C0]], label [[T0:%.*]], label [[F0:%.*]]
; CHECK: t0:
@@ -85,19 +85,19 @@ define i32 @many_writes(i1 %c0, i1 %c1, i1 %c2) {
; CHECK-NEXT: br i1 [[C2]], label [[F1:%.*]], label [[M1]]
; CHECK: t1:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: store i32 7, ptr [[P]], align 4
+; CHECK-NEXT: store i32 7, ptr [[P1]], align 4
; CHECK-NEXT: br label [[M2:%.*]]
; CHECK: f1:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: store i32 9, ptr [[P]], align 4
+; CHECK-NEXT: store i32 9, ptr [[P1]], align 4
; CHECK-NEXT: br label [[M2]]
; CHECK: m1:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: store i32 11, ptr [[P]], align 4
+; CHECK-NEXT: store i32 11, ptr [[P1]], align 4
; CHECK-NEXT: br label [[M2]]
; CHECK: m2:
; CHECK-NEXT: call void @unknown()
-; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P]], align 4
+; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[P1]], align 4
; CHECK-NEXT: ret i32 [[L]]
;
%p = alloca i32
@@ -163,8 +163,8 @@ define i32 @local_stack_remote_write_and_read() norecurse {
; TUNIT: Function Attrs: norecurse
; TUNIT-LABEL: define {{[^@]+}}@local_stack_remote_write_and_read
; TUNIT-SAME: () #[[ATTR2]] {
-; TUNIT-NEXT: [[A:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: [[R:%.*]] = call i32 @remote_write_and_read(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[A]])
+; TUNIT-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: [[R:%.*]] = call i32 @remote_write_and_read(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[A1]])
; TUNIT-NEXT: ret i32 42
;
; CGSCC: Function Attrs: norecurse
diff --git a/llvm/test/Transforms/Attributor/value-simplify-gpu.ll b/llvm/test/Transforms/Attributor/value-simplify-gpu.ll
index a7e0a92912090e..86be385fa8081b 100644
--- a/llvm/test/Transforms/Attributor/value-simplify-gpu.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify-gpu.ll
@@ -205,8 +205,8 @@ define internal void @level1(i32 %C) {
; TUNIT-LABEL: define {{[^@]+}}@level1
; TUNIT-SAME: (i32 [[C:%.*]]) #[[ATTR1]] {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[LOCAL:%.*]] = alloca i32, align 4
-; TUNIT-NEXT: call void @level2all_early(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[LOCAL]]) #[[ATTR4]]
+; TUNIT-NEXT: [[LOCAL1:%.*]] = alloca i8, i32 4, align 4
+; TUNIT-NEXT: call void @level2all_early(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[LOCAL1]]) #[[ATTR4]]
; TUNIT-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[C]], 0
; TUNIT-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; TUNIT: if.then:
@@ -216,7 +216,7 @@ define internal void @level1(i32 %C) {
; TUNIT-NEXT: call void @level2b() #[[ATTR5]]
; TUNIT-NEXT: br label [[IF_END]]
; TUNIT: if.end:
-; TUNIT-NEXT: call void @level2all_late(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[LOCAL]]) #[[ATTR6]]
+; TUNIT-NEXT: call void @level2all_late(ptr noalias nocapture nofree noundef nonnull writeonly align 4 dereferenceable(4) [[LOCAL1]]) #[[ATTR6]]
; TUNIT-NEXT: ret void
;
; CGSCC: Function Attrs: norecurse nosync nounwind
diff --git a/llvm/test/Transforms/Attributor/value-simplify-local-remote.ll b/llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
index 20b52c3fcd85a7..ed56bfa4f575d1 100644
--- a/llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify-local-remote.ll
@@ -375,13 +375,13 @@ define dso_local void @spam() {
; TUNIT-LABEL: define {{[^@]+}}@spam
; TUNIT-SAME: () #[[ATTR2:[0-9]+]] {
; TUNIT-NEXT: bb:
-; TUNIT-NEXT: [[TMP:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[TMP1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: [[X:%.*]] = fptosi float undef to i32
-; TUNIT-NEXT: store i32 [[X]], ptr [[TMP]], align 4
+; TUNIT-NEXT: store i32 [[X]], ptr [[TMP1]], align 4
; TUNIT-NEXT: br label [[BB16:%.*]]
; TUNIT: bb16:
-; TUNIT-NEXT: [[TRUETMP18:%.*]] = icmp eq i32 [[X]], 0
-; TUNIT-NEXT: br i1 [[TRUETMP18]], label [[BB35:%.*]], label [[BB19:%.*]]
+; TUNIT-NEXT: [[TMP18:%.*]] = icmp eq i32 [[X]], 0
+; TUNIT-NEXT: br i1 [[TMP18]], label [[BB35:%.*]], label [[BB19:%.*]]
; TUNIT: bb19:
; TUNIT-NEXT: br label [[BB23:%.*]]
; TUNIT: bb23:
@@ -399,13 +399,13 @@ define dso_local void @spam() {
; CGSCC-LABEL: define {{[^@]+}}@spam
; CGSCC-SAME: () #[[ATTR5:[0-9]+]] {
; CGSCC-NEXT: bb:
-; CGSCC-NEXT: [[TMP:%.*]] = alloca i32, align 4
+; CGSCC-NEXT: [[TMP1:%.*]] = alloca i8, i32 4, align 4
; CGSCC-NEXT: [[X:%.*]] = fptosi float undef to i32
-; CGSCC-NEXT: store i32 [[X]], ptr [[TMP]], align 4
+; CGSCC-NEXT: store i32 [[X]], ptr [[TMP1]], align 4
; CGSCC-NEXT: br label [[BB16:%.*]]
; CGSCC: bb16:
-; CGSCC-NEXT: [[TRUETMP18:%.*]] = icmp eq i32 [[X]], 0
-; CGSCC-NEXT: br i1 [[TRUETMP18]], label [[BB35:%.*]], label [[BB19:%.*]]
+; CGSCC-NEXT: [[TMP18:%.*]] = icmp eq i32 [[X]], 0
+; CGSCC-NEXT: br i1 [[TMP18]], label [[BB35:%.*]], label [[BB19:%.*]]
; CGSCC: bb19:
; CGSCC-NEXT: br label [[BB23:%.*]]
; CGSCC: bb23:
diff --git a/llvm/test/Transforms/Attributor/value-simplify.ll b/llvm/test/Transforms/Attributor/value-simplify.ll
index 0ee06afe92f226..34a01825aeaa96 100644
--- a/llvm/test/Transforms/Attributor/value-simplify.ll
+++ b/llvm/test/Transforms/Attributor/value-simplify.ll
@@ -1267,21 +1267,21 @@ define internal i8 @memcpy_uses_store(i8 %arg) {
; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@memcpy_uses_store
; TUNIT-SAME: (i8 [[ARG:%.*]]) #[[ATTR2]] {
-; TUNIT-NEXT: [[SRC:%.*]] = alloca i8, align 1
-; TUNIT-NEXT: [[DST:%.*]] = alloca i8, align 1
-; TUNIT-NEXT: store i8 [[ARG]], ptr [[SRC]], align 1
-; TUNIT-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[DST]], ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[SRC]], i32 noundef 1, i1 noundef false) #[[ATTR12:[0-9]+]]
-; TUNIT-NEXT: [[L:%.*]] = load i8, ptr [[DST]], align 1
+; TUNIT-NEXT: [[SRC1:%.*]] = alloca i8, align 1
+; TUNIT-NEXT: [[DST2:%.*]] = alloca i8, align 1
+; TUNIT-NEXT: store i8 [[ARG]], ptr [[SRC1]], align 1
+; TUNIT-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[DST2]], ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[SRC1]], i32 noundef 1, i1 noundef false) #[[ATTR12:[0-9]+]]
+; TUNIT-NEXT: [[L:%.*]] = load i8, ptr [[DST2]], align 1
; TUNIT-NEXT: ret i8 [[L]]
;
; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@memcpy_uses_store
; CGSCC-SAME: (i8 [[ARG:%.*]]) #[[ATTR1]] {
-; CGSCC-NEXT: [[SRC:%.*]] = alloca i8, align 1
-; CGSCC-NEXT: [[DST:%.*]] = alloca i8, align 1
-; CGSCC-NEXT: store i8 [[ARG]], ptr [[SRC]], align 1
-; CGSCC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[DST]], ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[SRC]], i32 noundef 1, i1 noundef false) #[[ATTR16:[0-9]+]]
-; CGSCC-NEXT: [[L:%.*]] = load i8, ptr [[DST]], align 1
+; CGSCC-NEXT: [[SRC1:%.*]] = alloca i8, align 1
+; CGSCC-NEXT: [[DST2:%.*]] = alloca i8, align 1
+; CGSCC-NEXT: store i8 [[ARG]], ptr [[SRC1]], align 1
+; CGSCC-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr noalias nocapture nofree noundef nonnull writeonly dereferenceable(1) [[DST2]], ptr noalias nocapture nofree noundef nonnull readonly dereferenceable(1) [[SRC1]], i32 noundef 1, i1 noundef false) #[[ATTR16:[0-9]+]]
+; CGSCC-NEXT: [[L:%.*]] = load i8, ptr [[DST2]], align 1
; CGSCC-NEXT: ret i8 [[L]]
;
%src = alloca i8
@@ -1316,21 +1316,21 @@ define i32 @test_speculatable_expr() norecurse {
; TUNIT: Function Attrs: norecurse nosync memory(none)
; TUNIT-LABEL: define {{[^@]+}}@test_speculatable_expr
; TUNIT-SAME: () #[[ATTR7:[0-9]+]] {
-; TUNIT-NEXT: [[STACK:%.*]] = alloca i32, align 4
+; TUNIT-NEXT: [[STACK1:%.*]] = alloca i8, i32 4, align 4
; TUNIT-NEXT: [[SPEC_RESULT:%.*]] = call i32 @speculatable() #[[ATTR14:[0-9]+]]
; TUNIT-NEXT: [[PLUS1:%.*]] = add i32 [[SPEC_RESULT]], 1
-; TUNIT-NEXT: store i32 [[PLUS1]], ptr [[STACK]], align 4
-; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[STACK]], align 4
+; TUNIT-NEXT: store i32 [[PLUS1]], ptr [[STACK1]], align 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[STACK1]], align 4
; TUNIT-NEXT: [[RSPEC:%.*]] = call i32 @ret_speculatable_expr(i32 [[TMP1]]) #[[ATTR15:[0-9]+]]
; TUNIT-NEXT: ret i32 [[RSPEC]]
;
; CGSCC: Function Attrs: norecurse nosync memory(none)
; CGSCC-LABEL: define {{[^@]+}}@test_speculatable_expr
; CGSCC-SAME: () #[[ATTR9:[0-9]+]] {
-; CGSCC-NEXT: [[STACK:%.*]] = alloca i32, align 4
+; CGSCC-NEXT: [[STACK1:%.*]] = alloca i8, i32 4, align 4
; CGSCC-NEXT: [[SPEC_RESULT:%.*]] = call i32 @speculatable() #[[ATTR17:[0-9]+]]
; CGSCC-NEXT: [[PLUS1:%.*]] = add i32 [[SPEC_RESULT]], 1
-; CGSCC-NEXT: store i32 [[PLUS1]], ptr [[STACK]], align 4
+; CGSCC-NEXT: store i32 [[PLUS1]], ptr [[STACK1]], align 4
; CGSCC-NEXT: [[RSPEC:%.*]] = call i32 @ret_speculatable_expr(i32 [[PLUS1]]) #[[ATTR17]]
; CGSCC-NEXT: ret i32 [[RSPEC]]
;
diff --git a/llvm/test/Transforms/OpenMP/parallel_deletion.ll b/llvm/test/Transforms/OpenMP/parallel_deletion.ll
index 6319875fd90568..0bab55846a71d1 100644
--- a/llvm/test/Transforms/OpenMP/parallel_deletion.ll
+++ b/llvm/test/Transforms/OpenMP/parallel_deletion.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals
; RUN: opt -S -passes='attributor,cgscc(openmp-opt-cgscc)' < %s | FileCheck %s
;
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
@@ -23,10 +23,17 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16
; }
;
; We delete all but the first of the parallel regions in this test.
+;.
+; CHECK: @[[_STR:[a-zA-Z0-9_$"\\.-]+]] = private unnamed_addr constant [23 x i8] c"
+; CHECK: @[[GLOB0:[0-9]+]] = private unnamed_addr global [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @.str }, align 8
+; CHECK: @[[GLOB1:[0-9]+]] = private unnamed_addr global [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 0, i32 0, ptr @.str }, align 8
+; CHECK: @[[_GOMP_CRITICAL_USER__REDUCTION_VAR:[a-zA-Z0-9_$"\\.-]+]] = common global [8 x i32] zeroinitializer
+; CHECK: @[[GLOB2:[0-9]+]] = private unnamed_addr global [[STRUCT_IDENT_T:%.*]] { i32 0, i32 18, i32 0, i32 0, ptr @.str }, align 8
+;.
define void @delete_parallel_0() {
; CHECK-LABEL: define {{[^@]+}}@delete_parallel_0() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0:[0-9]+]], i32 noundef 0, ptr noundef nonnull @.omp_outlined.willreturn)
+; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 0, ptr noundef nonnull @.omp_outlined.willreturn)
; CHECK-NEXT: ret void
;
; CHECK1-LABEL: define {{[^@]+}}@delete_parallel_0() {
@@ -46,6 +53,7 @@ entry:
}
define internal void @.omp_outlined.willreturn(ptr noalias %.global_tid., ptr noalias %.bound_tid.) {
+; CHECK: Function Attrs: mustprogress willreturn
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined.willreturn
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -68,6 +76,7 @@ entry:
}
define internal void @.omp_outlined.willreturn.0(ptr noalias %.global_tid., ptr noalias %.bound_tid.) willreturn {
+; CHECK: Function Attrs: mustprogress nosync willreturn memory(read)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined.willreturn.0
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -90,6 +99,7 @@ entry:
}
define internal void @.omp_outlined.willreturn.1(ptr noalias %.global_tid., ptr noalias %.bound_tid.) {
+; CHECK: Function Attrs: mustprogress nosync willreturn memory(none)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined.willreturn.1
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -112,6 +122,7 @@ entry:
}
define internal void @.omp_outlined.willreturn.2(ptr noalias %.global_tid., ptr noalias %.bound_tid.) {
+; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined.willreturn.2
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -192,6 +203,7 @@ entry:
}
define internal void @.omp_outlined..0(ptr noalias %.global_tid., ptr noalias %.bound_tid.) {
+; CHECK: Function Attrs: nosync memory(read)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined..0
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
; CHECK-NEXT: entry:
@@ -214,6 +226,7 @@ entry:
}
define internal void @.omp_outlined..1(ptr noalias %.global_tid., ptr noalias %.bound_tid.) {
+; CHECK: Function Attrs: nosync memory(none)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined..1
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -236,6 +249,7 @@ entry:
}
define internal void @.omp_outlined..2(ptr noalias %.global_tid., ptr noalias %.bound_tid.) {
+; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined..2
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
; CHECK-NEXT: entry:
@@ -281,14 +295,14 @@ entry:
define void @delete_parallel_2() {
; CHECK-LABEL: define {{[^@]+}}@delete_parallel_2() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
-; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 noundef 4, ptr noundef nonnull align 4 dereferenceable(4) [[A]]) #[[ATTR18:[0-9]+]]
-; CHECK-NEXT: store i32 0, ptr [[A]], align 4
-; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..3, ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A]])
-; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..4, ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A]])
-; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..5, ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A]])
-; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..6, ptr nocapture noundef nonnull align 4 dereferenceable(4) [[A]])
-; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 noundef 4, ptr noundef nonnull [[A]])
+; CHECK-NEXT: [[A1:%.*]] = alloca i8, i32 4, align 4
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 noundef 4, ptr noundef nonnull align 4 dereferenceable(4) [[A1]]) #[[ATTR18:[0-9]+]]
+; CHECK-NEXT: store i32 0, ptr [[A1]], align 4
+; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..3, ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A1]])
+; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..4, ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A1]])
+; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..5, ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A1]])
+; CHECK-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB0]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..6, ptr nocapture noundef nonnull align 4 dereferenceable(4) [[A1]])
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 noundef 4, ptr noundef nonnull [[A1]])
; CHECK-NEXT: ret void
;
; CHECK1-LABEL: define {{[^@]+}}@delete_parallel_2() {
@@ -326,6 +340,7 @@ entry:
}
define internal void @.omp_outlined..3(ptr noalias %.global_tid., ptr noalias %.bound_tid., ptr dereferenceable(4) %a) {
+; CHECK: Function Attrs: nofree nosync nounwind memory(argmem: readwrite, inaccessiblemem: readwrite)
; CHECK-LABEL: define {{[^@]+}}@.omp_outlined..3
; CHECK-SAME: (ptr noalias nocapture nofree readnone [[DOTGLOBAL_TID_:%.*]], ptr noalias nocapture nofree readnone [[DOTBOUND_TID_:%.*]], ptr nocapture nofree noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR6:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -469,7 +484,7 @@ define internal void @.omp_outlined..5(ptr noalias %.global_tid., ptr noalias %.
; CHECK-NEXT: call void @__kmpc_end_single(ptr noundef nonnull @[[GLOB0]], i32 [[TMP]])
; CHECK-NEXT: br label [[OMP_IF_END]]
; CHECK: omp_if.end:
-; CHECK-NEXT: call void @__kmpc_barrier(ptr noundef nonnull @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+; CHECK-NEXT: call void @__kmpc_barrier(ptr noundef nonnull @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK-NEXT: ret void
;
; CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
@@ -535,7 +550,7 @@ define internal void @.omp_outlined..6(ptr noalias %.global_tid., ptr noalias %.
; CHECK-NEXT: store i32 1, ptr [[A1]], align 4
; CHECK-NEXT: store ptr [[A1]], ptr [[DOTOMP_REDUCTION_RED_LIST]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTGLOBAL_TID_]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_reduce_nowait(ptr noundef nonnull @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 noundef 1, i64 noundef 8, ptr noundef nonnull align 8 [[DOTOMP_REDUCTION_RED_LIST]], ptr noundef nonnull @.omp.reduction.reduction_func, ptr noundef nonnull @.gomp_critical_user_.reduction.var)
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_reduce_nowait(ptr noundef nonnull @[[GLOB2]], i32 [[TMP2]], i32 noundef 1, i64 noundef 8, ptr noundef nonnull align 8 [[DOTOMP_REDUCTION_RED_LIST]], ptr noundef nonnull @.omp.reduction.reduction_func, ptr noundef nonnull @.gomp_critical_user_.reduction.var)
; CHECK-NEXT: switch i32 [[TMP4]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [
; CHECK-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]]
; CHECK-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]]
@@ -643,6 +658,7 @@ entry:
}
define internal void @.omp.reduction.reduction_func(ptr %arg, ptr %arg1) {
+; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
; CHECK-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func
; CHECK-SAME: (ptr nocapture nofree noundef nonnull readonly align 8 dereferenceable(8) [[ARG:%.*]], ptr nocapture nofree noundef nonnull readonly align 8 dereferenceable(8) [[ARG1:%.*]]) #[[ATTR10:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -717,3 +733,30 @@ declare void @readnone() readnone
!6 = !{!"omnipotent char", !7, i64 0}
!7 = !{!"Simple C/C++ TBAA"}
!8 = !{i32 7, !"openmp", i32 50}
+;.
+; CHECK: attributes #[[ATTR0]] = { mustprogress willreturn }
+; CHECK: attributes #[[ATTR1]] = { mustprogress nosync willreturn memory(read) }
+; CHECK: attributes #[[ATTR2]] = { mustprogress nosync willreturn memory(none) }
+; CHECK: attributes #[[ATTR3]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }
+; CHECK: attributes #[[ATTR4]] = { nosync memory(read) }
+; CHECK: attributes #[[ATTR5]] = { nosync memory(none) }
+; CHECK: attributes #[[ATTR6]] = { nofree nosync nounwind memory(argmem: readwrite, inaccessiblemem: readwrite) }
+; CHECK: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
+; CHECK: attributes #[[ATTR8:[0-9]+]] = { nofree nosync nounwind memory(inaccessiblemem: read) }
+; CHECK: attributes #[[ATTR9:[0-9]+]] = { nounwind }
+; CHECK: attributes #[[ATTR10]] = { mustprogress nofree norecurse nosync nounwind willreturn }
+; CHECK: attributes #[[ATTR11:[0-9]+]] = { convergent nounwind }
+; CHECK: attributes #[[ATTR12:[0-9]+]] = { nofree nosync nounwind memory(read) }
+; CHECK: attributes #[[ATTR13:[0-9]+]] = { memory(read) }
+; CHECK: attributes #[[ATTR14:[0-9]+]] = { memory(none) }
+; CHECK: attributes #[[ATTR15]] = { willreturn }
+; CHECK: attributes #[[ATTR16]] = { nosync willreturn }
+; CHECK: attributes #[[ATTR17]] = { nosync }
+; CHECK: attributes #[[ATTR18]] = { nofree willreturn }
+; CHECK: attributes #[[ATTR19]] = { nofree nounwind memory(read) }
+; CHECK: attributes #[[ATTR20]] = { nofree willreturn memory(readwrite) }
+;.
+; CHECK: [[META0:![0-9]+]] = !{i32 7, !"openmp", i32 50}
+; CHECK: [[META1:![0-9]+]] = !{!2}
+; CHECK: [[META2:![0-9]+]] = !{i64 2, i64 -1, i64 -1, i1 true}
+;.
diff --git a/llvm/test/Transforms/OpenMP/parallel_region_merging.ll b/llvm/test/Transforms/OpenMP/parallel_region_merging.ll
index f169fea09d0ea3..d31f28382e7ee7 100644
--- a/llvm/test/Transforms/OpenMP/parallel_region_merging.ll
+++ b/llvm/test/Transforms/OpenMP/parallel_region_merging.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs
; RUN: opt -S -aa-pipeline= -passes='attributor,cgscc(openmp-opt-cgscc)' -openmp-opt-enable-merging < %s | FileCheck %s --check-prefix=CHECK2
; #include <omp.h>
; void foo();
@@ -4670,17 +4670,23 @@ entry:
; CHECK-NEXT: call void @use(i32 [[TMP0]])
; CHECK-NEXT: ret void
+;.
+; CHECK2: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
+; CHECK2: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
+; CHECK2: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 22, ptr @[[GLOB0]] }, align 8
+; CHECK2: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 66, i32 0, i32 22, ptr @[[GLOB0]] }, align 8
+;.
; CHECK2-LABEL: define {{[^@]+}}@merge
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -4691,11 +4697,12 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK2-NEXT: omp.par.entry:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -4704,10 +4711,10 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined.(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined.(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..1(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..1(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -4738,12 +4745,12 @@ entry:
; CHECK2-LABEL: define {{[^@]+}}@unmergable_proc_bind
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1:[0-9]+]])
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]])
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
; CHECK2-NEXT: call void @__kmpc_push_proc_bind(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 [[TMP0]], i32 noundef 3)
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..2, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..3, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..2, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..3, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
@@ -4766,12 +4773,12 @@ entry:
; CHECK2-LABEL: define {{[^@]+}}@unmergable_num_threads
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]])
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
; CHECK2-NEXT: call void @__kmpc_push_num_threads(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 [[TMP0]], i32 [[A]])
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..4, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..5, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..4, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..5, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
@@ -4794,11 +4801,11 @@ entry:
; CHECK2-LABEL: define {{[^@]+}}@unmergable_seq_call
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..6, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..6, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: call void (...) @foo()
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..7, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..7, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
@@ -4822,13 +4829,13 @@ entry:
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_seq..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -4836,16 +4843,17 @@ entry:
; CHECK2: omp.par.exit.split:
; CHECK2-NEXT: br label [[ENTRY_SPLIT_SPLIT:%.*]]
; CHECK2: entry.split.split:
-; CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+; CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR1]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_seq..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -4854,19 +4862,19 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..8(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..8(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
; CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..9(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..9(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -4877,9 +4885,9 @@ entry:
; CHECK2: omp_region.body:
; CHECK2-NEXT: br label [[SEQ_PAR_MERGED:%.*]]
; CHECK2: seq.par.merged:
-; CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_A_ADDR]], align 4
+; CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_A_ADDR1]], align 4
; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
-; CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_A_ADDR]], align 4
+; CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_A_ADDR1]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
@@ -4911,16 +4919,16 @@ entry:
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
; CHECK2-NEXT: [[F_RELOADED:%.*]] = alloca float, align 4
-; CHECK2-NEXT: [[F_ADDR:%.*]] = alloca float, align 4
-; CHECK2-NEXT: store float [[F]], ptr [[F_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[F_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store float [[F]], ptr [[F_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: store float [[F]], ptr [[F_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
; CHECK2-NEXT: [[GEP_F_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
; CHECK2-NEXT: store ptr [[F_RELOADED]], ptr [[GEP_F_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_F_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
-; CHECK2-NEXT: store ptr [[F_ADDR]], ptr [[GEP_F_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_F_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+; CHECK2-NEXT: store ptr [[F_ADDR1]], ptr [[GEP_F_ADDR1]], align 8
; CHECK2-NEXT: [[GEP_P:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
; CHECK2-NEXT: store ptr [[P]], ptr [[GEP_P]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_seq_float..omp_par, ptr [[STRUCTARG]])
@@ -4933,13 +4941,14 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_seq_float..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[GEP_F_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
; CHECK2-NEXT: [[LOADGEP_F_RELOADED:%.*]] = load ptr, ptr [[GEP_F_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_F_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
-; CHECK2-NEXT: [[LOADGEP_F_ADDR:%.*]] = load ptr, ptr [[GEP_F_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_F_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
+; CHECK2-NEXT: [[LOADGEP_F_ADDR1:%.*]] = load ptr, ptr [[GEP_F_ADDR1]], align 8
; CHECK2-NEXT: [[GEP_P:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 2
; CHECK2-NEXT: [[LOADGEP_P:%.*]] = load ptr, ptr [[GEP_P]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
@@ -4951,19 +4960,19 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..10(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_F_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..10(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_F_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK2-NEXT: br i1 [[TMP4]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..11(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_F_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..11(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_F_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5009,13 +5018,13 @@ entry:
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
; CHECK2-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]] = alloca i64, align 8
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[GEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
; CHECK2-NEXT: store ptr [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], ptr [[GEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_seq_firstprivate..omp_par, ptr [[STRUCTARG]])
@@ -5025,16 +5034,17 @@ entry:
; CHECK2: omp.par.exit.split:
; CHECK2-NEXT: br label [[ENTRY_SPLIT_SPLIT:%.*]]
; CHECK2: entry.split.split:
-; CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
+; CHECK2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR1]], align 4
; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_seq_firstprivate..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[GEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
; CHECK2-NEXT: [[LOADGEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC:%.*]] = load ptr, ptr [[GEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
@@ -5045,16 +5055,16 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..12(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..12(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
; CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
; CHECK2-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_LOAD:%.*]] = load i64, ptr [[LOADGEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8
@@ -5069,9 +5079,9 @@ entry:
; CHECK2: omp_region.body:
; CHECK2-NEXT: br label [[SEQ_PAR_MERGED:%.*]]
; CHECK2: seq.par.merged:
-; CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_A_ADDR]], align 4
+; CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_A_ADDR1]], align 4
; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
-; CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_A_ADDR]], align 4
+; CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_A_ADDR1]], align 4
; CHECK2-NEXT: [[A_CASTED_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[ADD]] to i64
; CHECK2-NEXT: store i64 [[A_CASTED_SROA_0_0_INSERT_EXT]], ptr [[LOADGEP_A_CASTED_SROA_0_0_INSERT_EXT_SEQ_OUTPUT_ALLOC]], align 8
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
@@ -5104,13 +5114,13 @@ entry:
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_seq_sink_lt..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -5121,12 +5131,13 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_seq_sink_lt..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -5135,19 +5146,19 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..14(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..14(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], 0
; CHECK2-NEXT: br i1 [[TMP3]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..15(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..15(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5194,20 +5205,20 @@ entry:
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
; CHECK2-NEXT: [[A_RELOADED:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: [[B2:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: store i32 [[A]], ptr [[A_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
; CHECK2-NEXT: [[GEP_A_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
; CHECK2-NEXT: store ptr [[A_RELOADED]], ptr [[GEP_A_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
-; CHECK2-NEXT: [[GEP_B:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
-; CHECK2-NEXT: store ptr [[B]], ptr [[GEP_B]], align 8
-; CHECK2-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[B]])
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
+; CHECK2-NEXT: [[GEP_B2:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+; CHECK2-NEXT: store ptr [[B2]], ptr [[GEP_B2]], align 8
+; CHECK2-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[B2]])
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_seq_par_use..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -5215,19 +5226,20 @@ entry:
; CHECK2: omp.par.exit.split:
; CHECK2-NEXT: br label [[ENTRY_SPLIT_SPLIT:%.*]]
; CHECK2: entry.split.split:
-; CHECK2-NEXT: call void @llvm.lifetime.end.p0(i64 noundef 4, ptr noundef nonnull [[B]])
+; CHECK2-NEXT: call void @llvm.lifetime.end.p0(i64 noundef 4, ptr noundef nonnull [[B2]])
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_seq_par_use..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[GEP_A_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
; CHECK2-NEXT: [[LOADGEP_A_RELOADED:%.*]] = load ptr, ptr [[GEP_A_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
-; CHECK2-NEXT: [[GEP_B:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 2
-; CHECK2-NEXT: [[LOADGEP_B:%.*]] = load ptr, ptr [[GEP_B]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
+; CHECK2-NEXT: [[GEP_B2:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 2
+; CHECK2-NEXT: [[LOADGEP_B2:%.*]] = load ptr, ptr [[GEP_B2]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -5237,19 +5249,19 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..16(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..16(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK2-NEXT: br i1 [[TMP4]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..17(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_B]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..17(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_B2]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5261,7 +5273,7 @@ entry:
; CHECK2-NEXT: br label [[SEQ_PAR_MERGED:%.*]]
; CHECK2: seq.par.merged:
; CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
-; CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_B]], align 4
+; CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_B2]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
@@ -5294,17 +5306,17 @@ entry:
; CHECK2-SAME: (i32 [[CANCEL1:%.*]], i32 [[CANCEL2:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
-; CHECK2-NEXT: [[CANCEL1_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[CANCEL2_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[CANCEL1]], ptr [[CANCEL1_ADDR]], align 4
-; CHECK2-NEXT: store i32 [[CANCEL2]], ptr [[CANCEL2_ADDR]], align 4
+; CHECK2-NEXT: [[CANCEL1_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: [[CANCEL2_ADDR2:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[CANCEL1]], ptr [[CANCEL1_ADDR1]], align 4
+; CHECK2-NEXT: store i32 [[CANCEL2]], ptr [[CANCEL2_ADDR2]], align 4
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_CANCEL1_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[CANCEL1_ADDR]], ptr [[GEP_CANCEL1_ADDR]], align 8
-; CHECK2-NEXT: [[GEP_CANCEL2_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
-; CHECK2-NEXT: store ptr [[CANCEL2_ADDR]], ptr [[GEP_CANCEL2_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL1_ADDR1:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[CANCEL1_ADDR1]], ptr [[GEP_CANCEL1_ADDR1]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL2_ADDR2:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+; CHECK2-NEXT: store ptr [[CANCEL2_ADDR2]], ptr [[GEP_CANCEL2_ADDR2]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_cancellable_regions..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -5315,13 +5327,14 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_cancellable_regions..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
-; CHECK2-NEXT: [[GEP_CANCEL1_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_CANCEL1_ADDR:%.*]] = load ptr, ptr [[GEP_CANCEL1_ADDR]], align 8
-; CHECK2-NEXT: [[GEP_CANCEL2_ADDR:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
-; CHECK2-NEXT: [[LOADGEP_CANCEL2_ADDR:%.*]] = load ptr, ptr [[GEP_CANCEL2_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL1_ADDR1:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_CANCEL1_ADDR1:%.*]] = load ptr, ptr [[GEP_CANCEL1_ADDR1]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL2_ADDR2:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
+; CHECK2-NEXT: [[LOADGEP_CANCEL2_ADDR2:%.*]] = load ptr, ptr [[GEP_CANCEL2_ADDR2]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -5330,10 +5343,10 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..18(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL1_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..18(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL1_ADDR1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..19(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL2_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..19(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL2_ADDR2]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5378,20 +5391,20 @@ entry:
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
; CHECK2-NEXT: [[CANCEL1_RELOADED:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[CANCEL1_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[CANCEL2_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[CANCEL1]], ptr [[CANCEL1_ADDR]], align 4
-; CHECK2-NEXT: store i32 [[CANCEL2]], ptr [[CANCEL2_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[CANCEL1_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: [[CANCEL2_ADDR2:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[CANCEL1]], ptr [[CANCEL1_ADDR1]], align 4
+; CHECK2-NEXT: store i32 [[CANCEL2]], ptr [[CANCEL2_ADDR2]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: store i32 [[CANCEL1]], ptr [[CANCEL1_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
; CHECK2-NEXT: [[GEP_CANCEL1_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
; CHECK2-NEXT: store ptr [[CANCEL1_RELOADED]], ptr [[GEP_CANCEL1_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_CANCEL1_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
-; CHECK2-NEXT: store ptr [[CANCEL1_ADDR]], ptr [[GEP_CANCEL1_ADDR]], align 8
-; CHECK2-NEXT: [[GEP_CANCEL2_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
-; CHECK2-NEXT: store ptr [[CANCEL2_ADDR]], ptr [[GEP_CANCEL2_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL1_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+; CHECK2-NEXT: store ptr [[CANCEL1_ADDR1]], ptr [[GEP_CANCEL1_ADDR1]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL2_ADDR2:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+; CHECK2-NEXT: store ptr [[CANCEL2_ADDR2]], ptr [[GEP_CANCEL2_ADDR2]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_cancellable_regions_seq..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -5402,15 +5415,16 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_cancellable_regions_seq..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[GEP_CANCEL1_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
; CHECK2-NEXT: [[LOADGEP_CANCEL1_RELOADED:%.*]] = load ptr, ptr [[GEP_CANCEL1_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_CANCEL1_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
-; CHECK2-NEXT: [[LOADGEP_CANCEL1_ADDR:%.*]] = load ptr, ptr [[GEP_CANCEL1_ADDR]], align 8
-; CHECK2-NEXT: [[GEP_CANCEL2_ADDR:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 2
-; CHECK2-NEXT: [[LOADGEP_CANCEL2_ADDR:%.*]] = load ptr, ptr [[GEP_CANCEL2_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL1_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
+; CHECK2-NEXT: [[LOADGEP_CANCEL1_ADDR1:%.*]] = load ptr, ptr [[GEP_CANCEL1_ADDR1]], align 8
+; CHECK2-NEXT: [[GEP_CANCEL2_ADDR2:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 2
+; CHECK2-NEXT: [[LOADGEP_CANCEL2_ADDR2:%.*]] = load ptr, ptr [[GEP_CANCEL2_ADDR2]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -5420,19 +5434,19 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..20(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL1_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..20(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL1_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK2-NEXT: br i1 [[TMP4]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..21(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL2_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..21(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_CANCEL2_ADDR2]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5445,7 +5459,7 @@ entry:
; CHECK2: seq.par.merged:
; CHECK2-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP2]], 0
; CHECK2-NEXT: [[LNOT_EXT:%.*]] = zext i1 [[TOBOOL_NOT]] to i32
-; CHECK2-NEXT: store i32 [[LNOT_EXT]], ptr [[LOADGEP_CANCEL2_ADDR]], align 4
+; CHECK2-NEXT: store i32 [[LNOT_EXT]], ptr [[LOADGEP_CANCEL2_ADDR2]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT:%.*]]
; CHECK2: omp.par.merged.split:
; CHECK2-NEXT: br label [[OMP_REGION_BODY_SPLIT:%.*]]
@@ -5488,13 +5502,13 @@ entry:
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_3..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -5505,11 +5519,12 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_3..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -5518,13 +5533,13 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..22(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..22(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..23(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..23(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..24(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..24(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5567,16 +5582,16 @@ entry:
; CHECK2-NEXT: [[A_RELOADED:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[ADD1_SEQ_OUTPUT_ALLOC:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[ADD_SEQ_OUTPUT_ALLOC:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: store i32 [[A]], ptr [[A_RELOADED]], align 4
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
; CHECK2-NEXT: [[GEP_A_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
; CHECK2-NEXT: store ptr [[A_RELOADED]], ptr [[GEP_A_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[GEP_ADD_SEQ_OUTPUT_ALLOC:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
; CHECK2-NEXT: store ptr [[ADD_SEQ_OUTPUT_ALLOC]], ptr [[GEP_ADD_SEQ_OUTPUT_ALLOC]], align 8
; CHECK2-NEXT: [[GEP_ADD1_SEQ_OUTPUT_ALLOC:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
@@ -5593,13 +5608,14 @@ entry:
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_3_seq..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
; CHECK2-NEXT: [[GEP_A_RELOADED:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 0
; CHECK2-NEXT: [[LOADGEP_A_RELOADED:%.*]] = load ptr, ptr [[GEP_A_RELOADED]], align 8
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 1
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[GEP_ADD_SEQ_OUTPUT_ALLOC:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 2
; CHECK2-NEXT: [[LOADGEP_ADD_SEQ_OUTPUT_ALLOC:%.*]] = load ptr, ptr [[GEP_ADD_SEQ_OUTPUT_ALLOC]], align 8
; CHECK2-NEXT: [[GEP_ADD1_SEQ_OUTPUT_ALLOC:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP0]], i32 0, i32 3
@@ -5613,31 +5629,31 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..25(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..25(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM]])
; CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK2-NEXT: br i1 [[TMP4]], label [[OMP_REGION_BODY:%.*]], label [[OMP_REGION_END:%.*]]
; CHECK2: omp_region.end:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM1]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..26(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM4]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..26(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM4]])
; CHECK2-NEXT: [[TMP6:%.*]] = icmp ne i32 [[TMP5]], 0
-; CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_REGION_BODY5:%.*]], label [[OMP_REGION_END4:%.*]]
-; CHECK2: omp_region.end4:
-; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
-; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM6]])
+; CHECK2-NEXT: br i1 [[TMP6]], label [[OMP_REGION_BODY6:%.*]], label [[OMP_REGION_END5:%.*]]
+; CHECK2: omp_region.end5:
+; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM7:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
+; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM7]])
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split.split.split:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..27(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..27(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5645,18 +5661,18 @@ entry:
; CHECK2-NEXT: br label [[OMP_PAR_PRE_FINALIZE:%.*]]
; CHECK2: omp.par.pre_finalize:
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT_EXITSTUB:%.*]]
-; CHECK2: omp_region.body5:
-; CHECK2-NEXT: br label [[SEQ_PAR_MERGED2:%.*]]
-; CHECK2: seq.par.merged2:
+; CHECK2: omp_region.body6:
+; CHECK2-NEXT: br label [[SEQ_PAR_MERGED3:%.*]]
+; CHECK2: seq.par.merged3:
; CHECK2-NEXT: [[ADD_SEQ_OUTPUT_LOAD:%.*]] = load i32, ptr [[LOADGEP_ADD_SEQ_OUTPUT_ALLOC]], align 4
; CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[ADD_SEQ_OUTPUT_LOAD]], [[TMP2]]
; CHECK2-NEXT: store i32 [[ADD1]], ptr [[LOADGEP_ADD1_SEQ_OUTPUT_ALLOC]], align 4
; CHECK2-NEXT: br label [[OMP_PAR_MERGED_SPLIT_SPLIT_SPLIT:%.*]]
; CHECK2: omp.par.merged.split.split.split:
-; CHECK2-NEXT: br label [[OMP_REGION_BODY5_SPLIT:%.*]]
-; CHECK2: omp_region.body5.split:
-; CHECK2-NEXT: call void @__kmpc_end_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
-; CHECK2-NEXT: br label [[OMP_REGION_END4]]
+; CHECK2-NEXT: br label [[OMP_REGION_BODY6_SPLIT:%.*]]
+; CHECK2: omp_region.body6.split:
+; CHECK2-NEXT: call void @__kmpc_end_master(ptr @[[GLOB2]], i32 [[OMP_GLOBAL_THREAD_NUM4]])
+; CHECK2-NEXT: br label [[OMP_REGION_END5]]
; CHECK2: omp_region.body:
; CHECK2-NEXT: br label [[SEQ_PAR_MERGED:%.*]]
; CHECK2: seq.par.merged:
@@ -5699,13 +5715,13 @@ entry:
; CHECK2-LABEL: define {{[^@]+}}@unmergable_3_seq_call
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..28, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..28, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: call void (...) @foo()
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..29, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..29, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: call void (...) @foo()
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..30, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..30, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
@@ -5736,13 +5752,13 @@ entry:
; CHECK2-LABEL: define {{[^@]+}}@unmergable_3_proc_bind
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]])
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..31, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..31, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: call void @__kmpc_push_proc_bind(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 [[TMP0]], i32 noundef 3)
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..32, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..33, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..32, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..33, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
@@ -5773,13 +5789,13 @@ entry:
; CHECK2-LABEL: define {{[^@]+}}@unmergable_3_num_threads
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
; CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]])
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..34, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..34, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: call void @__kmpc_push_num_threads(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 [[TMP0]], i32 [[A]])
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..35, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..36, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..35, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..36, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
@@ -5811,13 +5827,13 @@ entry:
; CHECK2-SAME: (i32 [[A:%.*]]) local_unnamed_addr {
; CHECK2-NEXT: entry:
; CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr }, align 8
-; CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
-; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
+; CHECK2-NEXT: [[A_ADDR1:%.*]] = alloca i8, i32 4, align 4
+; CHECK2-NEXT: store i32 [[A]], ptr [[A_ADDR1]], align 4
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: br label [[OMP_PARALLEL:%.*]]
; CHECK2: omp_parallel:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
-; CHECK2-NEXT: store ptr [[A_ADDR]], ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+; CHECK2-NEXT: store ptr [[A_ADDR1]], ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @merge_2_unmergable_1..omp_par, ptr [[STRUCTARG]])
; CHECK2-NEXT: br label [[OMP_PAR_OUTLINED_EXIT:%.*]]
; CHECK2: omp.par.outlined.exit:
@@ -5826,15 +5842,16 @@ entry:
; CHECK2-NEXT: br label [[ENTRY_SPLIT_SPLIT:%.*]]
; CHECK2: entry.split.split:
; CHECK2-NEXT: call void (...) @foo()
-; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..39, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR]])
+; CHECK2-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr noundef nonnull align 8 dereferenceable(24) @[[GLOB1]], i32 noundef 1, ptr noundef nonnull @.omp_outlined..39, ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[A_ADDR1]])
; CHECK2-NEXT: ret void
;
;
+; CHECK2: Function Attrs: norecurse nounwind
; CHECK2-LABEL: define {{[^@]+}}@merge_2_unmergable_1..omp_par
; CHECK2-SAME: (ptr noalias [[TID_ADDR:%.*]], ptr noalias [[ZERO_ADDR:%.*]], ptr [[TMP0:%.*]]) #[[ATTR0]] {
; CHECK2-NEXT: omp.par.entry:
-; CHECK2-NEXT: [[GEP_A_ADDR:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
-; CHECK2-NEXT: [[LOADGEP_A_ADDR:%.*]] = load ptr, ptr [[GEP_A_ADDR]], align 8
+; CHECK2-NEXT: [[GEP_A_ADDR1:%.*]] = getelementptr { ptr }, ptr [[TMP0]], i32 0, i32 0
+; CHECK2-NEXT: [[LOADGEP_A_ADDR1:%.*]] = load ptr, ptr [[GEP_A_ADDR1]], align 8
; CHECK2-NEXT: [[TID_ADDR_LOCAL:%.*]] = alloca i32, align 4
; CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[TID_ADDR]], align 4
; CHECK2-NEXT: store i32 [[TMP1]], ptr [[TID_ADDR_LOCAL]], align 4
@@ -5843,10 +5860,10 @@ entry:
; CHECK2: omp.par.region:
; CHECK2-NEXT: br label [[OMP_PAR_MERGED:%.*]]
; CHECK2: omp.par.merged:
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..37(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..37(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
-; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..38(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR]])
+; CHECK2-NEXT: call void (ptr, ptr, ...) @.omp_outlined..38(ptr [[TID_ADDR]], ptr [[ZERO_ADDR]], ptr nocapture nofree noundef nonnull readonly align 4 dereferenceable(4) [[LOADGEP_A_ADDR1]])
; CHECK2-NEXT: br label [[ENTRY_SPLIT:%.*]]
; CHECK2: entry.split:
; CHECK2-NEXT: br label [[OMP_PAR_REGION_SPLIT:%.*]]
@@ -5881,3 +5898,14 @@ entry:
; CHECK2-NEXT: call void @use(i32 [[TMP0]])
; CHECK2-NEXT: ret void
;
+;.
+; CHECK2: attributes #[[ATTR0]] = { norecurse nounwind }
+; CHECK2: attributes #[[ATTR1:[0-9]+]] = { nounwind }
+; CHECK2: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
+; CHECK2: attributes #[[ATTR3:[0-9]+]] = { convergent nounwind }
+;.
+; CHECK2: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+; CHECK2: [[META1:![0-9]+]] = !{i32 7, !"openmp", i32 50}
+; CHECK2: [[META2:![0-9]+]] = !{!3}
+; CHECK2: [[META3:![0-9]+]] = !{i64 2, i64 -1, i64 -1, i1 true}
+;.
>From 75259ea7a512bbcbc627101429031a4824a444a0 Mon Sep 17 00:00:00 2001
From: vidsinghal <vidush.sl at gmail.com>
Date: Sat, 20 Apr 2024 13:23:52 -0400
Subject: [PATCH 2/3] change inttoptr, arithmetic, ptrtoint to a GEP
---
.../Transforms/IPO/AttributorAttributes.cpp | 59 ++++------
.../Attributor/ArgumentPromotion/array.ll | 39 ++-----
.../Attributor/ArgumentPromotion/attrs.ll | 12 +-
.../Attributor/ArgumentPromotion/byval-2.ll | 12 +-
.../Attributor/ArgumentPromotion/byval.ll | 20 ++--
.../Attributor/ArgumentPromotion/fp80.ll | 4 +-
.../Attributor/ArgumentPromotion/inalloca.ll | 28 ++---
llvm/test/Transforms/Attributor/allocator.ll | 108 +++++++++---------
8 files changed, 130 insertions(+), 152 deletions(-)
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 25b24d154f5525..3a23a068f09613 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -12851,25 +12851,19 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
LoadInst *OldLoadInst = cast<LoadInst>(LocalInst);
Value *PointerOperand = OldLoadInst->getPointerOperand();
- // We need to shift the old start offset by the difference between the
- // Old offset and the New offset.
- Value *ShiftValueForPointerOperand = ConstantInt::get(
- OldLoadInst->getContext(),
- APInt(32, (OldOffsetRange.Offset - NewOffsetRange.Offset)));
- // Cast ptr to 32 bit integer
- CastInst *PtrOperandToInt = PtrToIntInst::CreatePointerCast(
- PointerOperand, Type::getInt32Ty(OldLoadInst->getContext()), "",
- OldLoadInst);
- // Subtract shift amount from old offset
- BinaryOperator *NewPointerOperandInt = BinaryOperator::Create(
- Instruction::Sub, PtrOperandToInt, ShiftValueForPointerOperand,
- "", OldLoadInst);
- // Convert Int to ptr.
- CastInst *IntToPtr = new IntToPtrInst(
- NewPointerOperandInt, OldLoadInst->getPointerOperandType(), "",
- OldLoadInst);
+ IntegerType *Int8TyInteger =
+ IntegerType::get(LocalInst->getContext(), 8);
+ IntegerType *Int64TyInteger =
+ IntegerType::get(LocalInst->getContext(), 64);
+ Value *indexList[2] = {
+ ConstantInt::get(Int64TyInteger, 0),
+ ConstantInt::get(Int64TyInteger,
+ NewOffsetRange.Offset - OldOffsetRange.Offset)};
+ Value *GepToNewAddress = GetElementPtrInst::Create(
+ Int8TyInteger, PointerOperand, indexList, "NewGep", OldLoadInst);
+
LoadInst *NewLoadInst =
- new LoadInst(OldLoadInst->getType(), IntToPtr,
+ new LoadInst(OldLoadInst->getType(), GepToNewAddress,
OldLoadInst->getName(), OldLoadInst);
Changed |= A.changeAfterManifest(IRPosition::inst(*OldLoadInst),
*NewLoadInst);
@@ -12879,24 +12873,19 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
StoreInst *OldStoreInst = cast<StoreInst>(LocalInst);
Value *PointerOperand = OldStoreInst->getPointerOperand();
- Value *ShiftValueForPointerOperand = ConstantInt::get(
- OldStoreInst->getContext(),
- APInt(32, (OldOffsetRange.Offset - NewOffsetRange.Offset)));
-
- // Cast ptr to 32 bit integer
- CastInst *PtrOperandToInt = PtrToIntInst::CreatePointerCast(
- PointerOperand, Type::getInt32Ty(OldStoreInst->getContext()), "",
- OldStoreInst);
- // Subtract shift amount from old offset
- BinaryOperator *NewPointerOperandInt = BinaryOperator::Create(
- Instruction::Sub, PtrOperandToInt, ShiftValueForPointerOperand,
- "", OldStoreInst);
- // Convert Int to ptr.
- CastInst *IntToPtr = new IntToPtrInst(
- NewPointerOperandInt, OldStoreInst->getPointerOperandType(), "",
- OldStoreInst);
+ IntegerType *Int8TyInteger =
+ IntegerType::get(LocalInst->getContext(), 8);
+ IntegerType *Int64TyInteger =
+ IntegerType::get(LocalInst->getContext(), 64);
+ Value *indexList[2] = {
+ ConstantInt::get(Int64TyInteger, 0),
+ ConstantInt::get(Int64TyInteger,
+ NewOffsetRange.Offset - OldOffsetRange.Offset)};
+ Value *GepToNewAddress = GetElementPtrInst::Create(
+ Int8TyInteger, PointerOperand, indexList, "NewGep", OldStoreInst);
+
StoreInst *NewStoreInst = new StoreInst(
- OldStoreInst->getValueOperand(), IntToPtr, OldStoreInst);
+ OldStoreInst->getValueOperand(), GepToNewAddress, OldStoreInst);
Changed |= A.changeAfterManifest(IRPosition::inst(*OldStoreInst),
*NewStoreInst);
break;
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll
index d5d18eaa4f7980..e8ed3b07881053 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/array.ll
@@ -9,26 +9,17 @@ declare void @use(ptr nocapture readonly %arg)
define void @caller() {
; TUNIT-LABEL: define {{[^@]+}}@caller() {
; TUNIT-NEXT: entry:
-; TUNIT-NEXT: [[LEFT1:%.*]] = alloca i8, i32 2147483647, align 4
-; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[LEFT1]], align 4
-; TUNIT-NEXT: [[LEFT1_0_1:%.*]] = getelementptr [3 x i32], ptr [[LEFT1]], i64 0, i64 1
-; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[LEFT1_0_1]], align 4
-; TUNIT-NEXT: [[LEFT1_0_2:%.*]] = getelementptr [3 x i32], ptr [[LEFT1]], i64 0, i64 2
-; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[LEFT1_0_2]], align 4
+; TUNIT-NEXT: [[LEFT:%.*]] = alloca [3 x i32], align 4
+; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[LEFT]], align 4
+; TUNIT-NEXT: [[LEFT_0_1:%.*]] = getelementptr [3 x i32], ptr [[LEFT]], i64 0, i64 1
+; TUNIT-NEXT: [[TMP1:%.*]] = load i32, ptr [[LEFT_0_1]], align 4
+; TUNIT-NEXT: [[LEFT_0_2:%.*]] = getelementptr [3 x i32], ptr [[LEFT]], i64 0, i64 2
+; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[LEFT_0_2]], align 4
; TUNIT-NEXT: call void @callee(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define {{[^@]+}}@caller() {
; CGSCC-NEXT: entry:
-; CGSCC-NEXT: [[LEFT1:%.*]] = alloca i8, i32 12, align 4
-; CGSCC-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[LEFT1]] to i32
-; CGSCC-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], -4
-; CGSCC-NEXT: [[TMP2:%.*]] = inttoptr i32 [[TMP1]] to ptr
-; CGSCC-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-; CGSCC-NEXT: [[TMP4:%.*]] = ptrtoint ptr undef to i32
-; CGSCC-NEXT: [[TMP5:%.*]] = sub i32 [[TMP4]], 4
-; CGSCC-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
-; CGSCC-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
; CGSCC-NEXT: call void @callee(i32 undef, i32 undef, i32 undef)
; CGSCC-NEXT: ret void
;
@@ -39,25 +30,19 @@ entry:
}
define internal void @callee(ptr noalias %arg) {
-; CHECK: Function Attrs: memory(readwrite, argmem: none)
; CHECK-LABEL: define {{[^@]+}}@callee
-; CHECK-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-SAME: (i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i32 [[TMP2:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ARG_PRIV:%.*]] = alloca [3 x i32], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[ARG_PRIV]], align 4
-; CHECK-NEXT: [[ARG_PRIV_B4:%.*]] = getelementptr i8, ptr [[ARG_PRIV]], i64 4
-; CHECK-NEXT: store i32 [[TMP1]], ptr [[ARG_PRIV_B4]], align 4
-; CHECK-NEXT: [[ARG_PRIV_B8:%.*]] = getelementptr i8, ptr [[ARG_PRIV]], i64 8
-; CHECK-NEXT: store i32 [[TMP2]], ptr [[ARG_PRIV_B8]], align 4
-; CHECK-NEXT: call void @use(ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(12) [[ARG_PRIV]])
+; CHECK-NEXT: [[ARG_PRIV_0_1:%.*]] = getelementptr [3 x i32], ptr [[ARG_PRIV]], i64 0, i64 1
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[ARG_PRIV_0_1]], align 4
+; CHECK-NEXT: [[ARG_PRIV_0_2:%.*]] = getelementptr [3 x i32], ptr [[ARG_PRIV]], i64 0, i64 2
+; CHECK-NEXT: store i32 [[TMP2]], ptr [[ARG_PRIV_0_2]], align 4
+; CHECK-NEXT: call void @use(ptr noalias nocapture noundef nonnull readonly align 4 dereferenceable(12) [[ARG_PRIV]])
; CHECK-NEXT: ret void
;
entry:
call void @use(ptr %arg)
ret void
}
-;.
-; TUNIT: attributes #[[ATTR0]] = { memory(readwrite, argmem: none) }
-;.
-; CGSCC: attributes #[[ATTR0]] = { memory(readwrite, argmem: none) }
-;.
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
index b1d35eea7b9f1b..7095edd7b2ae68 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
@@ -15,10 +15,10 @@ define internal i32 @f(ptr byval(%struct.ss) %b, ptr byval(i32) %X, i32 %i) noun
; CHECK-NEXT: store i32 [[TMP2]], ptr [[X_PRIV]], align 4
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
+; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[TMP1]] = load i32, ptr [[B_PRIV]], align 8
+; CHECK-NEXT: [[TMP2]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 8
; CHECK-NEXT: store i32 0, ptr [[X_PRIV]], align 4
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[X_PRIV]], align 4
@@ -48,8 +48,8 @@ define i32 @test(ptr %X) {
; TUNIT-NEXT: store i32 1, ptr [[S1]], align 8
; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S1]], align 8
-; TUNIT-NEXT: [[S1_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
-; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_0_1]], align 8
+; TUNIT-NEXT: [[S1_B4:%.*]] = getelementptr i8, ptr [[S1]], i64 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_B4]], align 8
; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
; TUNIT-NEXT: [[C:%.*]] = call i32 @f(i32 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret i32 [[C]]
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
index 1d68cae96237da..a9ad487280403c 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
@@ -13,10 +13,10 @@ define internal void @f(ptr byval(%struct.ss) %b, ptr byval(i32) %X) nounwind
; CHECK-NEXT: store i32 [[TMP2]], ptr [[X_PRIV]], align 4
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 8
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
+; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[TMP1]] = load i32, ptr [[B_PRIV]], align 8
+; CHECK-NEXT: [[TMP2]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 8
; CHECK-NEXT: store i32 0, ptr [[X_PRIV]], align 4
; CHECK-NEXT: ret void
@@ -40,8 +40,8 @@ define i32 @test(ptr %X) {
; TUNIT-NEXT: store i32 1, ptr [[S1]], align 8
; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S1]], align 8
-; TUNIT-NEXT: [[S1_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
-; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_0_1]], align 8
+; TUNIT-NEXT: [[S1_B4:%.*]] = getelementptr i8, ptr [[S1]], i64 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_B4]], align 8
; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[X]], align 4
; TUNIT-NEXT: call void @f(i32 [[TMP0]], i64 [[TMP1]], i32 [[TMP2]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret i32 0
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
index 99121f876a2268..897038db54c28d 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
@@ -13,9 +13,9 @@ define internal i32 @f(ptr byval(%struct.ss) %b) nounwind {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 8
+; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[TMP1]] = load i32, ptr [[B_PRIV]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 8
; CHECK-NEXT: ret i32 [[TMP1]]
@@ -35,9 +35,9 @@ define internal i32 @g(ptr byval(%struct.ss) align 32 %b) nounwind {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[B_PRIV:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[B_PRIV]], align 4
-; CHECK-NEXT: [[B_PRIV_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[B_PRIV]], i64 0, i32 1
-; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_0_1]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_PRIV]], align 32
+; CHECK-NEXT: [[B_PRIV_B4:%.*]] = getelementptr i8, ptr [[B_PRIV]], i64 4
+; CHECK-NEXT: store i64 [[TMP1]], ptr [[B_PRIV_B4]], align 4
+; CHECK-NEXT: [[TMP1]] = load i32, ptr [[B_PRIV]], align 32
; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; CHECK-NEXT: store i32 [[TMP2]], ptr [[B_PRIV]], align 32
; CHECK-NEXT: ret i32 [[TMP2]]
@@ -59,12 +59,12 @@ define i32 @main() nounwind {
; TUNIT-NEXT: store i32 1, ptr [[S1]], align 32
; TUNIT-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_SS:%.*]], ptr [[S1]], i32 0, i32 1
; TUNIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[S1]], align 8
-; TUNIT-NEXT: [[S1_0_1:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
-; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_0_1]], align 8
+; TUNIT-NEXT: [[S1_B42:%.*]] = getelementptr i8, ptr [[S1]], i64 4
+; TUNIT-NEXT: [[TMP1:%.*]] = load i64, ptr [[S1_B42]], align 8
; TUNIT-NEXT: [[C0:%.*]] = call i32 @f(i32 [[TMP0]], i64 [[TMP1]]) #[[ATTR1:[0-9]+]]
; TUNIT-NEXT: [[TMP2:%.*]] = load i32, ptr [[S1]], align 32
-; TUNIT-NEXT: [[S1_0_12:%.*]] = getelementptr [[STRUCT_SS]], ptr [[S1]], i64 0, i32 1
-; TUNIT-NEXT: [[TMP3:%.*]] = load i64, ptr [[S1_0_12]], align 32
+; TUNIT-NEXT: [[S1_B4:%.*]] = getelementptr i8, ptr [[S1]], i64 4
+; TUNIT-NEXT: [[TMP3:%.*]] = load i64, ptr [[S1_B4]], align 32
; TUNIT-NEXT: [[C1:%.*]] = call i32 @g(i32 [[TMP2]], i64 [[TMP3]]) #[[ATTR1]]
; TUNIT-NEXT: [[A:%.*]] = add i32 [[C0]], [[C1]]
; TUNIT-NEXT: ret i32 [[A]]
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
index 6e35843bb570f6..101850f464c413 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
@@ -82,8 +82,8 @@ define internal i64 @CaptureAStruct(ptr byval(%struct.Foo) %a) {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: [[A_PRIV:%.*]] = alloca [[STRUCT_FOO:%.*]], align 8
; CGSCC-NEXT: store i32 [[TMP0]], ptr [[A_PRIV]], align 4
-; CGSCC-NEXT: [[A_PRIV_0_1:%.*]] = getelementptr [[STRUCT_FOO]], ptr [[A_PRIV]], i64 0, i32 1
-; CGSCC-NEXT: store i64 [[TMP1]], ptr [[A_PRIV_0_1]], align 8
+; CGSCC-NEXT: [[A_PRIV_B8:%.*]] = getelementptr i8, ptr [[A_PRIV]], i64 8
+; CGSCC-NEXT: store i64 [[TMP1]], ptr [[A_PRIV_B8]], align 8
; CGSCC-NEXT: [[A_PTR1:%.*]] = alloca i8, i32 8, align 8
; CGSCC-NEXT: br label [[LOOP:%.*]]
; CGSCC: loop:
diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll
index 957a26ff7176be..fd16e665dba420 100644
--- a/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll
+++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll
@@ -8,7 +8,7 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
; Argpromote + sroa should change this to passing the two integers by value.
define internal i32 @f(ptr inalloca(%struct.ss) %s) {
-; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read)
+; CHECK: Function Attrs: nofree norecurse nosync nounwind willreturn memory(argmem: read)
; CHECK-LABEL: define {{[^@]+}}@f
; CHECK-SAME: (ptr noalias nocapture nofree noundef nonnull inalloca([[STRUCT_SS:%.*]]) align 4 dereferenceable(8) [[S:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
@@ -27,7 +27,7 @@ entry:
}
define i32 @main() {
-; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
+; TUNIT: Function Attrs: nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@main
; TUNIT-SAME: () #[[ATTR1:[0-9]+]] {
; TUNIT-NEXT: entry:
@@ -38,7 +38,7 @@ define i32 @main() {
; TUNIT-NEXT: [[R:%.*]] = call i32 @f(ptr noalias nocapture nofree noundef nonnull inalloca([[STRUCT_SS]]) align 4 dereferenceable(8) [[S]]) #[[ATTR2:[0-9]+]]
; TUNIT-NEXT: ret i32 [[R]]
;
-; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
+; CGSCC: Function Attrs: nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@main
; CGSCC-SAME: () #[[ATTR1:[0-9]+]] {
; CGSCC-NEXT: entry:
@@ -60,9 +60,9 @@ entry:
; Argpromote can't promote %a because of the icmp use.
define internal i1 @g(ptr %a, ptr inalloca(%struct.ss) %b) nounwind {
-; CGSCC: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
+; CGSCC: Function Attrs: nofree norecurse nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@g
-; CGSCC-SAME: (ptr noalias nocapture nofree noundef nonnull readnone align 4 dereferenceable(8) [[A:%.*]], ptr noalias nocapture nofree noundef nonnull writeonly inalloca([[STRUCT_SS:%.*]]) align 4 dereferenceable(8) [[B:%.*]]) #[[ATTR2:[0-9]+]] {
+; CGSCC-SAME: (ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(8) [[A:%.*]], ptr noalias nocapture nofree nonnull writeonly inalloca([[STRUCT_SS:%.*]]) align 4 dereferenceable(8) [[B:%.*]]) #[[ATTR2:[0-9]+]] {
; CGSCC-NEXT: entry:
; CGSCC-NEXT: ret i1 undef
;
@@ -72,13 +72,13 @@ entry:
}
define i32 @test() {
-; TUNIT: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
+; TUNIT: Function Attrs: nofree norecurse nosync nounwind willreturn memory(none)
; TUNIT-LABEL: define {{[^@]+}}@test
; TUNIT-SAME: () #[[ATTR1]] {
; TUNIT-NEXT: entry:
; TUNIT-NEXT: ret i32 0
;
-; CGSCC: Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
+; CGSCC: Function Attrs: nofree nosync nounwind willreturn memory(none)
; CGSCC-LABEL: define {{[^@]+}}@test
; CGSCC-SAME: () #[[ATTR1]] {
; CGSCC-NEXT: entry:
@@ -90,12 +90,12 @@ entry:
ret i32 0
}
;.
-; TUNIT: attributes #[[ATTR0]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) }
-; TUNIT: attributes #[[ATTR1]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }
-; TUNIT: attributes #[[ATTR2]] = { nofree nosync nounwind willreturn memory(read) }
+; TUNIT: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind willreturn memory(argmem: read) }
+; TUNIT: attributes #[[ATTR1]] = { nofree norecurse nosync nounwind willreturn memory(none) }
+; TUNIT: attributes #[[ATTR2]] = { nofree nosync nounwind willreturn }
;.
-; CGSCC: attributes #[[ATTR0]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: read) }
-; CGSCC: attributes #[[ATTR1]] = { mustprogress nofree nosync nounwind willreturn memory(none) }
-; CGSCC: attributes #[[ATTR2]] = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) }
-; CGSCC: attributes #[[ATTR3]] = { nofree willreturn memory(read) }
+; CGSCC: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind willreturn memory(argmem: read) }
+; CGSCC: attributes #[[ATTR1]] = { nofree nosync nounwind willreturn memory(none) }
+; CGSCC: attributes #[[ATTR2]] = { nofree norecurse nosync nounwind willreturn memory(none) }
+; CGSCC: attributes #[[ATTR3]] = { willreturn }
;.
diff --git a/llvm/test/Transforms/Attributor/allocator.ll b/llvm/test/Transforms/Attributor/allocator.ll
index 6c8d3d6553f41e..eb7bb7061e0a98 100644
--- a/llvm/test/Transforms/Attributor/allocator.ll
+++ b/llvm/test/Transforms/Attributor/allocator.ll
@@ -7,20 +7,20 @@
@.str = private unnamed_addr constant [17 x i8] c"The value is %d\0A\00", align 1
;.
-; CHECK: @[[_STR:[a-zA-Z0-9_$"\\.-]+]] = private unnamed_addr constant [17 x i8] c"The value is %d\0A\00", align 1
+; CHECK: @.str = private unnamed_addr constant [17 x i8] c"The value is %d\0A\00", align 1
;.
define dso_local void @positive_alloca_1(i32 noundef %val) #0 {
; CHECK-LABEL: define dso_local void @positive_alloca_1
; CHECK-SAME: (i32 noundef [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 4, align 4
-; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 4, align 4
-; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR1]], align 4
-; CHECK-NEXT: store i32 10, ptr [[F2]], align 4
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[F2]], align 4
+; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i64, align 4
+; CHECK-NEXT: [[F:%.*]] = alloca [[STRUCT_FOO:%.*]], align 4
+; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR]], align 4
+; CHECK-NEXT: store i32 10, ptr [[F]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[F]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
-; CHECK-NEXT: store i32 [[ADD]], ptr [[F2]], align 4
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
+; CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[F]], align 4
; CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP1]], [[VAL]]
; CHECK-NEXT: [[CALL:%.*]] = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(17) @.str, i32 noundef [[ADD3]])
; CHECK-NEXT: ret void
@@ -49,11 +49,11 @@ define dso_local void @positive_malloc_1(ptr noundef %val) #0 {
; CHECK-LABEL: define dso_local void @positive_malloc_1
; CHECK-SAME: (ptr nocapture nofree noundef readonly [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR1]], align 8
+; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR]], align 8
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 12)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F2]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 10
; CHECK-NEXT: store i32 [[ADD]], ptr [[CALL]], align 4
@@ -86,11 +86,11 @@ define dso_local void @positive_malloc_2(ptr noundef %val) #0 {
; CHECK-LABEL: define dso_local void @positive_malloc_2
; CHECK-SAME: (ptr nocapture nofree noundef readonly [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: [[F3:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR1]], align 8
+; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR]], align 8
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 60)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F3]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[CALL]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 4
@@ -125,19 +125,19 @@ define dso_local ptr @negative_test_escaping_pointer(i32 noundef %val) #0 {
; CHECK-LABEL: define dso_local ptr @negative_test_escaping_pointer
; CHECK-SAME: (i32 noundef [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 4, align 4
-; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR1]], align 4
+; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR]], align 4
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 16)
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F2]], align 8
-; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F2]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[F]], align 8
; CHECK-NEXT: store i32 2, ptr [[TMP0]], align 8
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 10, [[VAL]]
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[F2]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[F]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 8
; CHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], [[ADD]]
; CHECK-NEXT: store i32 [[ADD2]], ptr [[TMP1]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[F2]], align 8
+; CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[F]], align 8
; CHECK-NEXT: ret ptr [[TMP3]]
;
entry:
@@ -168,13 +168,13 @@ define dso_local void @positive_test_not_a_single_start_offset(i32 noundef %val)
; CHECK-LABEL: define dso_local void @positive_test_not_a_single_start_offset
; CHECK-SAME: (i32 noundef [[VAL:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 4, align 4
-; CHECK-NEXT: [[F2:%.*]] = alloca i8, i32 5, align 4
-; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR1]], align 4
+; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[F:%.*]] = alloca [[STRUCT_FOO:%.*]], align 4
+; CHECK-NEXT: store i32 [[VAL]], ptr [[VAL_ADDR]], align 4
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 2, [[VAL]]
-; CHECK-NEXT: store i32 [[MUL]], ptr [[F2]], align 4
+; CHECK-NEXT: store i32 [[MUL]], ptr [[F]], align 4
; CHECK-NEXT: [[CALL:%.*]] = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(17) @.str, i32 noundef [[MUL]])
-; CHECK-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_FOO:%.*]], ptr [[F2]], i32 0, i32 2
+; CHECK-NEXT: [[C:%.*]] = getelementptr inbounds [[STRUCT_FOO]], ptr [[F]], i32 0, i32 2
; CHECK-NEXT: [[CALL3:%.*]] = call i32 (ptr, ...) @printf(ptr noundef nonnull dereferenceable(17) @.str, i32 noundef 67)
; CHECK-NEXT: ret void
;
@@ -202,7 +202,7 @@ entry:
define dso_local void @positive_test_reduce_array_allocation_1() {
; CHECK-LABEL: define dso_local void @positive_test_reduce_array_allocation_1() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ARRAY1:%.*]] = alloca i8, i32 4, align 8
+; CHECK-NEXT: [[ARRAY1:%.*]] = alloca ptr, i32 10, align 8
; CHECK-NEXT: store i32 0, ptr [[ARRAY1]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAY1]], align 8
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 2
@@ -239,15 +239,15 @@ define dso_local void @baz(ptr noundef %val, i32 noundef %arrayLength) #0 {
; CHECK-LABEL: define dso_local void @baz
; CHECK-SAME: (ptr nocapture nofree noundef readonly [[VAL:%.*]], i32 noundef [[ARRAYLENGTH:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[VAL_ADDR1:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: [[ARRAYLENGTH_ADDR2:%.*]] = alloca i8, i32 4, align 4
-; CHECK-NEXT: [[F3:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR1]], align 8
-; CHECK-NEXT: store i32 [[ARRAYLENGTH]], ptr [[ARRAYLENGTH_ADDR2]], align 4
+; CHECK-NEXT: [[VAL_ADDR:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[ARRAYLENGTH_ADDR:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[F:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: store ptr [[VAL]], ptr [[VAL_ADDR]], align 8
+; CHECK-NEXT: store i32 [[ARRAYLENGTH]], ptr [[ARRAYLENGTH_ADDR]], align 4
; CHECK-NEXT: [[CONV:%.*]] = sext i32 [[ARRAYLENGTH]] to i64
; CHECK-NEXT: [[MUL:%.*]] = mul i64 4, [[CONV]]
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef [[MUL]])
-; CHECK-NEXT: store ptr [[CALL]], ptr [[F3]], align 8
+; CHECK-NEXT: store ptr [[CALL]], ptr [[F]], align 8
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[VAL]], align 4
; CHECK-NEXT: store i32 [[TMP0]], ptr [[CALL]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[CALL]], align 4
@@ -283,8 +283,8 @@ entry:
define dso_local void @positive_test_reduce_array_allocation_2() #0 {
; CHECK-LABEL: define dso_local void @positive_test_reduce_array_allocation_2() {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[ARRAY1:%.*]] = alloca i8, i32 8, align 8
-; CHECK-NEXT: [[I2:%.*]] = alloca i8, i32 4, align 4
+; CHECK-NEXT: [[ARRAY1:%.*]] = alloca ptr, align 8
+; CHECK-NEXT: [[I2:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[CALL:%.*]] = call noalias ptr @malloc(i64 noundef 40000)
; CHECK-NEXT: store ptr [[CALL]], ptr [[ARRAY1]], align 8
; CHECK-NEXT: store i32 0, ptr [[I2]], align 4
@@ -433,21 +433,20 @@ define dso_local void @pthread_test(){
; TUNIT-LABEL: define dso_local void @pthread_test() {
; TUNIT-NEXT: [[ARG1:%.*]] = alloca i8, align 8
; TUNIT-NEXT: [[THREAD:%.*]] = alloca i64, align 8
-; TUNIT-NEXT: [[CALL1:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_remain_same, ptr noundef nonnull align 8 dereferenceable(1) [[ARG1]])
-; TUNIT-NEXT: [[F1:%.*]] = alloca i8, i32 4, align 4
-; TUNIT-NEXT: [[CALL2:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_be_reduced, ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(12) undef)
+; TUNIT-NEXT: [[CALL1:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noalias nocapture noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_remain_same, ptr noundef nonnull align 8 dereferenceable(1) [[ARG1]])
+; TUNIT-NEXT: [[CALL2:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noalias nocapture noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_be_reduced, ptr noalias nocapture nofree nonnull readnone align 4 dereferenceable(12) undef)
; TUNIT-NEXT: [[F2:%.*]] = alloca [[STRUCT_FOO:%.*]], align 4
-; TUNIT-NEXT: [[CALL3:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noundef align 4294967296 null, ptr noundef nonnull @pthread_check_captured_pointer, ptr noundef nonnull align 4 dereferenceable(12) [[F2]])
+; TUNIT-NEXT: [[CALL3:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noalias nocapture noundef align 4294967296 null, ptr noundef nonnull @pthread_check_captured_pointer, ptr noundef nonnull align 4 dereferenceable(12) [[F2]])
; TUNIT-NEXT: ret void
;
; CGSCC-LABEL: define dso_local void @pthread_test() {
; CGSCC-NEXT: [[ARG1:%.*]] = alloca i8, align 8
; CGSCC-NEXT: [[THREAD:%.*]] = alloca i64, align 8
-; CGSCC-NEXT: [[CALL1:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_remain_same, ptr noundef nonnull align 8 dereferenceable(1) [[ARG1]])
+; CGSCC-NEXT: [[CALL1:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noalias nocapture noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_remain_same, ptr noundef nonnull align 8 dereferenceable(1) [[ARG1]])
; CGSCC-NEXT: [[F:%.*]] = alloca [[STRUCT_FOO:%.*]], align 4
-; CGSCC-NEXT: [[CALL2:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_be_reduced, ptr noalias nocapture nofree noundef nonnull readonly align 4 dereferenceable(12) [[F]])
+; CGSCC-NEXT: [[CALL2:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noalias nocapture noundef align 4294967296 null, ptr noundef nonnull @pthread_allocation_should_be_reduced, ptr nofree noundef nonnull readonly align 4 dereferenceable(12) [[F]])
; CGSCC-NEXT: [[F2:%.*]] = alloca [[STRUCT_FOO]], align 4
-; CGSCC-NEXT: [[CALL3:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noundef align 4294967296 null, ptr noundef nonnull @pthread_check_captured_pointer, ptr noundef nonnull align 4 dereferenceable(12) [[F2]])
+; CGSCC-NEXT: [[CALL3:%.*]] = call i32 @pthread_create(ptr noundef nonnull align 8 dereferenceable(8) [[THREAD]], ptr noalias nocapture noundef align 4294967296 null, ptr noundef nonnull @pthread_check_captured_pointer, ptr noundef nonnull align 4 dereferenceable(12) [[F2]])
; CGSCC-NEXT: ret void
;
%arg1 = alloca i8, align 8
@@ -512,19 +511,19 @@ define dso_local void @alloca_array_multi_offset(){
; CHECK-LABEL: define dso_local void @alloca_array_multi_offset
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[I2:%.*]] = alloca i8, i32 4, align 4
-; CHECK-NEXT: store i32 0, ptr [[I2]], align 4
+; CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
+; CHECK-NEXT: store i32 0, ptr [[I]], align 4
; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I2]], align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 10
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
; CHECK: for.body:
; CHECK-NEXT: br label [[FOR_INC:%.*]]
; CHECK: for.inc:
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I2]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 2
-; CHECK-NEXT: store i32 [[ADD]], ptr [[I2]], align 4
+; CHECK-NEXT: store i32 [[ADD]], ptr [[I]], align 4
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
; CHECK-NEXT: ret void
@@ -571,8 +570,13 @@ declare i32 @printf(ptr noundef, ...) #1
; Function Attrs: nounwind allocsize(0)
declare noalias ptr @malloc(i64 noundef) #1
;.
-; CHECK: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind memory(none) }
+; TUNIT: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind memory(none) }
+;.
+; CGSCC: attributes #[[ATTR0]] = { nofree norecurse nosync nounwind memory(none) }
+;.
+; TUNIT: [[META0:![0-9]+]] = !{[[META1:![0-9]+]]}
+; TUNIT: [[META1]] = !{i64 2, i64 3, i1 false}
;.
-; CHECK: [[META0:![0-9]+]] = !{!1}
-; CHECK: [[META1:![0-9]+]] = !{i64 2, i64 3, i1 false}
+; CGSCC: [[META0:![0-9]+]] = !{[[META1:![0-9]+]]}
+; CGSCC: [[META1]] = !{i64 2, i64 3, i1 false}
;.
>From f4bbc49c4efcb4d5b90dea251a008b023109e35b Mon Sep 17 00:00:00 2001
From: vidsinghal <vidush.sl at gmail.com>
Date: Sat, 20 Apr 2024 13:57:52 -0400
Subject: [PATCH 3/3] change alloca to a char array
---
llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 3a23a068f09613..dc985261ca7c65 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -12801,16 +12801,15 @@ struct AAAllocationInfoImpl : public AAAllocationInfo {
case Instruction::Alloca: {
AllocaInst *AI = cast<AllocaInst>(I);
+
Type *CharType = Type::getInt8Ty(I->getContext());
- auto *NumBytesToValue =
- ConstantInt::get(I->getContext(), APInt(32, NumBytesToAllocate));
+ Type *CharArrayType = ArrayType::get(CharType, NumBytesToAllocate);
BasicBlock::iterator insertPt = AI->getIterator();
insertPt = std::next(insertPt);
- AllocaInst *NewAllocaInst =
- new AllocaInst(CharType, AI->getAddressSpace(), NumBytesToValue,
- AI->getAlign(), AI->getName(), insertPt);
+ AllocaInst *NewAllocaInst = new AllocaInst(
+ CharArrayType, AI->getAddressSpace(), AI->getName(), insertPt);
Changed |= A.changeAfterManifest(IRPosition::inst(*AI), *NewAllocaInst);
break;
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