[llvm] [TableGen] New tblgen Pattern bit to disable GISel pattern imports (PR #88382)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 19 08:23:08 PDT 2024
https://github.com/jofrn updated https://github.com/llvm/llvm-project/pull/88382
>From f4e7c49aebeed2d253049d86943c36681c17f84c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 11 Apr 2024 01:15:36 -0400
Subject: [PATCH 1/8] [TableGen] New tblgen Instruction bit to disable DAGISel
pattern imports
Added a new DAGISelShouldIgnore property to class Instruction in Target.td, similar to FastISelShouldIgnore. This allows one to avoid a record's DAGISel .td implementation and .inc generation.
---
llvm/include/llvm/Target/Target.td | 4 ++++
llvm/utils/TableGen/Common/CodeGenInstruction.cpp | 1 +
llvm/utils/TableGen/Common/CodeGenInstruction.h | 1 +
llvm/utils/TableGen/DAGISelEmitter.cpp | 15 ++++++++++++++-
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 1f7dc6922f13e4..61dc04595b62b9 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -777,6 +777,10 @@ class Instruction : InstructionEncoding {
/// SelectionDAG can.
bit FastISelShouldIgnore = false;
+ /// Should DAGISel ignore this instruction. In cases where lowering may
+ /// be done elsewhere or is unneeded, DAGISel may skip over them.
+ bit DAGISelShouldIgnore = false;
+
/// HasPositionOrder: Indicate tablegen to sort the instructions by record
/// ID, so that instruction that is defined earlier can be sorted earlier
/// in the assembly matching table.
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index 18a4e7b0f18b23..a76efb76bfc319 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -465,6 +465,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isConvergent = R->getValueAsBit("isConvergent");
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
+ DAGISelShouldIgnore = R->getValueAsBit("DAGISelShouldIgnore");
variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
isAuthenticated = R->getValueAsBit("isAuthenticated");
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index b658259b4892ee..c36bfba245f66b 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -282,6 +282,7 @@ class CodeGenInstruction {
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
bool FastISelShouldIgnore : 1;
+ bool DAGISelShouldIgnore : 1;
bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index b43a8e659dd9c5..4fbeafdc2355fb 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -165,8 +165,21 @@ void DAGISelEmitter::run(raw_ostream &OS) {
// Add all the patterns to a temporary list so we can sort them.
Records.startTimer("Sort patterns");
std::vector<const PatternToMatch *> Patterns;
- for (const PatternToMatch &PTM : CGP.ptms())
+ for (const PatternToMatch &PTM : CGP.ptms()) {
+
+ // Disable import of patterns marked as ignore.
+ const TreePatternNode &Dst = PTM.getDstPattern();
+ if (!Dst.isLeaf()) {
+ const Record *Op = Dst.getOperator();
+ const bool shouldIgnore =
+ Op->isSubClassOf("Instruction") &&
+ CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
+ if (shouldIgnore)
+ continue;
+ }
+
Patterns.push_back(&PTM);
+ }
// We want to process the matches in order of minimal cost. Sort the patterns
// so the least cost one is at the start.
>From ad38450e674b228eeb5735aa41c7c5c9331e559c Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 12 Apr 2024 12:14:38 -0400
Subject: [PATCH 2/8] [TableGen] Add test for DAGISelShouldIgnore
This test ensures no .inc code is generated in the MatcherTable for the corresponding marked .td record.
---
.../TableGen/DAGISelEmitter-shouldignore.td | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 llvm/test/TableGen/DAGISelEmitter-shouldignore.td
diff --git a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
new file mode 100644
index 00000000000000..61dac212a716e0
--- /dev/null
+++ b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
@@ -0,0 +1,37 @@
+// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s -DIGNORE | FileCheck %s
+// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s --match-prefix=CHECK_LOOK | FileCheck --check-prefix=CHECK_LOOK %s
+
+include "llvm/Target/Target.td"
+def ISA : InstrInfo;
+def Tgt : Target { let InstructionSet = ISA; }
+def R0 : Register<"r0"> { let Namespace = "Tgt"; }
+def RC : RegisterClass<"Tgt", [i32], 32, (add R0)>;
+def Op : RegisterOperand<RC>;
+
+class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
+ let Namespace = "Tgt";
+ let OutOperandList = OOps;
+ let InOperandList = IOps;
+ let Pattern = Pat;
+}
+
+#ifdef IGNORE
+let DAGISelShouldIgnore = 1 in
+def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt), []>;
+// CHECK: static const unsigned char MatcherTable[] = {
+// CHECK-NEXT: 0
+// CHECK-NEXT: }; // Total Array size is 1 bytes
+#else
+def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt),
+ [(set Op:$rd, (add Op:$rs, Op:$rt))]>;
+// CHECK_LOOK:static const unsigned char MatcherTable[] = {
+// CHECK_LOOK-NEXT:/* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+// CHECK_LOOK-NEXT:/* 3*/ OPC_RecordChild0, // #0 = $rs
+// CHECK_LOOK-NEXT:/* 4*/ OPC_RecordChild1, // #1 = $rt
+// CHECK_LOOK-NEXT:/* 5*/ OPC_MorphNodeTo1None, TARGET_VAL(Tgt::ADD),
+// CHECK_LOOK-NEXT: MVT::i32, 2/*#Ops*/, 0, 1,
+// CHECK_LOOK-NEXT:// Src: (add:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt) - Complexity = {{[0-9]+}}
+// CHECK_LOOK-NEXT:// Dst: (ADD:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt)
+// CHECK_LOOK-NEXT: 0
+// CHECK_LOOK-NEXT:}; // Total Array size is 13 bytes
+#endif
>From c206eb60ee2c2881ffb895ea607f4a1918df11b3 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 18 Apr 2024 17:23:44 -0400
Subject: [PATCH 3/8] [TableGen] Added tblgen ISelShouldIgnore bit to class
Pattern to disable pattern imports in GISel
Via `let ISelShouldIgnore = 1`, a Pattern record can be disabled to skip pattern warnings in GlobalISel.
---
llvm/include/llvm/Target/TargetSelectionDAG.td | 1 +
.../TableGen/GlobalISelEmitterSkippedPatterns.td | 6 ++++++
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 10 ++++++----
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 13 ++++++++-----
llvm/utils/TableGen/GlobalISelEmitter.cpp | 15 ++++++++++-----
5 files changed, 31 insertions(+), 14 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index ea3520835fa07d..eeef17674eac55 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -1979,6 +1979,7 @@ class Pattern<dag patternToMatch, list<dag> resultInstrs> {
list<dag> ResultInstrs = resultInstrs;
list<Predicate> Predicates = []; // See class Instruction in Target.td.
int AddedComplexity = 0; // See class Instruction in Target.td.
+ bit ISelShouldIgnore = 0;
}
// Pat - A simple (but common) form of a pattern, which produces a simple result
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index 7c9df02ebd87c6..5554b6f9000535 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -1,4 +1,6 @@
// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null 2>&1 | FileCheck %s
+// RUN: llvm-tblgen -warn-on-skipped-patterns -gen-global-isel -I %p/../../include %s -I %p/Common -o /dev/null -DIGNORE 2>&1 | FileCheck --allow-empty --check-prefix=CHECK0 %s
+
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -23,6 +25,10 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
//===- Bail out when we define a variable twice wrt complex suboperands. -===//
+#ifdef IGNORE
+let ISelShouldIgnore = 1 in
+#endif
+// CHECK0-NOT: warning: Skipped pattern: Error: {{.*}}
// CHECK: warning: Skipped pattern: Error: Complex suboperand x referenced by different operands: complex_rr:x:y and complex_rr:x:z.
def : Pat<(add (complex_rr GPR32:$x, GPR32:$y),
(complex_rr GPR32:$x, GPR32:$z)),
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 7a5d2be3ae95b2..7bccdbe8b5d724 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4246,7 +4246,7 @@ static TreePatternNodePtr PromoteXForms(TreePatternNodePtr N) {
void CodeGenDAGPatterns::ParseOnePattern(
Record *TheDef, TreePattern &Pattern, TreePattern &Result,
- const std::vector<Record *> &InstImpResults) {
+ const std::vector<Record *> &InstImpResults, bool ShouldIgnore) {
// Inline pattern fragments and expand multiple alternatives.
Pattern.InlinePatternFragments();
@@ -4332,7 +4332,7 @@ void CodeGenDAGPatterns::ParseOnePattern(
AddPatternToMatch(&Pattern,
PatternToMatch(TheDef, Preds, T, Temp.getOnlyTree(),
InstImpResults, Complexity,
- TheDef->getID()));
+ TheDef->getID(), ShouldIgnore));
}
} else {
// Show a message about a dropped pattern with some info to make it
@@ -4378,7 +4378,8 @@ void CodeGenDAGPatterns::ParsePatterns() {
FindPatternInputsAndOutputs(Pattern, Pattern.getTree(j), InstInputs,
InstResults, InstImpResults);
- ParseOnePattern(CurPattern, Pattern, Result, InstImpResults);
+ ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
+ CurPattern->getValueAsBit("ISelShouldIgnore"));
}
}
@@ -4410,7 +4411,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
PatternsToMatch.emplace_back(P.getSrcRecord(), P.getPredicates(),
std::move(NewSrc), std::move(NewDst),
P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), Check);
+ Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
@@ -4781,6 +4782,7 @@ void CodeGenDAGPatterns::GenerateVariants() {
Variant, PatternsToMatch[i].getDstPatternShared(),
PatternsToMatch[i].getDstRegs(),
PatternsToMatch[i].getAddedComplexity(), Record::getNewUID(Records),
+ PatternsToMatch[i].getISelShouldIgnore(),
PatternsToMatch[i].getHwModeFeatures());
}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 7fcd39a9e940cc..6a85a579658892 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1057,16 +1057,17 @@ class PatternToMatch {
TreePatternNodePtr DstPattern; // Resulting pattern.
std::vector<Record *> Dstregs; // Physical register defs being matched.
std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- unsigned ID; // Unique ID for the record.
+ int AddedComplexity; // Add to matching pattern complexity.
+ bool ISelShouldIgnore; // Should ISel ignore this pattern.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid, const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, bool ignore, const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
- HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
+ HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity), ISelShouldIgnore(ignore),
ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
@@ -1078,6 +1079,7 @@ class PatternToMatch {
const std::vector<Record *> &getDstRegs() const { return Dstregs; }
StringRef getHwModeFeatures() const { return HwModeFeatures; }
int getAddedComplexity() const { return AddedComplexity; }
+ bool getISelShouldIgnore() const { return ISelShouldIgnore; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
@@ -1240,7 +1242,8 @@ class CodeGenDAGPatterns {
void ParseOnePattern(Record *TheDef, TreePattern &Pattern,
TreePattern &Result,
- const std::vector<Record *> &InstImpResults);
+ const std::vector<Record *> &InstImpResults,
+ bool ShouldIgnore = false);
void AddPatternToMatch(TreePattern *Pattern, PatternToMatch &&PTM);
void FindPatternInputsAndOutputs(
TreePattern &I, TreePatternNodePtr Pat,
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 25e302ce1ca46f..f379476eeeb59f 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -428,7 +428,7 @@ class GlobalISelEmitter final : public GlobalISelMatchTableExecutorEmitter {
/// Analyze pattern \p P, returning a matcher for it if possible.
/// Otherwise, return an Error explaining why we don't support it.
- Expected<RuleMatcher> runOnPattern(const PatternToMatch &P);
+ std::optional<Expected<RuleMatcher>> runOnPattern(const PatternToMatch &P);
void declareSubtargetFeature(Record *Predicate);
@@ -1901,7 +1901,11 @@ std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
-Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
+std::optional<Expected<RuleMatcher>> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
+ if (P.getISelShouldIgnore()) {
+ return {};
+ }
+
// Keep track of the matchers and actions to emit.
int Score = P.getPatternComplexity(CGP);
RuleMatcher M(P.getSrcRecord()->getLoc());
@@ -2412,10 +2416,11 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
++NumPatternTotal;
auto MatcherOrErr = runOnPattern(Pat);
+ if (!MatcherOrErr) continue; // skip without warning
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
- if (auto Err = MatcherOrErr.takeError()) {
+ if (auto Err = MatcherOrErr->takeError()) {
if (WarnOnSkippedPatterns) {
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Skipped pattern: " + toString(std::move(Err)));
@@ -2427,13 +2432,13 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
}
if (RuleCoverage) {
- if (RuleCoverage->isCovered(MatcherOrErr->getRuleID()))
+ if (RuleCoverage->isCovered((*MatcherOrErr)->getRuleID()))
++NumPatternsTested;
else
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Pattern is not covered by a test");
}
- Rules.push_back(std::move(MatcherOrErr.get()));
+ Rules.push_back(std::move(MatcherOrErr->get()));
postProcessRule(Rules.back());
}
>From d49299eaf49dc9881ab471c3165f41a9c026d792 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Thu, 18 Apr 2024 19:15:54 -0400
Subject: [PATCH 4/8] [TableGen] clang-format for ShouldIgnore
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 8 ++++----
llvm/utils/TableGen/Common/CodeGenDAGPatterns.h | 7 ++++---
llvm/utils/TableGen/DAGISelEmitter.cpp | 4 ++--
llvm/utils/TableGen/GlobalISelEmitter.cpp | 6 ++++--
4 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 7bccdbe8b5d724..a75e2bc4d116d2 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4408,10 +4408,10 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
return;
}
- PatternsToMatch.emplace_back(P.getSrcRecord(), P.getPredicates(),
- std::move(NewSrc), std::move(NewDst),
- P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
+ PatternsToMatch.emplace_back(
+ P.getSrcRecord(), P.getPredicates(), std::move(NewSrc),
+ std::move(NewDst), P.getDstRegs(), P.getAddedComplexity(),
+ Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 6a85a579658892..723e042b3c199f 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1064,11 +1064,12 @@ class PatternToMatch {
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid, bool ignore, const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, bool ignore,
+ const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
- HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity), ISelShouldIgnore(ignore),
- ID(uid) {}
+ HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
+ ISelShouldIgnore(ignore), ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
ListInit *getPredicates() const { return Predicates; }
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index 4fbeafdc2355fb..b1a3acf4b2f451 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -171,10 +171,10 @@ void DAGISelEmitter::run(raw_ostream &OS) {
const TreePatternNode &Dst = PTM.getDstPattern();
if (!Dst.isLeaf()) {
const Record *Op = Dst.getOperator();
- const bool shouldIgnore =
+ const bool ShouldIgnore =
Op->isSubClassOf("Instruction") &&
CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
- if (shouldIgnore)
+ if (ShouldIgnore)
continue;
}
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index f379476eeeb59f..aec16ecdcb6770 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -1901,7 +1901,8 @@ std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
-std::optional<Expected<RuleMatcher>> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
+std::optional<Expected<RuleMatcher>>
+GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
if (P.getISelShouldIgnore()) {
return {};
}
@@ -2416,7 +2417,8 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
++NumPatternTotal;
auto MatcherOrErr = runOnPattern(Pat);
- if (!MatcherOrErr) continue; // skip without warning
+ if (!MatcherOrErr)
+ continue; // skip without warning
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
>From c10ab41689367050919dedc72cf920fd037bade8 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 09:24:01 -0400
Subject: [PATCH 5/8] [TableGen] style and names for GISelShouldIgnore
---
.../include/llvm/Target/TargetSelectionDAG.td | 2 +-
.../GlobalISelEmitterSkippedPatterns.td | 2 +-
.../TableGen/Common/CodeGenDAGPatterns.cpp | 6 +++---
.../TableGen/Common/CodeGenDAGPatterns.h | 10 +++++-----
llvm/utils/TableGen/GlobalISelEmitter.cpp | 19 +++++++------------
5 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index eeef17674eac55..1684b424e3b442 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -1979,7 +1979,7 @@ class Pattern<dag patternToMatch, list<dag> resultInstrs> {
list<dag> ResultInstrs = resultInstrs;
list<Predicate> Predicates = []; // See class Instruction in Target.td.
int AddedComplexity = 0; // See class Instruction in Target.td.
- bit ISelShouldIgnore = 0;
+ bit GISelShouldIgnore = 0;
}
// Pat - A simple (but common) form of a pattern, which produces a simple result
diff --git a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
index 5554b6f9000535..d85e43c6bfb450 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSkippedPatterns.td
@@ -26,7 +26,7 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
//===- Bail out when we define a variable twice wrt complex suboperands. -===//
#ifdef IGNORE
-let ISelShouldIgnore = 1 in
+let GISelShouldIgnore = 1 in
#endif
// CHECK0-NOT: warning: Skipped pattern: Error: {{.*}}
// CHECK: warning: Skipped pattern: Error: Complex suboperand x referenced by different operands: complex_rr:x:y and complex_rr:x:z.
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index a75e2bc4d116d2..88d353e89a4614 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4379,7 +4379,7 @@ void CodeGenDAGPatterns::ParsePatterns() {
InstResults, InstImpResults);
ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
- CurPattern->getValueAsBit("ISelShouldIgnore"));
+ CurPattern->getValueAsBit("GISelShouldIgnore"));
}
}
@@ -4411,7 +4411,7 @@ void CodeGenDAGPatterns::ExpandHwModeBasedTypes() {
PatternsToMatch.emplace_back(
P.getSrcRecord(), P.getPredicates(), std::move(NewSrc),
std::move(NewDst), P.getDstRegs(), P.getAddedComplexity(),
- Record::getNewUID(Records), P.getISelShouldIgnore(), Check);
+ Record::getNewUID(Records), P.getGISelShouldIgnore(), Check);
};
for (PatternToMatch &P : Copy) {
@@ -4782,7 +4782,7 @@ void CodeGenDAGPatterns::GenerateVariants() {
Variant, PatternsToMatch[i].getDstPatternShared(),
PatternsToMatch[i].getDstRegs(),
PatternsToMatch[i].getAddedComplexity(), Record::getNewUID(Records),
- PatternsToMatch[i].getISelShouldIgnore(),
+ PatternsToMatch[i].getGISelShouldIgnore(),
PatternsToMatch[i].getHwModeFeatures());
}
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 723e042b3c199f..7f94db0b7d5d76 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -1057,9 +1057,9 @@ class PatternToMatch {
TreePatternNodePtr DstPattern; // Resulting pattern.
std::vector<Record *> Dstregs; // Physical register defs being matched.
std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- bool ISelShouldIgnore; // Should ISel ignore this pattern.
- unsigned ID; // Unique ID for the record.
+ int AddedComplexity; // Add to matching pattern complexity.
+ bool GISelShouldIgnore; // Should GlobalISel ignore importing this pattern.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
@@ -1069,7 +1069,7 @@ class PatternToMatch {
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
- ISelShouldIgnore(ignore), ID(uid) {}
+ GISelShouldIgnore(ignore), ID(uid) {}
Record *getSrcRecord() const { return SrcRecord; }
ListInit *getPredicates() const { return Predicates; }
@@ -1080,7 +1080,7 @@ class PatternToMatch {
const std::vector<Record *> &getDstRegs() const { return Dstregs; }
StringRef getHwModeFeatures() const { return HwModeFeatures; }
int getAddedComplexity() const { return AddedComplexity; }
- bool getISelShouldIgnore() const { return ISelShouldIgnore; }
+ bool getGISelShouldIgnore() const { return GISelShouldIgnore; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index aec16ecdcb6770..78abf80e7aecb3 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -428,7 +428,7 @@ class GlobalISelEmitter final : public GlobalISelMatchTableExecutorEmitter {
/// Analyze pattern \p P, returning a matcher for it if possible.
/// Otherwise, return an Error explaining why we don't support it.
- std::optional<Expected<RuleMatcher>> runOnPattern(const PatternToMatch &P);
+ Expected<RuleMatcher> runOnPattern(const PatternToMatch &P);
void declareSubtargetFeature(Record *Predicate);
@@ -1901,12 +1901,7 @@ std::optional<CodeGenSubRegIndex *> GlobalISelEmitter::inferSubRegIndexForNode(
return CGRegs.getSubRegIdx(SubRegInit->getDef());
}
-std::optional<Expected<RuleMatcher>>
-GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
- if (P.getISelShouldIgnore()) {
- return {};
- }
-
+Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
// Keep track of the matchers and actions to emit.
int Score = P.getPatternComplexity(CGP);
RuleMatcher M(P.getSrcRecord()->getLoc());
@@ -2416,13 +2411,13 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
for (const PatternToMatch &Pat : CGP.ptms()) {
++NumPatternTotal;
- auto MatcherOrErr = runOnPattern(Pat);
- if (!MatcherOrErr)
+ if (Pat.getGISelShouldIgnore())
continue; // skip without warning
+ auto MatcherOrErr = runOnPattern(Pat);
// The pattern analysis can fail, indicating an unsupported pattern.
// Report that if we've been asked to do so.
- if (auto Err = MatcherOrErr->takeError()) {
+ if (auto Err = MatcherOrErr.takeError()) {
if (WarnOnSkippedPatterns) {
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Skipped pattern: " + toString(std::move(Err)));
@@ -2434,13 +2429,13 @@ void GlobalISelEmitter::run(raw_ostream &OS) {
}
if (RuleCoverage) {
- if (RuleCoverage->isCovered((*MatcherOrErr)->getRuleID()))
+ if (RuleCoverage->isCovered(MatcherOrErr->getRuleID()))
++NumPatternsTested;
else
PrintWarning(Pat.getSrcRecord()->getLoc(),
"Pattern is not covered by a test");
}
- Rules.push_back(std::move(MatcherOrErr->get()));
+ Rules.push_back(std::move(MatcherOrErr.get()));
postProcessRule(Rules.back());
}
>From e9287d30404a916ced37b64ee1f1f674f15aa967 Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 10:01:41 -0400
Subject: [PATCH 6/8] [TableGen] Add .inc test for GISelShouldIgnore
This test ensures the MatchTable has no patterns marked with GISelShouldIgnore.
---
llvm/test/TableGen/GlobalISelEmitterVariadic.td | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
index ba6a93bd4837f2..05da0cbc36f9cd 100644
--- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td
+++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td
@@ -1,4 +1,5 @@
// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
+// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - -DIGNORE | FileCheck %s --check-prefix=CHECK0
include "llvm/Target/Target.td"
include "GlobalISelEmitterCommon.td"
@@ -17,11 +18,20 @@ def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
def : Pat<(build_vector GPR32:$src1),
(ONE GPR32:$src1)> {
let AddedComplexity = 1000;
+#ifdef IGNORE
+ let GISelShouldIgnore = 1;
+#endif
}
+#ifdef IGNORE
+let GISelShouldIgnore = 1 in
+#endif
def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
(TWO GPR32:$src1, GPR32:$src2)>;
+// CHECK0: constexpr static uint8_t MatchTable0[] = {
+// CHECK0-NEXT: GIM_Reject,
+// CHECK0-NEXT:}; // Size: 1 bytes
// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4([[NEXT_OPCODE_LABEL:[0-9]+]]),
// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 //
>From 5fbc5eeb72f5d4bf375cffcc204c28ea5d7ac5ca Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 10:12:30 -0400
Subject: [PATCH 7/8] [TableGen] Remove ShouldIgnore bit on Instruction ; not
needed for dagisel
---
llvm/include/llvm/Target/Target.td | 4 --
.../TableGen/DAGISelEmitter-shouldignore.td | 37 -------------------
.../TableGen/Common/CodeGenInstruction.cpp | 1 -
.../TableGen/Common/CodeGenInstruction.h | 1 -
llvm/utils/TableGen/DAGISelEmitter.cpp | 15 +-------
5 files changed, 1 insertion(+), 57 deletions(-)
delete mode 100644 llvm/test/TableGen/DAGISelEmitter-shouldignore.td
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 61dc04595b62b9..1f7dc6922f13e4 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -777,10 +777,6 @@ class Instruction : InstructionEncoding {
/// SelectionDAG can.
bit FastISelShouldIgnore = false;
- /// Should DAGISel ignore this instruction. In cases where lowering may
- /// be done elsewhere or is unneeded, DAGISel may skip over them.
- bit DAGISelShouldIgnore = false;
-
/// HasPositionOrder: Indicate tablegen to sort the instructions by record
/// ID, so that instruction that is defined earlier can be sorted earlier
/// in the assembly matching table.
diff --git a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td b/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
deleted file mode 100644
index 61dac212a716e0..00000000000000
--- a/llvm/test/TableGen/DAGISelEmitter-shouldignore.td
+++ /dev/null
@@ -1,37 +0,0 @@
-// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s -DIGNORE | FileCheck %s
-// RUN: llvm-tblgen --gen-dag-isel -I %p/../../include %s --match-prefix=CHECK_LOOK | FileCheck --check-prefix=CHECK_LOOK %s
-
-include "llvm/Target/Target.td"
-def ISA : InstrInfo;
-def Tgt : Target { let InstructionSet = ISA; }
-def R0 : Register<"r0"> { let Namespace = "Tgt"; }
-def RC : RegisterClass<"Tgt", [i32], 32, (add R0)>;
-def Op : RegisterOperand<RC>;
-
-class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
- let Namespace = "Tgt";
- let OutOperandList = OOps;
- let InOperandList = IOps;
- let Pattern = Pat;
-}
-
-#ifdef IGNORE
-let DAGISelShouldIgnore = 1 in
-def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt), []>;
-// CHECK: static const unsigned char MatcherTable[] = {
-// CHECK-NEXT: 0
-// CHECK-NEXT: }; // Total Array size is 1 bytes
-#else
-def ADD : I<(outs Op:$rd), (ins Op:$rs, Op:$rt),
- [(set Op:$rd, (add Op:$rs, Op:$rt))]>;
-// CHECK_LOOK:static const unsigned char MatcherTable[] = {
-// CHECK_LOOK-NEXT:/* 0*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
-// CHECK_LOOK-NEXT:/* 3*/ OPC_RecordChild0, // #0 = $rs
-// CHECK_LOOK-NEXT:/* 4*/ OPC_RecordChild1, // #1 = $rt
-// CHECK_LOOK-NEXT:/* 5*/ OPC_MorphNodeTo1None, TARGET_VAL(Tgt::ADD),
-// CHECK_LOOK-NEXT: MVT::i32, 2/*#Ops*/, 0, 1,
-// CHECK_LOOK-NEXT:// Src: (add:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt) - Complexity = {{[0-9]+}}
-// CHECK_LOOK-NEXT:// Dst: (ADD:{ *:[i32] } Op:{ *:[i32] }:$rs, Op:{ *:[i32] }:$rt)
-// CHECK_LOOK-NEXT: 0
-// CHECK_LOOK-NEXT:}; // Total Array size is 13 bytes
-#endif
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index a76efb76bfc319..18a4e7b0f18b23 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -465,7 +465,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isConvergent = R->getValueAsBit("isConvergent");
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
FastISelShouldIgnore = R->getValueAsBit("FastISelShouldIgnore");
- DAGISelShouldIgnore = R->getValueAsBit("DAGISelShouldIgnore");
variadicOpsAreDefs = R->getValueAsBit("variadicOpsAreDefs");
isAuthenticated = R->getValueAsBit("isAuthenticated");
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index c36bfba245f66b..b658259b4892ee 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -282,7 +282,6 @@ class CodeGenInstruction {
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
bool FastISelShouldIgnore : 1;
- bool DAGISelShouldIgnore : 1;
bool hasChain : 1;
bool hasChain_Inferred : 1;
bool variadicOpsAreDefs : 1;
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index b1a3acf4b2f451..b43a8e659dd9c5 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -165,21 +165,8 @@ void DAGISelEmitter::run(raw_ostream &OS) {
// Add all the patterns to a temporary list so we can sort them.
Records.startTimer("Sort patterns");
std::vector<const PatternToMatch *> Patterns;
- for (const PatternToMatch &PTM : CGP.ptms()) {
-
- // Disable import of patterns marked as ignore.
- const TreePatternNode &Dst = PTM.getDstPattern();
- if (!Dst.isLeaf()) {
- const Record *Op = Dst.getOperator();
- const bool ShouldIgnore =
- Op->isSubClassOf("Instruction") &&
- CGP.getTargetInfo().getInstruction(Op).DAGISelShouldIgnore;
- if (ShouldIgnore)
- continue;
- }
-
+ for (const PatternToMatch &PTM : CGP.ptms())
Patterns.push_back(&PTM);
- }
// We want to process the matches in order of minimal cost. Sort the patterns
// so the least cost one is at the start.
>From 5a509f7445a6b6bee10f4cf8cd114cb94e45249b Mon Sep 17 00:00:00 2001
From: Joe Fernau <joe.fernau at amd.com>
Date: Fri, 19 Apr 2024 11:21:38 -0400
Subject: [PATCH 8/8] [TableGen] Move pattern import disabling earlier
---
llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 88d353e89a4614..72bdb2721832ac 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -4378,8 +4378,8 @@ void CodeGenDAGPatterns::ParsePatterns() {
FindPatternInputsAndOutputs(Pattern, Pattern.getTree(j), InstInputs,
InstResults, InstImpResults);
- ParseOnePattern(CurPattern, Pattern, Result, InstImpResults,
- CurPattern->getValueAsBit("GISelShouldIgnore"));
+ if (CurPattern->getValueAsBit("GISelShouldIgnore"))
+ ParseOnePattern(CurPattern, Pattern, Result, InstImpResults);
}
}
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