[llvm] 46957a1 - [InstCombine] Fix incorrect fshr to fshl transform

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2024-04-19T14:02:22+09:00
New Revision: 46957a138dea339799059ea5bf032e40042ff185

URL: https://github.com/llvm/llvm-project/commit/46957a138dea339799059ea5bf032e40042ff185
DIFF: https://github.com/llvm/llvm-project/commit/46957a138dea339799059ea5bf032e40042ff185.diff

LOG: [InstCombine] Fix incorrect fshr to fshl transform

This transform is only valid if the (modular) shift amount is not
zero.

Proof: https://alive2.llvm.org/ce/z/WBxn-x

Fixes https://github.com/llvm/llvm-project/issues/89338.

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    llvm/test/Transforms/InstCombine/fsh.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index aa547565bd0859..e7a2f54f86809f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -1988,7 +1988,10 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
       // is not entirely arbitrary. For historical reasons, the backend may
       // recognize rotate left patterns but miss rotate right patterns.
       if (IID == Intrinsic::fshr) {
-        // fshr X, Y, C --> fshl X, Y, (BitWidth - C)
+        // fshr X, Y, C --> fshl X, Y, (BitWidth - C) if C is not zero.
+        if (!isKnownNonZero(ShAmtC, SQ.getWithInstruction(II)))
+          return nullptr;
+
         Constant *LeftShiftC = ConstantExpr::getSub(WidthC, ShAmtC);
         Module *Mod = II->getModule();
         Function *Fshl = Intrinsic::getDeclaration(Mod, Intrinsic::fshl, Ty);

diff  --git a/llvm/test/Transforms/InstCombine/fsh.ll b/llvm/test/Transforms/InstCombine/fsh.ll
index 3bd44ece306b9a..505a2283672548 100644
--- a/llvm/test/Transforms/InstCombine/fsh.ll
+++ b/llvm/test/Transforms/InstCombine/fsh.ll
@@ -1002,10 +1002,9 @@ define <2 x i32> @fsh_unary_shuffle_ops_partial_widening(<3 x i32> %x, <2 x i32>
   ret <2 x i32> %r
 }
 
-; FIXME: This is a miscompile.
 define <2 x i32> @fshr_vec_zero_elem(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @fshr_vec_zero_elem(
-; CHECK-NEXT:    [[FSH:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> <i32 30, i32 0>)
+; CHECK-NEXT:    [[FSH:%.*]] = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> <i32 2, i32 0>)
 ; CHECK-NEXT:    ret <2 x i32> [[FSH]]
 ;
   %fsh = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 2, i32 0>)