[llvm] [RISCV] Add test case for CASE_VFMA_CHANGE_OPCODE_VV to handle MF4 pseudos (PR #88947)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 18 06:13:03 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/88947
>From e5f95c62087c8425015a14a684be39ac4d53f508 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 16 Apr 2024 11:00:05 -0700
Subject: [PATCH 1/2] [RISCV] Fix CASE_VFMA_CHANGE_OPCODE_VV to handle MF4
pseudos
---
.../RISCV/rvv/change-vmadd-to-vmacc.mir | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir b/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
new file mode 100644
index 00000000000000..81d36890ccae79
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -run-pass=machine-cse -o - %s | FileCheck %s
+
+---
+name: test
+alignment: 4
+tracksRegLiveness: true
+constants:
+ - id: 0
+ value: half 0xHC200
+ alignment: 2
+ isTargetSpecific: false
+ - id: 1
+ value: half 0xH3C00
+ alignment: 2
+ isTargetSpecific: false
+ - id: 2
+ value: half 0xHB800
+ alignment: 2
+ isTargetSpecific: false
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test
+ ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.0
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI killed [[LUI]], target-flags(riscv-lo) %const.0
+ ; CHECK-NEXT: [[PseudoVLSE16_V_MF4_:%[0-9]+]]:vr = PseudoVLSE16_V_MF4 $noreg, killed [[ADDI]], $x0, 2, 4 /* e16 */, 3 /* ta, ma */ :: (load (s16) from constant-pool)
+ ; CHECK-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.1
+ ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI killed [[LUI1]], target-flags(riscv-lo) %const.1
+ ; CHECK-NEXT: [[PseudoVLSE16_V_MF4_1:%[0-9]+]]:vr = PseudoVLSE16_V_MF4 $noreg, killed [[ADDI1]], $x0, 2, 4 /* e16 */, 3 /* ta, ma */ :: (load (s16) from constant-pool)
+ ; CHECK-NEXT: [[PseudoVFRSQRT7_V_MF4_E16_:%[0-9]+]]:vr = nofpexcept PseudoVFRSQRT7_V_MF4_E16 $noreg, killed [[PseudoVLSE16_V_MF4_1]], 2, 4 /* e16 */, 3 /* ta, ma */
+ ; CHECK-NEXT: [[PseudoVFMADD_VV_MF4_E16_:%[0-9]+]]:vr = ninf contract afn nofpexcept PseudoVFMADD_VV_MF4_E16 [[PseudoVFRSQRT7_V_MF4_E16_]], [[PseudoVFRSQRT7_V_MF4_E16_]], killed [[PseudoVLSE16_V_MF4_]], 7, 2, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
+ ; CHECK-NEXT: $v8 = COPY [[PseudoVFMADD_VV_MF4_E16_]]
+ ; CHECK-NEXT: PseudoRET implicit $v8
+ %0:gpr = LUI target-flags(riscv-hi) %const.0
+ %1:gpr = ADDI killed %0, target-flags(riscv-lo) %const.0
+ %2:vr = PseudoVLSE16_V_MF4 $noreg, killed %1, $x0, 2, 4 /* e16 */, 3 :: (load (s16) from constant-pool)
+ %3:gpr = LUI target-flags(riscv-hi) %const.1
+ %4:gpr = ADDI killed %3, target-flags(riscv-lo) %const.1
+ %5:vr = PseudoVLSE16_V_MF4 $noreg, killed %4, $x0, 2, 4 /* e16 */, 3 :: (load (s16) from constant-pool)
+ %6:vr = nofpexcept PseudoVFRSQRT7_V_MF4_E16 $noreg, killed %5, 2, 4 /* e16 */, 3 /* ta, ma */
+ %7:vr = ninf contract afn nofpexcept PseudoVFMADD_VV_MF4_E16 %6, %6, killed %2, 7, 2, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
+ $v8 = COPY %7
+ PseudoRET implicit $v8
+
+...
>From a84f9c097dfc00c922f56d325d3ab39daa86b014 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Wed, 17 Apr 2024 10:53:02 -0700
Subject: [PATCH 2/2] fixup! use llvm test
---
.../RISCV/rvv/change-vmadd-to-vmacc.mir | 45 -------------------
llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll | 22 +++++++++
2 files changed, 22 insertions(+), 45 deletions(-)
delete mode 100644 llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
diff --git a/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir b/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
deleted file mode 100644
index 81d36890ccae79..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
+++ /dev/null
@@ -1,45 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-# RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -run-pass=machine-cse -o - %s | FileCheck %s
-
----
-name: test
-alignment: 4
-tracksRegLiveness: true
-constants:
- - id: 0
- value: half 0xHC200
- alignment: 2
- isTargetSpecific: false
- - id: 1
- value: half 0xH3C00
- alignment: 2
- isTargetSpecific: false
- - id: 2
- value: half 0xHB800
- alignment: 2
- isTargetSpecific: false
-body: |
- bb.0:
- ; CHECK-LABEL: name: test
- ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.0
- ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI killed [[LUI]], target-flags(riscv-lo) %const.0
- ; CHECK-NEXT: [[PseudoVLSE16_V_MF4_:%[0-9]+]]:vr = PseudoVLSE16_V_MF4 $noreg, killed [[ADDI]], $x0, 2, 4 /* e16 */, 3 /* ta, ma */ :: (load (s16) from constant-pool)
- ; CHECK-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.1
- ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI killed [[LUI1]], target-flags(riscv-lo) %const.1
- ; CHECK-NEXT: [[PseudoVLSE16_V_MF4_1:%[0-9]+]]:vr = PseudoVLSE16_V_MF4 $noreg, killed [[ADDI1]], $x0, 2, 4 /* e16 */, 3 /* ta, ma */ :: (load (s16) from constant-pool)
- ; CHECK-NEXT: [[PseudoVFRSQRT7_V_MF4_E16_:%[0-9]+]]:vr = nofpexcept PseudoVFRSQRT7_V_MF4_E16 $noreg, killed [[PseudoVLSE16_V_MF4_1]], 2, 4 /* e16 */, 3 /* ta, ma */
- ; CHECK-NEXT: [[PseudoVFMADD_VV_MF4_E16_:%[0-9]+]]:vr = ninf contract afn nofpexcept PseudoVFMADD_VV_MF4_E16 [[PseudoVFRSQRT7_V_MF4_E16_]], [[PseudoVFRSQRT7_V_MF4_E16_]], killed [[PseudoVLSE16_V_MF4_]], 7, 2, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
- ; CHECK-NEXT: $v8 = COPY [[PseudoVFMADD_VV_MF4_E16_]]
- ; CHECK-NEXT: PseudoRET implicit $v8
- %0:gpr = LUI target-flags(riscv-hi) %const.0
- %1:gpr = ADDI killed %0, target-flags(riscv-lo) %const.0
- %2:vr = PseudoVLSE16_V_MF4 $noreg, killed %1, $x0, 2, 4 /* e16 */, 3 :: (load (s16) from constant-pool)
- %3:gpr = LUI target-flags(riscv-hi) %const.1
- %4:gpr = ADDI killed %3, target-flags(riscv-lo) %const.1
- %5:vr = PseudoVLSE16_V_MF4 $noreg, killed %4, $x0, 2, 4 /* e16 */, 3 :: (load (s16) from constant-pool)
- %6:vr = nofpexcept PseudoVFRSQRT7_V_MF4_E16 $noreg, killed %5, 2, 4 /* e16 */, 3 /* ta, ma */
- %7:vr = ninf contract afn nofpexcept PseudoVFMADD_VV_MF4_E16 %6, %6, killed %2, 7, 2, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
- $v8 = COPY %7
- PseudoRET implicit $v8
-
-...
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
index 6e3ee2a312185d..8a72b2ddafaca4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
@@ -35,6 +35,28 @@ define <vscale x 1 x half> @vfmadd_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x
ret <vscale x 1 x half> %vd
}
+define <vscale x 1 x half> @vfmadd_vv_nxv1f16_commuted(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {
+; ZVFH-LABEL: vfmadd_vv_nxv1f16_commuted:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmacc.vv v8, v10, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: vfmadd_vv_nxv1f16_commuted:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v9, v8, v11
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: ret
+ %vd = call <vscale x 1 x half> @llvm.fma.v1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %vc, <vscale x 1 x half> %va)
+ ret <vscale x 1 x half> %vd
+}
+
define <vscale x 1 x half> @vfmadd_vf_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, half %c) {
; ZVFH-LABEL: vfmadd_vf_nxv1f16:
; ZVFH: # %bb.0:
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