[llvm] [Exegesis][RISCV] Add RISCV support for llvm-exegesis (PR #89047)

[Aiden Grossman via llvm-commits]

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@@ -207,14 +208,16 @@ class BenchmarkCodeStreamer : public MCStreamer, public AsmCommentConsumer {
                     Align ByteAlignment, SMLoc Loc) override {}
 
   unsigned findRegisterByName(const StringRef RegName) const {
+    if (unsigned Reg = Target.findRegisterByName(RegName))
+      return Reg;
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boomanaiden154 wrote:

Why is this just tacked on here? If there's registers missing, they should probably be added to the `RegNameToRegNo` map by modifying `LlvmState::createRegNameToRegNoMapping`. If this works better and covers all/more cases though, it might be something we want to do cleanup on, but that can probably be done in a separate PR along with the additional cleanup.

https://github.com/llvm/llvm-project/pull/89047