[llvm] [RISCV] Support postRA vsetvl insertion pass (PR #70549)

[Piyou Chen via llvm-commits]

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@@ -505,13 +548,15 @@ class VSETVLIInfo {
   bool getTailAgnostic() const { return TailAgnostic; }
   bool getMaskAgnostic() const { return MaskAgnostic; }
 
-  bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const {
+  bool hasNonZeroAVL(const MachineRegisterInfo &MRI,
+                     const LiveIntervals *LIS) const {
     if (hasAVLImm())
       return getAVLImm() > 0;
     if (hasAVLReg()) {
       if (getAVLReg() == RISCV::X0)
         return true;
-      if (MachineInstr *MI = MRI.getVRegDef(getAVLReg());
+      if (MachineInstr *MI =
+              getReachingDefMI(getAVLReg(), (MachineInstr *)nullptr, &MRI, LIS);
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BeMg wrote:

Create a pr to keep the AVLRegDef inside VSETVLInfo. https://github.com/llvm/llvm-project/pull/89180 

https://github.com/llvm/llvm-project/pull/70549