[clang] [llvm] [arm] Support reserving r4 and r5 alongside r9 (PR #88981)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 17 10:43:39 PDT 2024
https://github.com/benisxdxd updated https://github.com/llvm/llvm-project/pull/88981
>From 24453d337187e43a5901337681098d2e7520b740 Mon Sep 17 00:00:00 2001
From: benisxdxd <164242179+benisxdxd at users.noreply.github.com>
Date: Tue, 16 Apr 2024 23:38:26 +0300
Subject: [PATCH 1/2] [arm] Support reserving r4 and r5 alongside r9
---
clang/include/clang/Driver/Options.td | 4 ++++
clang/lib/Driver/ToolChains/Arch/ARM.cpp | 8 +++++++-
llvm/lib/Target/ARM/ARM.td | 10 ++++++++++
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 7 ++++++-
llvm/lib/Target/ARM/ARMSubtarget.h | 8 ++++++++
5 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index e24626913add76..bc7f51d72a3c72 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4754,6 +4754,10 @@ def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,
def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,
HelpText<"Allow generation of complex IT blocks.">;
def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
+def ffixed_r4 : Flag<["-"], "ffixed-r4">, Group<m_arm_Features_Group>,
+ HelpText<"Reserve the r4 register (ARM only)">;
+def ffixed_r5 : Flag<["-"], "ffixed-r5">, Group<m_arm_Features_Group>,
+ HelpText<"Reserve the r5 register (ARM only)">;
def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,
HelpText<"Reserve the r9 register (ARM only)">;
def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index a68368c4758651..4c5d1fd55d1f82 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -915,8 +915,14 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
}
// llvm does not support reserving registers in general. There is support
- // for reserving r9 on ARM though (defined as a platform-specific register
+ // for reserving r4,r5 and r9 on ARM though (defined as a platform-specific register
// in ARM EABI).
+ if (Args.hasArg(options::OPT_ffixed_r4))
+ Features.push_back("+reserve-r4");
+
+ if (Args.hasArg(options::OPT_ffixed_r5))
+ Features.push_back("+reserve-r5");
+
if (Args.hasArg(options::OPT_ffixed_r9))
Features.push_back("+reserve-r9");
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 66596dbda83c95..782e6c5dfc091a 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -477,6 +477,16 @@ def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
"Reserve R9, making it unavailable"
" as GPR">;
+// True if R4 is not available as a general purpose register.
+def FeatureReserveR4 : SubtargetFeature<"reserve-r4", "ReserveR4", "true",
+ "Reserve R4, making it unavailable"
+ " as GPR">;
+
+// True if R5 is not available as a general purpose register.
+def FeatureReserveR5 : SubtargetFeature<"reserve-r5", "ReserveR5", "true",
+ "Reserve R5, making it unavailable"
+ " as GPR">;
+
// True if MOVT / MOVW pairs are not used for materialization of
// 32-bit imms (including global addresses).
def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 9adf758b46c481..81e16239d94008 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -211,7 +211,12 @@ getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, STI.getFramePointerReg());
if (hasBasePointer(MF))
markSuperRegs(Reserved, BasePtr);
- // Some targets reserve R9.
+
+ // Some targets reserve R4, R5 or R9.
+ if (STI.isReserveR4())
+ markSuperRegs(Reserved, ARM::R4);
+ if (STI.isReserveR5())
+ markSuperRegs(Reserved, ARM::R5);
if (STI.isR9Reserved())
markSuperRegs(Reserved, ARM::R9);
// Reserve D16-D31 if the subtarget doesn't support them.
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 497ae160fde281..04f6abeba82f91 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -441,6 +441,14 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
}
+ bool isR4Reserved() const {
+ return ReserveR4;
+ }
+
+ bool isR5Reserved() const {
+ return ReserveR5;
+ }
+
MCPhysReg getFramePointerReg() const {
if (isTargetDarwin() ||
(!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
>From 229211f5c22f6cc06aa8fb644dd7fb6c3a222b17 Mon Sep 17 00:00:00 2001
From: benisxdxd <164242179+benisxdxd at users.noreply.github.com>
Date: Wed, 17 Apr 2024 20:43:32 +0300
Subject: [PATCH 2/2] Fix isRegReserved mixup and small test
---
clang/test/Driver/arm-fixed-r9.c | 4 ----
clang/test/Driver/arm-fixed-regs.c | 14 ++++++++++++++
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 4 ++--
3 files changed, 16 insertions(+), 6 deletions(-)
delete mode 100644 clang/test/Driver/arm-fixed-r9.c
create mode 100644 clang/test/Driver/arm-fixed-regs.c
diff --git a/clang/test/Driver/arm-fixed-r9.c b/clang/test/Driver/arm-fixed-r9.c
deleted file mode 100644
index 74ac336bd7f01e..00000000000000
--- a/clang/test/Driver/arm-fixed-r9.c
+++ /dev/null
@@ -1,4 +0,0 @@
-// RUN: %clang -target arm-none-gnueabi -ffixed-r9 -### %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-FIXED-R9 < %t %s
-
-// CHECK-FIXED-R9: "-target-feature" "+reserve-r9"
diff --git a/clang/test/Driver/arm-fixed-regs.c b/clang/test/Driver/arm-fixed-regs.c
new file mode 100644
index 00000000000000..3d4857bbd2d6c9
--- /dev/null
+++ b/clang/test/Driver/arm-fixed-regs.c
@@ -0,0 +1,14 @@
+// RUN: %clang -target arm-none-gnueabi -ffixed-r9 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-R9 < %t %s
+
+// CHECK-FIXED-R9: "-target-feature" "+reserve-r9"
+
+// RUN: %clang -target arm-none-gnueabi -ffixed-r4 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-R4 < %t %s
+
+// CHECK-FIXED-R4: "-target-feature" "+reserve-r4"
+
+// RUN: %clang -target arm-none-gnueabi -ffixed-r5 -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-FIXED-R5 < %t %s
+
+// CHECK-FIXED-R5: "-target-feature" "+reserve-r5"
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 81e16239d94008..f2e2c6265451d6 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -213,9 +213,9 @@ getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, BasePtr);
// Some targets reserve R4, R5 or R9.
- if (STI.isReserveR4())
+ if (STI.isR4Reserved())
markSuperRegs(Reserved, ARM::R4);
- if (STI.isReserveR5())
+ if (STI.isR5Reserved())
markSuperRegs(Reserved, ARM::R5);
if (STI.isR9Reserved())
markSuperRegs(Reserved, ARM::R9);
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