[llvm] [RISCV] Fix CASE_VFMA_CHANGE_OPCODE_VV to handle MF4 pseudos (PR #88947)

[Michael Maitland via llvm-commits]

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/88947

This was a mistake that I did not realize and we did not have coverage for.

>From ecea7aade095b0b042147978da5e76d1e12f5da4 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 16 Apr 2024 11:00:05 -0700
Subject: [PATCH] [RISCV] Fix CASE_VFMA_CHANGE_OPCODE_VV to handle MF4 pseudos

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp      |  2 +-
 .../RISCV/rvv/change-vmadd-to-vmacc.mir       | 45 +++++++++++++++++++
 2 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 508f607fab20fd..ccabee2e32c4b0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2950,7 +2950,7 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
   CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
 
 #define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP)                               \
-  CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E16)                     \
+  CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16)                     \
   CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32)                     \
   CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)
 
diff --git a/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir b/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
new file mode 100644
index 00000000000000..81d36890ccae79
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/change-vmadd-to-vmacc.mir
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+f,+d -riscv-v-vector-bits-min=128 -run-pass=machine-cse -o - %s | FileCheck %s
+
+---
+name:   test
+alignment:       4
+tracksRegLiveness: true
+constants:
+  - id:              0
+    value:           half 0xHC200
+    alignment:       2
+    isTargetSpecific: false
+  - id:              1
+    value:           half 0xH3C00
+    alignment:       2
+    isTargetSpecific: false
+  - id:              2
+    value:           half 0xHB800
+    alignment:       2
+    isTargetSpecific: false
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test
+    ; CHECK: [[LUI:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.0
+    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI killed [[LUI]], target-flags(riscv-lo) %const.0
+    ; CHECK-NEXT: [[PseudoVLSE16_V_MF4_:%[0-9]+]]:vr = PseudoVLSE16_V_MF4 $noreg, killed [[ADDI]], $x0, 2, 4 /* e16 */, 3 /* ta, ma */ :: (load (s16) from constant-pool)
+    ; CHECK-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI target-flags(riscv-hi) %const.1
+    ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI killed [[LUI1]], target-flags(riscv-lo) %const.1
+    ; CHECK-NEXT: [[PseudoVLSE16_V_MF4_1:%[0-9]+]]:vr = PseudoVLSE16_V_MF4 $noreg, killed [[ADDI1]], $x0, 2, 4 /* e16 */, 3 /* ta, ma */ :: (load (s16) from constant-pool)
+    ; CHECK-NEXT: [[PseudoVFRSQRT7_V_MF4_E16_:%[0-9]+]]:vr = nofpexcept PseudoVFRSQRT7_V_MF4_E16 $noreg, killed [[PseudoVLSE16_V_MF4_1]], 2, 4 /* e16 */, 3 /* ta, ma */
+    ; CHECK-NEXT: [[PseudoVFMADD_VV_MF4_E16_:%[0-9]+]]:vr = ninf contract afn nofpexcept PseudoVFMADD_VV_MF4_E16 [[PseudoVFRSQRT7_V_MF4_E16_]], [[PseudoVFRSQRT7_V_MF4_E16_]], killed [[PseudoVLSE16_V_MF4_]], 7, 2, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
+    ; CHECK-NEXT: $v8 = COPY [[PseudoVFMADD_VV_MF4_E16_]]
+    ; CHECK-NEXT: PseudoRET implicit $v8
+    %0:gpr = LUI target-flags(riscv-hi) %const.0
+    %1:gpr = ADDI killed %0, target-flags(riscv-lo) %const.0
+    %2:vr = PseudoVLSE16_V_MF4 $noreg, killed %1, $x0, 2, 4 /* e16 */, 3 :: (load (s16) from constant-pool)
+    %3:gpr = LUI target-flags(riscv-hi) %const.1
+    %4:gpr = ADDI killed %3, target-flags(riscv-lo) %const.1
+    %5:vr = PseudoVLSE16_V_MF4 $noreg, killed %4, $x0, 2, 4 /* e16 */, 3 :: (load (s16) from constant-pool)
+    %6:vr = nofpexcept PseudoVFRSQRT7_V_MF4_E16 $noreg, killed %5, 2, 4 /* e16 */, 3 /* ta, ma */
+    %7:vr = ninf contract afn nofpexcept PseudoVFMADD_VV_MF4_E16 %6, %6, killed %2, 7, 2, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
+    $v8 = COPY %7
+    PseudoRET implicit $v8
+
+...